Design of 5 th -Order Low-Pass Switched Capacitor Elliptic Filter Allen Waters, ECE 626

Size: px
Start display at page:

Download "Design of 5 th -Order Low-Pass Switched Capacitor Elliptic Filter Allen Waters, ECE 626"

Transcription

1 Design of 5 th -Order Low-Pass Switched Capacitor Elliptic Filter Allen Waters, ECE 626 I. INTRODUCTION Matlab and Cadence Spectre are used to design and simulate a 5 th -order low pass switched capacitor filter, operating at 15 MHz. The entire design process is documented and the filter is designed using ideal opamps and switches, achieving 0.2dB passband ripple (0-1 MHz) and -60dB stopband attenuation (2-7.5 MHz). The filter includes a first-order, high-q biquad, and low-q biquad stage, and is optimized for both dynamic range and area. Non-idealities including finite gain and bandwidth, charge injection, slew rate, and offset voltage are simulated. II. IDEAL DERIVATION IN MATLAB a. Architecture survey The specifications for the filter design are listed in Table I. Parameter Specification Sampling Frequency 15 MHz DC Gain 0 db Passband 0-1 MHz Passband Ripple < 0.2 db Stopband MHz Stopband Gain < -60 db Minimum Capacitor Size 0.05 pf Table I. Target Specifications Using the pre-defined filter tools in Matlab, we may compare the minimum filter order to achieve these specifications using different filter architectures. The filter is first designed in the 2 z 1 s-domain and then transformed to the z-domain using the bilinear transform, s. Since T z 1 this transformation causes frequency warping, it is necessary to pre-warp the frequency specifications before beginning the design. Appendix A includes the Matlab script used in the filter design, which illustrated this frequency warping. Architecture Minimum Order Butterworth 12 Chebyshev Type I 7 Chebyshev Type II 7 Elliptic 5 Table II. Architecture Requirements

2 b. Ideal response The filter order selections indicate that an elliptic filter will achieve the specifications in the smallest order. Elliptic filters have poor phase response; however, there are no phase specifications for the filter design, so an elliptic filter will be used to minimize area and complexity. Since the non-ideal simulations will suffer a performance hit, the 5 th -order elliptic filter was designed with the most headroom allowable, short of increasing to a 6 th -order design. It was designed to provide -62 db of stopband attenuation and only 0.12 db of passband ripple. The corresponding transfer function returned by Matlab is: ( z z z z z H z) z z z z z The frequency response from this ideal transfer function is plotted in Figures 1-3. Figure 1. Ideal frequency res ponse. Figure 2. Ideal passband ripple. Figure 3. Ideal stopband attenuation Figure 4. Pole-zero locations in Z-domain. Matlab is also used to break the 5 th -order transfer function up into separate contributions from multiple filter stages. Second-Order-Section conversion is used because lower-order filters are more manageable; furthermore, the pairs of poles and zeros in the Z-plane (see Figure 4) are perfect for a pair of bi-quad filters. These separate transfer functions are:

3 ; Q = 0.5 ; Q = ; Q = The quality factor of each filter is determined from the pole frequency, Q P. 2Re P There is one high-q stage (Q >> 1) and one low-q stage (Q 1), as well as a first-order stage. The Second-Order-Section conversion leaves a scalar G representing the overall gain of the system. This gain is distributed evenly among the three filter blocks. Note that this is not merely for convenience- by minimizing the gain in any of the three stages, the difference between capacitor values is minimized. This is beneficial when the filter is scaled for area, as addressed in Section IV. ; Figure 5. Cascaded filter design. Figure 6. Linear, first-order stage.

4 Figure 7. High-Q biquad stage. Figure 8. Low-Q biquad stage.

5 III. FILTER ARCHITECTURE The single-ended version of each of the three filter blocks is presented in [1] and [2], along with derivations for all of the capacitor values. It is fairly trivial to make the filters differential, simple mirroring the switched capacitors across to the non-inverting input. Figures 5-8 show the blocks used for the elliptic filter. Design techniques for cascading filter stages are described in [2]. Amongst the advice, the last stage should not be high-q (in fact, the high-q pole should be kept in the middle of the cascade). The first stage should be a low-pass system to remove high-frequency noise. Since the first-order filter demonstrates stricter low-pass behavior than the low-q biquad, it will be first in the cascade, followed by the high-q and finally the low-q stages (see Figure 5). The capacitor values calculated from [2] are included in the Calculated Value column of Table 3. Since the system of equations to be satisfied is indeterminate, the feedback capacitors are each arbitrarily set to 10pF. LINEAR Calculated Value (pf) scaling factor Dynamic Range Scaling (pf) Area Scaling (pf) CA C C C HIGH-Q C C C C C C C C LOW-Q C C C C C C C C Table III. Capacitor values for simulation.

6 Figure 9. Sample-and-hold output stage. There is also a sample-and-hold block at the end of the cascade which improves stopband performance, shown in Figure 9. The simulated transfer function, using the switched-capacitor implementation of the filter, is plotted in Figures Some headroom from the ideal case is lost, but all frequency response specifications are met. Figure 10. Simulated elliptic filer, before scaling. Figure 11. Simulated passband ripple, before scaling. Figure 12. Simulated stopband gain, before scaling.

7 IV. OPTIMIZATION The filter is a cascade of opamps, each with a different output swing shown in Figure 13. Since each of the opamps has the same input-referred noise, the signal-to-noise ratio (SNR) will improve with output swing. However, increasing the gain beyond unity means that a different stage must attenuate the input signal, and will not have optimum noise performance. Thus SNR is optimized by scaling all opamp output swings to unity. Consider the simple example in Figure 15, with a single input branch, a feedback path, and a single output branch. To scale the output swing by k, either the input capacitor scales by k or the feedback capacitor divides by k. To maintain the same output current as before (not disturbing the next opamp input), the output branch divides by k as well. Following this procedure through the 5 stages, the capacitor values are optimized for dynamic range. Once this is completed, all the capacitors in the design are scaled evenly to bring the smallest value down to 0.05pF, minimizing chip area. The order of these two optimizations is important; First you loot, then you burn. Table 3 includes both sets of scaled values. Simulation results are in Figures 16-21, illustrating that the scaled values indeed still meet all the specifications. Figure 13. Opamp voltage swings before DR scaling. Figure 14. Mismatch in passband before DR scaling. Figure 15. Input/output/feedback branches for dynamic range scaling.

8 Figure 16. Opamp voltage swings after DR scaling. Figure 17. Unity gain in passband after DR scaling. Figure 18. Filter res ponse after DR scaling. Figure 19. Filter response after area scaling. Figure 20. Passband response after area scaling. Figure 21.Stopband response after area scaling. V. SIMULATION WITH OPAMP MACROMODEL Figure 22 shows the finite gain, finite bandwidth macromodel used in simulation for an opamp. Bandwidth is simply determined by the RC parallel combination on either side of the

9 schematic. Gain is determined by the product of the resistance (2MΩ) and the transconductance of the amplifier, GMM. Figure 22. Operational amplifier macromodel. VI. NON-IDEAL EFFECTS With the successfully designed switched capacitor filter, several non-idealities are simulated in order to understand their impact on performance. Charge injection, opamp offset voltage, slew rate, finite bandwidth and finite gain are all simulated within the elliptical filter. a. Finite opamp gain If the opamp has finite gain, then the simplistic assumptions about the virtual ground nodes at the inputs are false and there will be some nonzero input voltage. If the gain drops low enough (or in other words, residual input voltage raises high enough) it interferes with the charge-sharing function of the switched capacitors and the filter fails to function correctly. As shown in Figure 23, finite gain takes effect on the transfer function at about 20dB. As opamp gain approaches zero, the filter heavily attenuates all input signals.

10 Figure 23. Effect of finite opamp gain on filter frequency response. b. Finite opamp bandwidth Certainly, the opamp needs bandwidth at least the Nyquist rate (15MHz in this case) to resolve an input signal. If bandwidth drops below the Nyquist rate then the passband shrinks and the transfer function loses its shape, as shown in Figures The difference between the 100MHz and 1MHz simulations illustrates this point. Figure 24. Effect of finite opamp bandwidth on filter frequency response.

11 Figure 25. Passband response with finite BW. Figure 26. Stopband response with finite BW. c. Opamp offset voltage Input offset is simulated by placing a DC voltage source into on of the opamp input terminals. It is generally a model for mismatch or asymmetry between the two differential paths. Similar to the residual charge from finite gain, this degrades performance. Tens of millivolts will completely distort the filter s frequency response. d. Charge Injection When using real NMOS transmission gate switches, some small amount of charge is injected into the channel on each clock cycle. The charge is proportional to the area of the device and the overdrive voltage: Q WLC V inj This is simulated using a CMOS transmission gate as shown in Figure X: OX Figure 27. CMOS transmission gate for charge injection. e. Slew rate In the ideal case, the output of the filter would respond instantaneously to stimuli at the input. Naturally, there is some duration of time while the output is still changing. Slew rate measures this worst case rate of change of the output voltage- it is simulated by sending an ideal pulse into the filter during a transient analysis (see Figure 28). In the

12 output waveform, the output changes linearly trying to adapt to the ideal pulse. This is shown in Figure 29, and the calculated slew rate is V/mS. Figure 28. Transient simulation of slew rate. Figure 29. Detailed view of output slewing. VII. CONCLUSION A 5 th -order low pass switched capacitor filter was designed using Matlab and Spectre. The filter is designed using ideal opamps and switches, achieving 0.2dB passband ripple (0-1 MHz) and -60dB stopband attenuation (2-7.5 MHz) at 15 MHz sampling rate. The filter includes a first-order, high-q biquad, and low-q biquad stage, and is optimized for both dynamic range and area. The area is minimized to be equivalent to a single 3.54pF capacitor. Non-idealities in the opamp and transmission gates, including finite gain and bandwidth, charge injection, slew rate, and offset voltage, are discusses and simulated. REFERENCES [1] David A. Johns, and Ken Martin, Analog Integrated Circuit Design, John Wiley and Sons, [2] Dr. Gabor Temes, Oregon State University, ECE626 lecture notes, Winter APPENDIX A: MATLAB SCRIPT function designer(gp, gs) %Final project script for ECE626. Written by Allen Waters. %Input parameters: % gp: maximum passband ripple % gs: minimum stopband attenuation

13 % constants fs = 15e6; %sampling frequency fp = 1e6; %passband frequency fs = 2e6; %stopband frequency % frequency warping wp = 2*fs*tan(2*pi*fP/(2*fs)); ws = 2*fs*tan(2*pi*fS/(2*fs)); % find minimum order for different filter types n_butter = buttord(wp, ws, gp, gs, 's'); n_cheb1 = cheb1ord(wp, ws, gp, gs, 's'); n_cheb2 = cheb2ord(wp, ws, gp, gs, 's'); [n_ellip, Wp] = ellipord(wp, ws, gp, gs, 's'); fprintf('filter orders (butterworth, cheb1, cheb2, elliptic) are:\n') fprintf('\t\t\t%d\t%d\t%d\t%d\n\n', n_butter, n_cheb1, n_cheb2, n_ellip) % determine elliptic filter transfer function [Hnum, Hden] = ellip(n_ellip, gp, gs, Wp, 'low', 's'); [HnumZ, HdenZ] = bilinear(hnum, Hden, fs); fvtool(hnumz, HdenZ); % break into three different transfer functions [sos, gain] = tf2sos(hnumz, HdenZ) fprintf('total gain needed is %f\n', gain) g_stage = gain ^ (1/3); fprintf('gain per stage is %f\n', g_stage) % calculate Q values pole2 = roots([sos(2,4), sos(2,5), sos(2,6)]); pole2_s = log(pole2(1)); Q2 = abs(pole2_s) / (2 * abs(real(pole2_s))); fprintf('q2 is %f\n', Q2) pole3 = roots([sos(3,4), sos(3,5), sos(3,6)]); pole3_s = log(pole3(1)); Q3 = abs(pole3_s) / (2 * abs(real(pole3_s))); fprintf('q3 is %f\n', Q3) % calculate coefficients for capacitor values % linear fprintf('\nlinear STAGE\n\n') Ca = 10; pole1 = roots([sos(1,4), sos(1,5)]); C3 = Ca * (1- pole1) / pole1; dc_gain = g_stage * (sos(1,1) * 1 + sos(1,2)) / (sos(1,4) * 1 + sos(1,5)); C2 = -1 * C3 * dc_gain; C1 = -0.5 * C2; fprintf('ca = %f pf\n', Ca) fprintf('c1 = %f pf\n', C1) fprintf('c2 = %f pf\n', C2) fprintf('c3 = %f pf\n', C3) % low-q fprintf('\nlow-q BIQUAD\n\n') a2 = g_stage * sos(2,1) / sos(2,6);

14 a1 = g_stage * sos(2,2) / sos(2,6); a0 = g_stage * sos(2,3) / sos(2,6); b2 = sos(2,4) / sos(2,6); b1 = sos(2,5) / sos(2,6); K6 = b2-1; K5 = (b1 + b2 + 1) ^ 0.5; K4 = K5; K3 = a0; K2 = a2 - a0; K1 = (a0 + a1 + a2) / K5; C1 = 10; C4 = 10; fprintf('c1 = %f pf\n', C1) fprintf('c2 = %f pf\n', K1 * C1) fprintf('c3 = %f pf\n', K4 * C1) fprintf('c4 = %f pf\n', C4) fprintf('c5 = %f pf\n', K2 * C4) fprintf('c6 = %f pf\n', K3 * C4) fprintf('c7 = %f pf\n', K5 * C4) fprintf('c8 = %f pf\n', K6 * C4) % high-q fprintf('\nhigh-q BIQUAD\n\n') a2 = g_stage * sos(3,1) / sos(3,4); a1 = g_stage * sos(3,2) / sos(3,4); a0 = g_stage * sos(3,3) / sos(3,4); b1 = sos(3,5) / sos(3,4); b0 = sos(3,6) / sos(3,4); K5 = (b0 + b1 + 1) ^ 0.5; K4 = K5; K6 = (1 - b0) / K5; K3 = a2; K2 = (a2 - a0) / K5; K1 = (a0 + a1 + a2) / K5; C1 = 10; C6 = 10; fprintf('c1 = %f pf\n', C1) fprintf('c2 = %f pf\n', K1 * C1) fprintf('c3 = %f pf\n', K2 * C1) fprintf('c4 = %f pf\n', K4 * C1) fprintf('c5 = %f pf\n', K6 * C1) fprintf('c6 = %f pf\n', C6) fprintf('c7 = %f pf\n', K3 * C6) fprintf('c8 = %f pf\n', K5 * C6)

Design of a 100 MHz, 5 th Order Elliptic, Low-Pass Switched Capacitor Filter

Design of a 100 MHz, 5 th Order Elliptic, Low-Pass Switched Capacitor Filter Design of a 100 MHz, 5 th Order Elliptic, Low-Pass Switched Capacitor Filter 1 Jon Guerber, ECE 626, Student Member, IEEE Abstract The design and simulation of an Elliptic switched capacitor filter with

More information

ECE626 Project Switched Capacitor Filter Design

ECE626 Project Switched Capacitor Filter Design ECE626 Project Switched Capacitor Filter Design Hari Prasath Venkatram Contents I Introduction 2 II Choice of Topology 2 III Poles and Zeros 2 III-ABilinear Transform......................................

More information

System on a Chip. Prof. Dr. Michael Kraft

System on a Chip. Prof. Dr. Michael Kraft System on a Chip Prof. Dr. Michael Kraft Lecture 4: Filters Filters General Theory Continuous Time Filters Background Filters are used to separate signals in the frequency domain, e.g. remove noise, tune

More information

A Unity Gain Fully-Differential 10bit and 40MSps Sample-And-Hold Amplifier in 0.18μm CMOS

A Unity Gain Fully-Differential 10bit and 40MSps Sample-And-Hold Amplifier in 0.18μm CMOS A Unity Gain Fully-Differential 0bit and 40MSps Sample-And-Hold Amplifier in 0.8μm CMOS Sanaz Haddadian, and Rahele Hedayati Abstract A 0bit, 40 MSps, sample and hold, implemented in 0.8-μm CMOS technology

More information

BandPass Sigma-Delta Modulator for wideband IF signals

BandPass Sigma-Delta Modulator for wideband IF signals BandPass Sigma-Delta Modulator for wideband IF signals Luca Daniel (University of California, Berkeley) Marco Sabatini (STMicroelectronics Berkeley Labs) maintain the same advantages of BaseBand converters

More information

Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem

Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem A report Submitted to Canopus Systems Inc. Zuhail Sainudeen and Navid Yazdi Arizona State University July 2001 1. Overview

More information

ECE 203 LAB 2 PRACTICAL FILTER DESIGN & IMPLEMENTATION

ECE 203 LAB 2 PRACTICAL FILTER DESIGN & IMPLEMENTATION Version 1. 1 of 7 ECE 03 LAB PRACTICAL FILTER DESIGN & IMPLEMENTATION BEFORE YOU BEGIN PREREQUISITE LABS ECE 01 Labs ECE 0 Advanced MATLAB ECE 03 MATLAB Signals & Systems EXPECTED KNOWLEDGE Understanding

More information

INF4420 Switched capacitor circuits Outline

INF4420 Switched capacitor circuits Outline INF4420 Switched capacitor circuits Spring 2012 1 / 54 Outline Switched capacitor introduction MOSFET as an analog switch z-transform Switched capacitor integrators 2 / 54 Introduction Discrete time analog

More information

CMOS Operational-Amplifier

CMOS Operational-Amplifier CMOS Operational-Amplifier 1 What will we learn in this course How to design a good OP Amp. Basic building blocks Biasing and Loading Swings and Bandwidth CH2(8) Operational Amplifier as A Black Box Copyright

More information

ECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier

ECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier ECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier Objective Design, simulate and test a two-stage operational amplifier Introduction Operational amplifiers (opamp) are essential components of

More information

Design of Rail-to-Rail Op-Amp in 90nm Technology

Design of Rail-to-Rail Op-Amp in 90nm Technology IJSTE - International Journal of Science Technology & Engineering Volume 1 Issue 2 August 2014 ISSN(online) : 2349-784X Design of Rail-to-Rail Op-Amp in 90nm Technology P R Pournima M.Tech Electronics

More information

INF4420. Switched capacitor circuits. Spring Jørgen Andreas Michaelsen

INF4420. Switched capacitor circuits. Spring Jørgen Andreas Michaelsen INF4420 Switched capacitor circuits Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Outline Switched capacitor introduction MOSFET as an analog switch z-transform Switched capacitor integrators

More information

Modulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies

Modulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies A. Pena Perez, V.R. Gonzalez- Diaz, and F. Maloberti, ΣΔ Modulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies, IEEE Proceeding of Latin American Symposium on Circuits and Systems, Feb.

More information

Outline. Noise and Distortion. Noise basics Component and system noise Distortion INF4420. Jørgen Andreas Michaelsen Spring / 45 2 / 45

Outline. Noise and Distortion. Noise basics Component and system noise Distortion INF4420. Jørgen Andreas Michaelsen Spring / 45 2 / 45 INF440 Noise and Distortion Jørgen Andreas Michaelsen Spring 013 1 / 45 Outline Noise basics Component and system noise Distortion Spring 013 Noise and distortion / 45 Introduction We have already considered

More information

Lecture 3 Switched-Capacitor Circuits Trevor Caldwell

Lecture 3 Switched-Capacitor Circuits Trevor Caldwell Advanced Analog Circuits Lecture 3 Switched-Capacitor Circuits Trevor Caldwell trevor.caldwell@analog.com Lecture Plan Date Lecture (Wednesday 2-4pm) Reference Homework 2017-01-11 1 MOD1 & MOD2 ST 2, 3,

More information

Advanced Operational Amplifiers

Advanced Operational Amplifiers IsLab Analog Integrated Circuit Design OPA2-47 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA2-1 Advanced Current Mirrors and Opamps Two-stage

More information

Design of Low Voltage Low Power CMOS OP-AMP

Design of Low Voltage Low Power CMOS OP-AMP RESEARCH ARTICLE OPEN ACCESS Design of Low Voltage Low Power CMOS OP-AMP Shahid Khan, Prof. Sampath kumar V. Electronics & Communication department, JSSATE ABSTRACT Operational amplifiers are an integral

More information

Keywords: op amp filters, Sallen-Key filters, high pass filter, opamps, single op amp

Keywords: op amp filters, Sallen-Key filters, high pass filter, opamps, single op amp Maxim > Design Support > Technical Documents > Tutorials > Amplifier and Comparator Circuits > APP 738 Maxim > Design Support > Technical Documents > Tutorials > Audio Circuits > APP 738 Maxim > Design

More information

ETIN25 Analogue IC Design. Laboratory Manual Lab 2

ETIN25 Analogue IC Design. Laboratory Manual Lab 2 Department of Electrical and Information Technology LTH ETIN25 Analogue IC Design Laboratory Manual Lab 2 Jonas Lindstrand Martin Liliebladh Markus Törmänen September 2011 Laboratory 2: Design and Simulation

More information

CMOS Operational-Amplifier

CMOS Operational-Amplifier CMOS Operational-Amplifier 1 What will we learn in this course How to design a good OP Amp. Basic building blocks Biasing and Loading Swings and Bandwidth CH2(8) Operational Amplifier as A Black Box Copyright

More information

ECEN 474/704 Lab 6: Differential Pairs

ECEN 474/704 Lab 6: Differential Pairs ECEN 474/704 Lab 6: Differential Pairs Objective Design, simulate and layout various differential pairs used in different types of differential amplifiers such as operational transconductance amplifiers

More information

Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wireless Applications

Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wireless Applications RESEARCH ARTICLE OPEN ACCESS Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wireless Applications Sharon Theresa George*, J. Mangaiyarkarasi** *(Department of Information and Communication

More information

Gábor C. Temes. School of Electrical Engineering and Computer Science Oregon State University. 1/57

Gábor C. Temes. School of Electrical Engineering and Computer Science Oregon State University. 1/57 Gábor C. Temes School of Electrical Engineering and Computer Science Oregon State University temes@ece.orst.edu 1/57 Switched-Capacitor Circuit Techniques ORIGIN : "SC" replacing "R"; 1873, James Clerk

More information

ECE 627 Project: Design of a High-Speed Delta-Sigma A/D Converter

ECE 627 Project: Design of a High-Speed Delta-Sigma A/D Converter ECE 627 Project: Design of a High-Speed Delta-Sigma A/D Converter Brian L. Young youngbr@eecs.oregonstate.edu Oregon State University June 6, 28 I. INTRODUCTION The goal of the Spring 28, ECE 627 project

More information

A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER

A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER M. Taherzadeh-Sani, R. Lotfi, and O. Shoaei ABSTRACT A novel class-ab architecture for single-stage operational amplifiers is presented. The structure

More information

Chapter 13: Introduction to Switched- Capacitor Circuits

Chapter 13: Introduction to Switched- Capacitor Circuits Chapter 13: Introduction to Switched- Capacitor Circuits 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4 Switched-Capacitor Integrator 13.5 Switched-Capacitor

More information

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY DIGITAL SIGNAL PROCESSING UNIT 3

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY DIGITAL SIGNAL PROCESSING UNIT 3 NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY DIGITAL SIGNAL PROCESSING UNIT 3 IIR FILTER DESIGN Structure of IIR System design of Discrete time

More information

LM148/LM248/LM348 Quad 741 Op Amps

LM148/LM248/LM348 Quad 741 Op Amps Quad 741 Op Amps General Description The LM148 series is a true quad 741. It consists of four independent, high gain, internally compensated, low power operational amplifiers which have been designed to

More information

DAT175: Topics in Electronic System Design

DAT175: Topics in Electronic System Design DAT175: Topics in Electronic System Design Analog Readout Circuitry for Hearing Aid in STM90nm 21 February 2010 Remzi Yagiz Mungan v1.10 1. Introduction In this project, the aim is to design an adjustable

More information

Tuesday, March 22nd, 9:15 11:00

Tuesday, March 22nd, 9:15 11:00 Nonlinearity it and mismatch Tuesday, March 22nd, 9:15 11:00 Snorre Aunet (sa@ifi.uio.no) Nanoelectronics group Department of Informatics University of Oslo Last time and today, Tuesday 22nd of March:

More information

An Ultra Low-Voltage and Low-Power OTA Using Bulk-Input Technique and Its Application in Active-RC Filters

An Ultra Low-Voltage and Low-Power OTA Using Bulk-Input Technique and Its Application in Active-RC Filters Circuits and Systems, 2011, 2, 183-189 doi:10.4236/cs.2011.23026 Published Online July 2011 (http://www.scirp.org/journal/cs) An Ultra Low-Voltage and Low-Power OTA Using Bulk-Input Technique and Its Application

More information

NOWADAYS, multistage amplifiers are growing in demand

NOWADAYS, multistage amplifiers are growing in demand 1690 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 51, NO. 9, SEPTEMBER 2004 Advances in Active-Feedback Frequency Compensation With Power Optimization and Transient Improvement Hoi

More information

THE TREND toward implementing systems with low

THE TREND toward implementing systems with low 724 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 7, JULY 1995 Design of a 100-MHz 10-mW 3-V Sample-and-Hold Amplifier in Digital Bipolar Technology Behzad Razavi, Member, IEEE Abstract This paper

More information

Lecture #6: Analog-to-Digital Converter

Lecture #6: Analog-to-Digital Converter Lecture #6: Analog-to-Digital Converter All electrical signals in the real world are analog, and their waveforms are continuous in time. Since most signal processing is done digitally in discrete time,

More information

What is the typical voltage gain of the basic two stage CMOS opamp we studied? (i) 20dB (ii) 40dB (iii) 80dB (iv) 100dB

What is the typical voltage gain of the basic two stage CMOS opamp we studied? (i) 20dB (ii) 40dB (iii) 80dB (iv) 100dB Department of Electronic ELEC 5808 (ELG 6388) Signal Processing Electronics Final Examination Dec 14th, 2010 5:30PM - 7:30PM R. Mason answer all questions one 8.5 x 11 crib sheets allowed 1. (5 points)

More information

Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching

Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching RESEARCH ARTICLE OPEN ACCESS Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching Annu Saini, Prity Yadav (M.Tech. Student, Department

More information

Analog Integrated Circuits Fundamental Building Blocks

Analog Integrated Circuits Fundamental Building Blocks Analog Integrated Circuits Fundamental Building Blocks Basic OTA/Opamp architectures Faculty of Electronics Telecommunications and Information Technology Gabor Csipkes Bases of Electronics Department Outline

More information

[Kumar, 2(9): September, 2013] ISSN: Impact Factor: 1.852

[Kumar, 2(9): September, 2013] ISSN: Impact Factor: 1.852 IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY Design and Performance analysis of Low power CMOS Op-Amp Anand Kumar Singh *1, Anuradha 2, Dr. Vijay Nath 3 *1,2 Department of

More information

LIMITATIONS IN MAKING AUDIO BANDWIDTH MEASUREMENTS IN THE PRESENCE OF SIGNIFICANT OUT-OF-BAND NOISE

LIMITATIONS IN MAKING AUDIO BANDWIDTH MEASUREMENTS IN THE PRESENCE OF SIGNIFICANT OUT-OF-BAND NOISE LIMITATIONS IN MAKING AUDIO BANDWIDTH MEASUREMENTS IN THE PRESENCE OF SIGNIFICANT OUT-OF-BAND NOISE Bruce E. Hofer AUDIO PRECISION, INC. August 2005 Introduction There once was a time (before the 1980s)

More information

Data Conversion Techniques (DAT115)

Data Conversion Techniques (DAT115) Data Conversion Techniques (DAT115) Hand in Report Second Order Sigma Delta Modulator with Interleaving Scheme Group 14N Remzi Yagiz Mungan, Christoffer Holmström [ 1 20 ] Contents 1. Task Description...

More information

Design of Reconfigurable Baseband Filter. Xin Jin

Design of Reconfigurable Baseband Filter. Xin Jin Design of Reconfigurable Baseband Filter by Xin Jin A thesis submitted to the Graduate Faculty of Auburn University in partial fulfillment of the requirements for the Degree of Master of Science Auburn,

More information

Design and Simulation of Low Voltage Operational Amplifier

Design and Simulation of Low Voltage Operational Amplifier Design and Simulation of Low Voltage Operational Amplifier Zach Nelson Department of Electrical Engineering, University of Nevada, Las Vegas 4505 S Maryland Pkwy, Las Vegas, NV 89154 United States of America

More information

ECEN 325 Lab 5: Operational Amplifiers Part III

ECEN 325 Lab 5: Operational Amplifiers Part III ECEN Lab : Operational Amplifiers Part III Objectives The purpose of the lab is to study some of the opamp configurations commonly found in practical applications and also investigate the non-idealities

More information

Nonlinear Macromodeling of Amplifiers and Applications to Filter Design.

Nonlinear Macromodeling of Amplifiers and Applications to Filter Design. ECEN 622 Nonlinear Macromodeling of Amplifiers and Applications to Filter Design. By Edgar Sanchez-Sinencio Thanks to Heng Zhang for part of the material OP AMP MACROMODELS Systems containing a significant

More information

Operational Amplifiers

Operational Amplifiers Monolithic Amplifier Circuits: Operational Amplifiers Chapter Jón Tómas Guðmundsson tumi@hi.is. Week Fall 200 Operational amplifiers (op amps) are an integral part of many analog and mixedsignal systems

More information

Operational Amplifiers

Operational Amplifiers Monolithic Amplifier Circuits: Operational Amplifiers Chapter 1 Jón Tómas Guðmundsson tumi@hi.is 1. Week Fall 2010 1 Introduction Operational amplifiers (op amps) are an integral part of many analog and

More information

FYS3240 PC-based instrumentation and microcontrollers. Signal sampling. Spring 2015 Lecture #5

FYS3240 PC-based instrumentation and microcontrollers. Signal sampling. Spring 2015 Lecture #5 FYS3240 PC-based instrumentation and microcontrollers Signal sampling Spring 2015 Lecture #5 Bekkeng, 29.1.2015 Content Aliasing Nyquist (Sampling) ADC Filtering Oversampling Triggering Analog Signal Information

More information

Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier

Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in double-ended

More information

IN the design of the fine comparator for a CMOS two-step flash A/D converter, the main design issues are offset cancelation

IN the design of the fine comparator for a CMOS two-step flash A/D converter, the main design issues are offset cancelation JOURNAL OF STELLAR EE315 CIRCUITS 1 A 60-MHz 150-µV Fully-Differential Comparator Erik P. Anderson and Jonathan S. Daniels (Invited Paper) Abstract The overall performance of two-step flash A/D converters

More information

CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC

CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC 138 CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC 6.1 INTRODUCTION The Clock generator is a circuit that produces the timing or the clock signal for the operation in sequential circuits. The circuit

More information

Analog Design-filters

Analog Design-filters Analog Design-filters Introduction and Motivation Filters are networks that process signals in a frequency-dependent manner. The basic concept of a filter can be explained by examining the frequency dependent

More information

BUCK Converter Control Cookbook

BUCK Converter Control Cookbook BUCK Converter Control Cookbook Zach Zhang, Alpha & Omega Semiconductor, Inc. A Buck converter consists of the power stage and feedback control circuit. The power stage includes power switch and output

More information

Chapter 12 Opertational Amplifier Circuits

Chapter 12 Opertational Amplifier Circuits 1 Chapter 12 Opertational Amplifier Circuits Learning Objectives 1) The design and analysis of the two basic CMOS op-amp architectures: the two-stage circuit and the single-stage, folded cascode circuit.

More information

CHAPTER 3. Instrumentation Amplifier (IA) Background. 3.1 Introduction. 3.2 Instrumentation Amplifier Architecture and Configurations

CHAPTER 3. Instrumentation Amplifier (IA) Background. 3.1 Introduction. 3.2 Instrumentation Amplifier Architecture and Configurations CHAPTER 3 Instrumentation Amplifier (IA) Background 3.1 Introduction The IAs are key circuits in many sensor readout systems where, there is a need to amplify small differential signals in the presence

More information

Comparative Analysis of Compensation Techniques for improving PSRR of an OPAMP

Comparative Analysis of Compensation Techniques for improving PSRR of an OPAMP Comparative Analysis of Compensation Techniques for improving PSRR of an OPAMP 1 Pathak Jay, 2 Sanjay Kumar M.Tech VLSI and Embedded System Design, Department of School of Electronics, KIIT University,

More information

ECE 442 Solid State Devices & Circuits. 15. Differential Amplifiers

ECE 442 Solid State Devices & Circuits. 15. Differential Amplifiers ECE 442 Solid State Devices & Circuits 15. Differential Amplifiers Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 442 Jose Schutt Aine 1 Background

More information

EE247 Lecture 24. EE247 Lecture 24

EE247 Lecture 24. EE247 Lecture 24 EE247 Lecture 24 Administrative EE247 Final exam: Date: Wed. Dec. 15 th Time: -12:30pm-3:30pm- Location: 289 Cory Closed book/course notes No calculators/cell phones/pdas/computers Bring one 8x11 paper

More information

Op-Amp Design Project EE 5333 Analog Integrated Circuits Prof. Ramesh Harjani Department of ECE University of Minnesota, Twin Cities Report prepared

Op-Amp Design Project EE 5333 Analog Integrated Circuits Prof. Ramesh Harjani Department of ECE University of Minnesota, Twin Cities Report prepared Op-Amp Design Project EE 5333 Analog Integrated Circuits Prof. Ramesh Harjani Department of ECE University of Minnesota, Twin Cities Report prepared by: Nirav Desai (4280229) 1 Contents: 1. Design Specifications

More information

LM13600 Dual Operational Transconductance Amplifiers with Linearizing Diodes and Buffers

LM13600 Dual Operational Transconductance Amplifiers with Linearizing Diodes and Buffers LM13600 Dual Operational Transconductance Amplifiers with Linearizing Diodes and Buffers General Description The LM13600 series consists of two current controlled transconductance amplifiers each with

More information

Nonlinear Macromodeling of Amplifiers and Applications to Filter Design.

Nonlinear Macromodeling of Amplifiers and Applications to Filter Design. ECEN 622(ESS) Nonlinear Macromodeling of Amplifiers and Applications to Filter Design. By Edgar Sanchez-Sinencio Thanks to Heng Zhang for part of the material OP AMP MACROMODELS Systems containing a significant

More information

DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS

DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS by Yves Geerts Alcatel Microelectronics, Belgium Michiel Steyaert KU Leuven, Belgium and Willy Sansen KU Leuven,

More information

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN OPAMP DESIGN AND SIMULATION Vishal Saxena OPAMP DESIGN PROJECT R 2 v out v in /2 R 1 C L v in v out V CM R L V CM C L V CM -v in /2 R 1 C L (a) (b) R 2 ECE415/EO

More information

Evaluation Board Analog Output Functions and Characteristics

Evaluation Board Analog Output Functions and Characteristics Evaluation Board Analog Output Functions and Characteristics Application Note July 2002 AN1023 Introduction The ISL5239 Evaluation Board includes the circuit provisions to convert the baseband digital

More information

CHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS

CHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS CHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS Chapter Outline 8.1 The CMOS Differential Pair 8. Small-Signal Operations of the MOS Differential Pair 8.3 The BJT Differential Pair 8.4 Other Non-ideal

More information

Design Analysis and Performance Comparison of Low Power High Gain 2nd Stage Differential Amplifier Along with 1st Stage

Design Analysis and Performance Comparison of Low Power High Gain 2nd Stage Differential Amplifier Along with 1st Stage Design Analysis and Performance Comparison of Low Power High Gain 2nd Stage Differential Amplifier Along with 1st Stage Sadeque Reza Khan Department of Electronic and Communication Engineering, National

More information

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic

More information

A 10 bit, 1.8 GS/s Time Interleaved Pipeline ADC

A 10 bit, 1.8 GS/s Time Interleaved Pipeline ADC A 10 bit, 1.8 GS/s Time Interleaved Pipeline ADC M. Åberg 2, A. Rantala 2, V. Hakkarainen 1, M. Aho 1, J. Riikonen 1, D. Gomes Martin 2, K. Halonen 1 1 Electronic Circuit Design Laboratory Helsinki University

More information

Lecture 2: Non-Ideal Amps and Op-Amps

Lecture 2: Non-Ideal Amps and Op-Amps Lecture 2: Non-Ideal Amps and Op-Amps Prof. Ali M. Niknejad Department of EECS University of California, Berkeley Practical Op-Amps Linear Imperfections: Finite open-loop gain (A 0 < ) Finite input resistance

More information

Design of a Folded Cascode Operational Amplifier in a 1.2 Micron Silicon-Carbide CMOS Process

Design of a Folded Cascode Operational Amplifier in a 1.2 Micron Silicon-Carbide CMOS Process University of Arkansas, Fayetteville ScholarWorks@UARK Electrical Engineering Undergraduate Honors Theses Electrical Engineering 5-2017 Design of a Folded Cascode Operational Amplifier in a 1.2 Micron

More information

DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT

DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT PRADEEP G CHAGASHETTI Mr. H.V. RAVISH ARADHYA Department of E&C Department of E&C R.V.COLLEGE of ENGINEERING R.V.COLLEGE of ENGINEERING Bangalore

More information

Design of Miller Compensated Two-Stage Operational Amplifier for Data Converter Applications

Design of Miller Compensated Two-Stage Operational Amplifier for Data Converter Applications Design of Miller Compensated Two-Stage Operational Amplifier for Data Converter Applications Prema Kumar. G Shravan Kudikala Casest, School Of Physics Casest, School Of Physics University Of Hyderabad

More information

EE 501 Lab 4 Design of two stage op amp with miller compensation

EE 501 Lab 4 Design of two stage op amp with miller compensation EE 501 Lab 4 Design of two stage op amp with miller compensation Objectives: 1. Design a two stage op amp 2. Investigate how to miller compensate a two-stage operational amplifier. Tasks: 1. Build a two-stage

More information

Introduction (cont )

Introduction (cont ) Active Filter 1 Introduction Filters are circuits that are capable of passing signals within a band of frequencies while rejecting or blocking signals of frequencies outside this band. This property of

More information

Analog Integrated Circuit Design Exercise 1

Analog Integrated Circuit Design Exercise 1 Analog Integrated Circuit Design Exercise 1 Integrated Electronic Systems Lab Prof. Dr.-Ing. Klaus Hofmann M.Sc. Katrin Hirmer, M.Sc. Sreekesh Lakshminarayanan Status: 21.10.2015 Pre-Assignments The lecture

More information

AN-1106 Custom Instrumentation Amplifier Design Author: Craig Cary Date: January 16, 2017

AN-1106 Custom Instrumentation Amplifier Design Author: Craig Cary Date: January 16, 2017 AN-1106 Custom Instrumentation Author: Craig Cary Date: January 16, 2017 Abstract This application note describes some of the fine points of designing an instrumentation amplifier with op-amps. We will

More information

Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation

Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation Rail-To-Rail Op-Amp Design with Negative Miller Capacitance Compensation Muhaned Zaidi, Ian Grout, Abu Khari bin A ain Abstract In this paper, a two-stage op-amp design is considered using both Miller

More information

A study of switched-capacitor filters

A study of switched-capacitor filters University of Arkansas, Fayetteville ScholarWorks@UARK Electrical Engineering Undergraduate Honors Theses Electrical Engineering 12-2008 A study of switched-capacitor filters Kacie Thomas University of

More information

University of Michigan EECS 311: Electronic Circuits Fall 2009 LAB 2 NON IDEAL OPAMPS

University of Michigan EECS 311: Electronic Circuits Fall 2009 LAB 2 NON IDEAL OPAMPS University of Michigan EECS 311: Electronic Circuits Fall 2009 LAB 2 NON IDEAL OPAMPS Issued 10/5/2008 Pre Lab Completed 10/12/2008 Lab Due in Lecture 10/21/2008 Introduction In this lab you will characterize

More information

Gábor C. Temes. School of Electrical Engineering and Computer Science Oregon State University. 1/25

Gábor C. Temes. School of Electrical Engineering and Computer Science Oregon State University. 1/25 Gábor C. Temes School of Electrical Engineering and Computer Science Oregon State University temes@ece.orst.edu 1/25 Noise Intrinsic (inherent) noise: generated by random physical effects in the devices.

More information

BANDPASS delta sigma ( ) modulators are used to digitize

BANDPASS delta sigma ( ) modulators are used to digitize 680 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 52, NO. 10, OCTOBER 2005 A Time-Delay Jitter-Insensitive Continuous-Time Bandpass 16 Modulator Architecture Anurag Pulincherry, Michael

More information

AUDIO SIEVING USING SIGNAL FILTERS

AUDIO SIEVING USING SIGNAL FILTERS AUDIO SIEVING USING SIGNAL FILTERS A project under V.6.2 Signals and System Engineering Yatharth Aggarwal Sagar Mayank Chauhan Rajan Table of Contents Introduction... 2 Filters... 4 Butterworth Filter...

More information

Low power high-gain class-ab OTA with dynamic output current scaling

Low power high-gain class-ab OTA with dynamic output current scaling LETTER IEICE Electronics Express, Vol.0, No.3, 6 Low power high-gain class-ab OTA with dynamic output current scaling Youngil Kim a) and Sangsun Lee b) Department Nanoscale Semiconductor Engineering, Hanyang

More information

Basic OpAmp Design and Compensation. Chapter 6

Basic OpAmp Design and Compensation. Chapter 6 Basic OpAmp Design and Compensation Chapter 6 6.1 OpAmp applications Typical applications of OpAmps in analog integrated circuits: (a) Amplification and filtering (b) Biasing and regulation (c) Switched-capacitor

More information

Class-AB Low-Voltage CMOS Unity-Gain Buffers

Class-AB Low-Voltage CMOS Unity-Gain Buffers Class-AB Low-Voltage CMOS Unity-Gain Buffers Mariano Jimenez, Antonio Torralba, Ramón G. Carvajal and J. Ramírez-Angulo Abstract Class-AB circuits, which are able to deal with currents several orders of

More information

Lecture Notes Unit-III

Lecture Notes Unit-III Lecture Notes Unit-III FAQs Q1: An operational amplifier has a differential gain of 103 and CMRR of 100, input voltages are 120µV and 80µV, determine output voltage. 2 MARKS

More information

A Novel Continuous-Time Common-Mode Feedback for Low-Voltage Switched-OPAMP

A Novel Continuous-Time Common-Mode Feedback for Low-Voltage Switched-OPAMP 10.4 A Novel Continuous-Time Common-Mode Feedback for Low-oltage Switched-OPAMP M. Ali-Bakhshian Electrical Engineering Dept. Sharif University of Tech. Azadi Ave., Tehran, IRAN alibakhshian@ee.sharif.edu

More information

Design of High-Speed Op-Amps for Signal Processing

Design of High-Speed Op-Amps for Signal Processing Design of High-Speed Op-Amps for Signal Processing R. Jacob (Jake) Baker, PhD, PE Professor and Chair Boise State University 1910 University Dr. Boise, ID 83725-2075 jbaker@ieee.org Abstract - As CMOS

More information

Design and implementation of two stage operational amplifier

Design and implementation of two stage operational amplifier Design and implementation of two stage operational amplifier Priyanka T 1, Dr. H S Aravind 2, Yatheesh Hg 3 1M.Tech student, Dept, of ECE JSSATE Bengaluru 2Professor and HOD, Dept, of ECE JSSATE Bengaluru

More information

FYS3240 PC-based instrumentation and microcontrollers. Signal sampling. Spring 2017 Lecture #5

FYS3240 PC-based instrumentation and microcontrollers. Signal sampling. Spring 2017 Lecture #5 FYS3240 PC-based instrumentation and microcontrollers Signal sampling Spring 2017 Lecture #5 Bekkeng, 30.01.2017 Content Aliasing Sampling Analog to Digital Conversion (ADC) Filtering Oversampling Triggering

More information

NEW CIRCUIT TECHNIQUES AND DESIGN METHODES FOR INTEGRATED CIRCUITS PROCESSING SIGNALS FROM CMOS SENSORS

NEW CIRCUIT TECHNIQUES AND DESIGN METHODES FOR INTEGRATED CIRCUITS PROCESSING SIGNALS FROM CMOS SENSORS 11 NEW CIRCUIT TECHNIQUES ND DESIGN METHODES FOR INTEGRTED CIRCUITS PROCESSING SIGNLS FROM CMOS SENSORS Paul ULPOIU *, Emil SOFRON ** * Texas Instruments, Dallas, US, Email: paul.vulpoiu@gmail.com ** University

More information

NOVEMBER 29, 2017 COURSE PROJECT: CMOS TRANSIMPEDANCE AMPLIFIER ECG 720 ADVANCED ANALOG IC DESIGN ERIC MONAHAN

NOVEMBER 29, 2017 COURSE PROJECT: CMOS TRANSIMPEDANCE AMPLIFIER ECG 720 ADVANCED ANALOG IC DESIGN ERIC MONAHAN NOVEMBER 29, 2017 COURSE PROJECT: CMOS TRANSIMPEDANCE AMPLIFIER ECG 720 ADVANCED ANALOG IC DESIGN ERIC MONAHAN 1.Introduction: CMOS Transimpedance Amplifier Avalanche photodiodes (APDs) are highly sensitive,

More information

Rail to Rail Input Amplifier with constant G M and High Unity Gain Frequency. Arun Ramamurthy, Amit M. Jain, Anuj Gupta

Rail to Rail Input Amplifier with constant G M and High Unity Gain Frequency. Arun Ramamurthy, Amit M. Jain, Anuj Gupta 1 Rail to Rail Input Amplifier with constant G M and High Frequency Arun Ramamurthy, Amit M. Jain, Anuj Gupta Abstract A rail to rail input, 2.5V CMOS input amplifier is designed that amplifies uniformly

More information

Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. LM148/LM248/LM348 Quad 741 Op Amps General Description The LM148 series

More information

E4215: Analog Filter Synthesis and Design: HW0

E4215: Analog Filter Synthesis and Design: HW0 E425: Analog Filter Synthesis and Design: HW0 due on 2 Jan. 2003 This assignment has ZEO credit and does not contribute to the final grade. Its purpose is to gauge your familiarity of prerequisite topics..

More information

Operational Amplifiers

Operational Amplifiers Basic Electronics Syllabus: Introduction to : Ideal OPAMP, Inverting and Non Inverting OPAMP circuits, OPAMP applications: voltage follower, addition, subtraction, integration, differentiation; Numerical

More information

Classic Filters. Figure 1 Butterworth Filter. Chebyshev

Classic Filters. Figure 1 Butterworth Filter. Chebyshev Classic Filters There are 4 classic analogue filter types: Butterworth, Chebyshev, Elliptic and Bessel. There is no ideal filter; each filter is good in some areas but poor in others. Butterworth: Flattest

More information

Ultra Low-voltage Multiple-loop Feedback Switched-capacitor Filters

Ultra Low-voltage Multiple-loop Feedback Switched-capacitor Filters Ultra Low-voltage Multiple-loop Feedback Switched-capacitor Filters By Udhayasimha Puttamreddy Submitted in partial fulfilment of the requirements For the degree of Master of Applied Science At Dalhousie

More information

CHAPTER 9 FEEDBACK. NTUEE Electronics L.H. Lu 9-1

CHAPTER 9 FEEDBACK. NTUEE Electronics L.H. Lu 9-1 CHAPTER 9 FEEDBACK Chapter Outline 9.1 The General Feedback Structure 9.2 Some Properties of Negative Feedback 9.3 The Four Basic Feedback Topologies 9.4 The Feedback Voltage Amplifier (Series-Shunt) 9.5

More information

EE301 Electronics I , Fall

EE301 Electronics I , Fall EE301 Electronics I 2018-2019, Fall 1. Introduction to Microelectronics (1 Week/3 Hrs.) Introduction, Historical Background, Basic Consepts 2. Rewiev of Semiconductors (1 Week/3 Hrs.) Semiconductor materials

More information

Discretization of Continuous Controllers

Discretization of Continuous Controllers Discretization of Continuous Controllers Thao Dang VERIMAG, CNRS (France) Discretization of Continuous Controllers One way to design a computer-controlled control system is to make a continuous-time design

More information