Advanced Device Fabrication Techniques. ChiiDong Chen

Transcription

1 Advanced Device Fabrication Techniques TIGP lecture, NTU ChiiDong Chen Institute of Physics, Academia Sinica url:

2 Outline: 1 State-of-the-art device fabrication techniques Future light sources: EUV and e-beam 2 e-beam lithography 3 Examples: nano-pore based point contact devices nano electronic devices

3 Lithography = Pattern transferring

4 Standard etching process CVD, Thermal, e-gun, Sputtering, spin-coating remove exposed part (for positive-tone PR) selective dry/wet etching spin-coating UV light remove resist mask contact, projection finished pattern mask plate

5 Complementary process: lift-off remove exposed part (for positive-tone PR) spin-coating Thermal, e-gun, Sputtering UV light resist mask remove excess film contact, projection finished pattern mask plate

6 Substrate treatment process selective dry/wet etching or doping spin-coating UV light remove resist mask mask plate Contact or Projection exposure finished pattern

7 Experimental transistors for future process generations 65nm process 2005 production 45nm process 2007 production CMOS 0.8 nm conventional gate oxide 32nm process 2009 production 22nm process 2011 production Intel C. Michael Garner

8 Moore s Law: a 30% decrease in the size of printed dimensions every two years

9 Large circuit functions on a single semiconductor substrate = Reduced cost! >220M Transistors Integrated into Devices Produced Today source: Intel

10 SOURCES OF RADIATION FOR MICROLITHOGRAPHY Arc lamps (Hg-Xe) KrF (Krypton Fluoride) ArF (Argon Fluoride) Minimum feature size is scaling faster than lithography wavelength Advanced photo mask techniques help to bridge the gap Mark Bohr, Intel

11 The Ultimates of Optical Lithography Resolution: R=k 1 (λ/na) NA = sinθ = numerical aperture K 1 = a constant for a specific lithography process smaller K1 can be achieved by improving the process or resist contrast Depth of Focus DoF=k 2 (λ/na 2 ) Calculated R and DoF values UV wavelength 248 nm 193 nm 157 nm 13.4 nm Typical NA Production value of k Resolution 0.17 µm 0.13 µm 0.11 µm µm DoF (assuming k 2 = 1) 0.44 µm 0.34 µm 0.28 µm 0.21 µm P.F. Carcia et al. DuPoint Photomasks, Vacuum and Thin Film (1999)

12 Optical Proximity Correction used in 90 nm (193nm) production line Drawn structure Add OPC features Mask structure Printed on wafer Mark Bohr, Intel

13 Two types of phase shift mask Alternating aperture phase shift mask Embedded attenuating phase shift mask Cr Shifter 0 Amplitude at mask 0 Absorbing phase-shifter 6~18% transmittance 0 Amplitude at wafer 0 1. dark line appears at the center 2. Applicable only in limited structures 0 Intensity at wafer 0 1. Can even improve DoF 2. Use MoSi x O y N z, SiN x or CrO x F y instead of Cr Ref: P.F. Carcia et al. DuPoint Photomasks, Vacuum and Thin Film

14 Material Engineering gains importance!

15 90 nm Generation Transistor This is nano technology! source: Intel develop forum Spring, 2003

16 Nano materials will play an important role in the silicon nanotechnology platform Interconnectors with high electrical conductivity Low K interlevel Dielectric High K gate oxide Strained Si J. Brinker, UNM/Sandia National Labs Photoresist 0.2 µm C. Michael Garner, Intel, Sept.16, 2003

17 Introduction of high-k gate dielectric 90 nm process Experimental high-k Capacitance 1X 1.6X Leakage 1X <0.01X Carolyn Block, Intel

18 A message from Intel Compress P-doped regions by filling SiGe into carved trenches, hole conduction increased by 25% Stretch N-doped regions by annealing SixNy cover layer, electron conduction increased by10% Traditional MOS new PMOS new NMOS Graded SiGe layer Selective SiGe S-D Tensile Si 3 N 4 Cap Strained silicon benefits Strained silicon lattice increases electron and hole mobility Greater mobility results in 10-20% increase in transistor drive current (higher performance) Both NMOS and PMOS transistors improved Intel develop forum

19 Introduction of new materials 1st Production Process Generation nm m m m 65 nm 45 nm 32 nm 22 nm Wafer Size (mm) / Inter-connect Al Al Al Cu Cu Cu Cu? Channel Si Si Si Strained Si Strained Si Strained Si Strained Si Strained Si Gate dielectric SiO 2 SiO 2 SiO 2 SiO 2 SiO 2 High-k High-k High-k Gate electrode PolySi PolySi PolySi PolySi PolySi Metal Metal Metal source: Intel develop forum

20 Three types of new Fully Depleted Transistors SOI wafer gate Handling Si wafer Si BOX Planar fully depleted SOI Non-planar Double-gate (FinFET) Non-planar Tri-gate

21 Fully Depleted Transistors made on SOI wafers Non-planar Double-gate (FinFET) Non-planar Tri-gate Raised S-D using Selective Epi-Si Deposition Robert Chau, Intel

22 From Tri-gate transistors to Nano-wire transistors depletion electric field Tri-gate transistor Nano-wire transistor

23 Future light sources: Extreme UV Electron beam

24 EUV exposure tool Uses very short 13.4 nm light 13.4 nm radiation absorbed by all materials Requires reflective optics coated with quarter-wave Bragg reflectors Uses reflective reticles with patterned absorbers Vacuum operation Intel Corporation & EUV LLC Charles (Chuck) W. Gwyn

25 EUV reflective mask 13 nm EUV light reticles Cr absorber Si0 2 buffer Si capping 40 Mo/Si pairs Mo (~2.8nm) Si (~4.1nm) Intel EUV mask low thermal expansion glass substrate

26 EUV mask and patterned resist 90 nm Elbows in 350 nm polysi Source: Intel

27 Electron-Beam Lithography Electron Beam (e-beam) Gun: Electrons generated by: Thermionic emission from a hot filament. Field aided emission by applying a large electric field to a filament. Or a combination of the two. Filament is negatively biased (cathode) and electrons are accelerated to the substrate at typically kev. 2 2 ev = h k 2m e λ 0.25 ~ 0.12nm E-beam is focused to a small spot size using: Electrostatic lenses Magnetic fields Apertures A scanned e-beam spot writes the image in the resist one pixel at a time. X,Y direction of beam is controlled by electrostatic plates.

28 ELECTRON BEAM LITHOGRAPHY SYSTEM EOC ONTROL SYSTEM EOC EOC CONTROL EXPOSURE CONTROL SYSTEM STAGE CONTROL SYSTEM CONTROL LASER IF INTERFEROMETER CPU STAGE X-Y-Z STAGE CONTROL VACUUM VACUUM PUMP CONTROL VACUUM CONTROL SYSTEM

29 JEOL JBX-9300FS ELIONIX ELS-7000

30 ELECTRON OPTICS SYSTEM TFE electron gun Acceleration tube ION PUMP ION PUMP Alignment coil Blanking electrode Blanking aperture Electromagnetic lens ION PUMP Alignment coil Objective aperture Objective lens

31 Electron Optics Acceleration tube Blanking electro Blanking aperture Electromagnetic lens Objective aperture Objective lens Z Y X X-Y-Z Stage

32 ZrO/W THERMAL FIELD EMISSION GUN Polycrystalline tungsten Heating filament ZrO Reservoir Filament Emitter 100 W Crystal Outgassing Ports Suppressor Cap Base

33 Beam blanking 1 st Electrostatic Blankng Blanking aperture 2 nd Electrostatic Blanking

34 Electronmagnetic Alignment 1 st Alignment coil 2 nd Alignment coil Electronmagnetic lens

35 Electrostatic Deflector 1 st Electrostatic Deflecto 2 nd Electrostatic Deflector Objective lens

36 Beam spot size vs. beam current for different apertures ELS 7000 Vacc=100kV

37 Modification of an SEM based e-beam writer Electron source Blanking circuit Beam blanker Condense lens CAD PC XY deflection DAC RS232 A SEM internal XY scan signal Magnification, etc Step motor control X Y Object lens aperture Deflection coils Seconduary electron detector Faraday cup and gold standard Sample stage insulator image ADC Im

38 Comparison between 30keV and 100keV e-beam writer Incident electrons resist substrate Distribution of forward electrons Distribution of secondary electrons 30keV 30keV 100keV 100keV 1. Good for prototype test 2. Thin resist line-width < 30nm 3. Clear align key image 4. Good for lift-off process 5. Lack of stage stability 1. Good for large area exposure 2. Thin resist line-width < 10nm 3. Require thick/clear align keys 4. Require extra resist engineering 5. Stable/accurate stage stability

39 Principal of Electron Beam Exposure Electron beam Positive-tone e-beam resist substrate Backscattered electrons secondary electrons traces of electrons After development Proximity effect: main resolution limiting factor primary electrons backscattered electrons secondary electrons stray exposure

40 Lift-off and a) Etching processes PMMA (200~400 nm) substrate spin coating + curing a) PMMA (200~400 nm) substrate spin coating on film electron beam exposure electron beam exposure b) b) braking chemical bonds braking chemical bonds c) resist c) development 100 nm silicon development O 2 plasma reactive ion etching d) d) clean residual resist dry or wet etching deposition acetone bath e) evaporation from point source lift-off e) remove resist f) remove resist

41 Resist profile made by high energy beam exposure 200nm PMMA LOR 500nm

42 Controlling undercut in bottom layer resist (a) (b) (c) 200 Undercut(nm) Linewidth 100nm Linewidth 70nm Linewidth 50nm Linewidth 30nm Linewidth 20nm 1µm Development Time(sec)

43 quasi-3d polymer photonic crystal Transmission spectra, different lattice constants Transmission (a.u.) 400nm Transmission (a.u.) 350nm 2µm Wavelength(nm) Wavelength(nm) Frequency (ω a/2πc) M K TE TM Transmission (a.u.) 300nm Wavelength(nm) Transmission (a.u.) random Wavelength(nm)

44 3D polymer structures 500nm (a) (b) 1µm 2µm

45 Examples of 100keV e-beam lithography 3nm NiCr wire 13nm Au wire 8 nm negative-tone inorganic resist D. R. S. Cumming et al, Microelectronic Engineering 30 (1996), 423 Machine : Modified JEOL 100CXII Kelvin Nanotechnology Ltd M. Kamp et al. J. Vac. Sci. Technol. B, 17, 86, (1999) Machine : Eiko E 100 M. S. M. Saifullah et al., Jpn. J. Appl. Phys. 38 (1999) K. Yamazaki et al., Proc. SPIE (2000) 458. Machine : 100-keV e-beam writer NTT Basic Research Laboratories

46 Sub-10 nm Electron Beam Nanolithography Using Spin Coatable TiO 2 Resists University of Cambridge and Leica Microsystems Lithography Limited Leica VB6-UHR-EWF 100keV M. S. M. Saifullah,et al., Nano Letters, 3, 1587 (2003)

47

48 Issues related to the integrated circuit industry: Slow throughput A 0.1 µm diameter beam is < the area of a 6 wafer. Projection EBL Systems (SCALPEL): scattering with angular limitation in projection electron beam lithography beam of electrons membrane scatterer screening mask Lens 1 back focal plane filter reduced image on Lens 2

49 Multibeam direct-write electron beam lithography system Single source with correction lens array Multi-source with single electron optical column ~50 wafers/hr 2µm ~60 wafers/hr a tip with focus electrode M. Muraki et al. J. Vac. Sci. Technol. B 18(6), 3061, 2000 Canon Inc., E. Yin et al. J. Vac. Sci. Technol. B 18(6), 3126, 2000 Ion Diagnostics Incorporated

50 Take home message: Extreme ultraviolet electron beam projection are considered leading contenders for next generation lithography However, electron beam direct write system is a maskless lithography. eliminating mask amortization costs and speed up chip development cycles. The ultimate resolution of electron beam lithography remains to be explored Main applications: manufacture of small volume specialty products direct write for advanced prototyping of integrated circuits studies of quantum effects and other novel physics phenomena at very small dimensions