IXRFSM18N50 Z-MOS RF Power MOSFET

Transcription

1 N-Channel Enhancement Mode Switch Mode RF MOSFET Low Capacitance Z-MOS TM MOSFET Process Optimized for RF Operation Ideal for Class C, D, & E Applications Symbol Test Conditions Maximum Ratings V DSS T J = 25 C to 15 C 5 V V DGR T J = 25 C to 15 C; R GS = 1 M 5 V V GS Continuous ±2 V V GSM Transient ±3 V I D25 T c = 25 C 19 A I DM T c = 25 C, pulse width limited by T JM 95 A I AR T c = 25 C 19 A E AR T c = 25 C 3 mj V DSS = 5 V I D25 = 19 A R DS(on).34 P DC = 835 W dv/dt I S I DM, di/dt A/ s, V DD V DSS, T j 15 C, R G =.2 5 V/ns I S = >2 V/ns P DC 835 W P DHS T c = 25 C 37 W P DAMB T amb = 25 C 3. W GATE DRAIN Symbol Test Conditions Characteristic Values (T J = 25 C unless otherwise specified) min. typ. max. V DSS V GS = V, I D = 4 ma 5 V V GS(th) V DS = V GS, I D = V I GSS V GS = ±2 V DC, V DS = ± na I DSS V DS =.8V DSS T J = 25C V GS = T J =125C R DS(on) V GS = 2 V, I D =.5I D25 Pulse test, t 3 S, duty cycle d 2% R thjc R thjhs A ma C/W C/W g fs V DS = 5 V, I D =.5I D25, pulse test S T J C T JM 15 C T stg C T L 1.6mm(.62 in) from case for s 3 C Weight 5 g SG1 Features SG2 Isolated Substrate high isolation voltage (>25V) excellent thermal transfer Increased temperature and power cycling capability IXYS advanced Z-MOS process Low gate charge and capacitances easier to drive faster switching Low R DS(on) Very low insertion inductance (<2nH) No beryllium oxide (BeO) or other hazardous materials Advantages SD1 SD2 Optimized for RF and high speed Easy to mount no insulators needed High power density

2 Symbol Test Conditions Characteristic Values (T J = 25 C unless otherwise specified) min. typ. max. R G.5 C iss pf C oss V GS = V, V DS =.8 V DSS(max), f = 1 MHz pf C rss pf C stray Back Metal to any Pin 33 pf T d(on) 4 ns T on V GS = 15 V, V DS =.8 V DSS 4 ns I D =.5 I DM T d(off) R G = 1 (External) 5 ns T off 6 ns Q g(on) 42 nc Q gs V GS = V, V DS =.5 V DSS I D =.5 I D25 13 nc Q gd 2 nc Source-Drain Diode Characteristic Values (T J = 25 C unless otherwise specified) Symbol Test Conditions min. typ. max. I S V GS = V 19 A I SM Repetitive; pulse width limited by T JM 95 A V SD I F = I s, V GS = V, Pulse test, t 3µs, duty cycle 2% 1.5 V T rr 2 ns CAUTION: Operation at or above the Maximum Ratings values may impact device reliability or cause permanent damage to the device. Information in this document is believed to be accurate and reliable. IXYSRF reserves the right to make changes to information published in this document at any time and without notice.

3 Fig. 1 Fig. 2 Typical Transfer Characteristics V DS = 5V, P.W. = 2µS V - 15V Typical Output Characteristics 8.5V ID, Drain Current (A) V GS, Gate-to Source Voltage (V) ID, Drain Currnet (A) 25 8V V 7V 5 6.5V V DS, Drain-to-Source Voltage (V) Fig Gate-to-Source Voltage (V) Gate Charge vs. Gate-to-Source Voltage V DS = 25V, I D = 9.5A, I G = 3mA ID, Drain Currnet (A) Fig Extended Typical Output Characteristics Top 12V - 15V V 9V 8.5V 8V 7.5V 7V Bottom 6.5V Gate Charge (nc) V DS, Drain-to-Source Voltage (V) Fig. 5 V DS vs. Capacitance Fig. 6 Maximum Transient Thermal Impedance Ciss 1. Capacitance (pf) Coss Crss Z(th)JC - ºC/W VDS Voltage (V) Pulse Time - Seconds

4 Fig. 7 Pin Description Symbol Function Pin Number Description SG1 Source-gate side 1, 3 Source connection on gate side SG2 Source-gate side 6, 7, 8 Source connection on gate side SD1 Source-drain side 9, Source connection on drain side SD2 Source-drain side 15, 16 Source connection on drain side Drain Drain 11, 12, 13, 14 MOSFET Drain Gate Gate 4, 5 MOSFET Gate Fig. 8 Package Description IXYSRF XXXXXXXX TPyyww R.O. # Note: 1. ALL LEADS ARE PURE MATTE TIN PLATED. 2. Cu SURFACE OF BOTTOM DCB IS PRE-Ni PLATED UNLESS OTHERWISE STATED 3. Cu SURFACE OF BOTTOM DCB IS ELECTRI- CALLY ISOLATED 2,5V AC FROM ALL OTH- ER LEADS. 4. PIN 2 N/A, missing, used for device orientation. DRAIN GATE SG1 SG2 SD1 SD2

5 Fig. 9 Footprint and PCB layout For optimum results, multiple pins of the same type should be grouped together on the PCB as shown below. This assures wide traces to the attached driver and load, minimizing parasitic inductance. The source pin groups, SG1, SG2, SD1, SD2, are all source connections at the die. For best operation, the source groups would be ideally incorporated into a large contiguous ground plane on the same side of mounting on the circuit board. In other words, instead of routing ground traces to the device during layout, the footprint would be set over a large ground plane with drain and gate traces routed out of the ground plane. This is done during layout by first establishing a polygon that covers the entire PCB, representing the ground plane, and that is poured by the layout software around needed traces. Grouped pins on gate side inch/mm DRAIN GATE Grouped pins on drain side SG1 SG2 SD1 SD2 Doc # ds Rev. 2/2 216 IXYS RF An IXYS Company 169 Oakridge Drive., Suite Fort Collins, CO USA Fax: sales@ixyscolorado.com Web:

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