AOC V Common-Drain Dual N-Channel AlphaMOS

Transcription

1 OC8 Common-Drain Dual N-Channel lphamos General Description Trench Power lphamos (αmos L) technology Low R SS(ON) With ESD protection to improve battery performance and safety Common drain configuration for design simplicity RoHS and Halogen-Free Compliant Product Summary SS I S (at GS =.5) R SS(ON) (at GS =.5) R SS(ON) (at GS =.) R SS(ON) (at GS =.7) R SS(ON) (at GS =.) R SS(ON) (at GS =.5) < mω < mω < 5mΩ < 9mΩ < 6mΩ pplications Typical ESD protection HBM Class Battery protection switch Mobile device battery charging and discharging lphadfn.5x.5_ Top iew Bottom iew Top iew Bottom iew S G Pin S G G S G S Orderable Part Number Package Type Form Minimum Order Quantity OC8 lphadfn.5x.5_ Tape & Reel bsolute Maximum Ratings T =5 C unless otherwise noted Parameter Source-Source oltage Gate-Source oltage Source Current(DC) Note Source Current(Pulse) Note Power Dissipation Note T =5 C T =5 C Symbol SS GS I S I SM P D Maximum Junction and Storage Temperature Range T J, T STG -55 to 5 Thermal Characteristics Parameter Symbol Typ Max Maximum Junction-to-mbient t s R 5 θj Maximum Junction-to-mbient Steady-State 5 8 Note. Mounted on in FR- board with oz. Copper. Note. PW < µs pulses, duty cycle.5% max ± 6.7 Units W C Units C/W C/W Rev..: June 5 Page of 5

2 Electrical Characteristics (T J =5 C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units STTIC PRMETERS B SSS Source-Source Breakdown oltage I S =5µ, GS = Test Circuit 6 SS =, GS = Test Circuit I SSS Zero Gate oltage Source Current µ T J =55 C 5 I GSS Gate leakage current SS =, GS =± Test Circuit ± µ GS(th) Gate Threshold oltage SS = GS, I S =5µ Test Circuit R SS(ON) Static Source to Source On-Resistance 7.8 T J =5 C mω 9. 5 mω mω mω g FS Forward Transconductance SS =5, I S = Test Circuit S FSS Forward Source to Source oltage I S =, GS = Test Circuit 5.65 DYNMIC PRMETERS R g Gate resistance f=mhz KΩ SWITCHING PRMETERS Q g Total Gate Charge GS =.5, SS =, I S = 9.5 nc t D(on) Turn-On DelayTime.8 µs t r Turn-On Rise Time GS =.5, SS =, R L =.Ω,. µs t D(off) Turn-Off DelayTime R GEN =Ω Test Circuit8.5 µs t f Turn-Off Fall Time 6.5 µs THIS PRODUCT HS BEEN DESIGNED ND QULIFIED FOR THE CONSUMER MRKET. PPLICTIONS OR USES S CRITICL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS RE NOT UTHORIZED. OS DOES NOT SSUME NY LIBILITY RISING OUT OF SUCH PPLICTIONS OR USES OF ITS PRODUCTS. OS RESERES THE RIGHT TO IMPROE PRODUCT DESIGN, FUNCTIONS ND RELIBILITY WITHOUT NOTICE. GS =.5, I S = Test Circuit GS =., I S = Test Circuit GS =.7, I S = Test Circuit GS =., I S = Test Circuit GS =.5, I S = Test Circuit mω Rev..: ugust 5 Page of 5

3 TYPICL ELECTRICL ND THERML CHRCTERISTICS 5. DS =5 I S () GS =.5 I S () C 5 C 5 5 SS (olts) Figure : On-Region Characteristics GS (olts) Figure : Transfer Characteristics R SS(ON) (mω) 5 5 GS =.5 GS =.5 GS =. GS =. GS = Normalized On-Resistance...8 GS =. I S = GS =.5 I S = GS =.5 I S = GS =. I S = GS =.7 I S = I S () Figure : On-Resistance vs. Source Current and Gate oltage Temperature ( C) Figure : On-Resistance vs. Junction Temperature 5 I S =.E+.E+ R SS(ON) (mω) 5 C I S ().E-.E-.E- 5 C 5 C 5 C.E- 6 8 GS (olts) Figure 5: On-Resistance vs. Gate-Source oltage.e FSS (olts) Figure 6: Forward Source to Source Characteristics Rev..: ugust 5 Page of 5

4 TYPICL ELECTRICL ND THERML CHRCTERISTICS 5 SS = I S = GS (olts) 6 9 Q g (nc) Figure 7: Gate-Charge Characteristics I S (mps).... R SS(ON) limited T J(Max) =5 C T =5 C µs µs µs ms ms Power (W) T J(Max) =5 C T =5 C DC... SS (olts) GS > or equal to.5 Figure 9: Maximum Forward Biased Safe Operating rea (Note). E Pulse Width (s) Figure : Single Pulse Power Rating Junction-to- mbient (Note) Z θj Normalized Transient Thermal Resistance.. D=T on /T T J,PK =T +P DM.Z θj.r θj R θj =8 C/W Single Pulse In descending order D=.5,.,.,.5,.,., single pulse P D T on T. E Pulse Width (s) Figure : Normalized Maximum Transient Thermal Impedance (Note) Rev..: ugust 5 Page of 5

5 TEST CIRCUIT Isss POSITIE SS FOR ISSS+ NEGTIE SS FOR ISSS- S TEST CIRCUIT Igss, POSITIE GS FOR IGSS+ NEGTIE GS FOR IGSS- S G When FET is measured between GTE and SOURCE of FET are shorted G G SS G S G S TEST CIRCUIT gs(off) When FET is measured S TEST CIRCUIT Rss(on) S ss/is between GTE and SOURCE of FET are shorted G G Is G SS G SS GS S GS S TEST CIRCUIT 5 F(SS), TEST CIRCUIT 6 BDSS POSITIE SS FOR ISSS+.5 S NEGTIE SS FOR ISSS- S When FET measured FET GS=.5 G IF G Is G G SS GS= S S TEST CIRCUIT 7 BGSO, TEST CIRCUIT 8 POSITIE SS FOR ISSS+ Switching time NEGTIE SS FOR ISSS- S S out When FET is measured between GTE and SOURCE of FET are shorted G G in G G IG S S Rev..: ugust 5 Page 5 of 5