AOI472 N-Channel Enhancement Mode Field Effect Transistor

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1 N-Channel Enhancement Mode Field Effect Transistor General Description Features The uses advanced trench technology and design to provide excellent R DS(ON) with low gate charge. This device is suitable for use in PWM, load switching and general purpose applications. Standard product is Pb-free (meets ROHS & Sony 259 specifications). V DS (V) = 25V I D = (VGS = V) R DS(ON) <. mω (V GS = V) R DS(ON) <9.7 mω (VGS =.5V) UIS Tested 93 Rg,Ciss,Coss,Crss Tested IPK D G D S Top View Drain Connected to Tab G S bsolute Maximum Ratings T =25 C unless otherwise noted Parameter Symbol Maximum Drain-Source Voltage 25 Gate-Source Voltage Continuous Drain Current G Pulsed Drain Current C valanche Current C Power Dissipation B T C = C Repetitive avalanche energy L=.mH C T C = C Junction and Storage Temperature Range V DS V GS I DM I R E R T J, T STG ±2 I D to 75 Units V V mj W C Thermal Characteristics Parameter Symbol Typ Max Units Maximum Junction-to-mbient t s 5 2 Maximum Junction-to-mbient R θj Steady-State Maximum Junction-to-Case B Steady-State R θjc 2. 3 lpha & Omega Semiconductor, Ltd.

2 Electrical Characteristics (T J =25 C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units STTIC PRMETERS BV DSS Drain-Source Breakdown Voltage I D =2u, V GS =V 25 V V DS =2V, V GS =V I DSS Zero Gate Voltage Drain Current µ T J =55 C 5 I GSS Gate-Body leakage current V DS =V, V GS =±2V n V GS(th) Gate Threshold Voltage V DS =V GS, I D =2µ 2.5 V I D(ON) On state drain current V GS =V, V DS =5V R DS(ON) Static Drain-Source On-Resistance V GS =V, I D =3 V GS =.5V, I D =2 T J =25 C g FS Forward Transconductance V DS =5V, I D =2 9 S V SD Diode Forward Voltage I S =, V GS =V.7 V I S Maximum Body-Diode Continuous Current DYNMIC PRMETERS C iss Input Capacitance 2 2 pf C oss Output Capacitance V GS =V, V DS =2.5V, f=mhz 5 pf C rss Reverse Transfer Capacitance 2 pf R g Gate resistance V GS =V, V DS =V, f=mhz..5 Ω SWITCHING PRMETERS Q g (V) Total Gate Charge 3 nc Q g (.5V) Total Gate Charge 7 22 nc V GS =V, V DS =2.5V, I D =2 Q gs Gate Source Charge 5.5 nc Q gd Gate Drain Charge 3.5. nc t D(on) Turn-On DelayTime 7.5 ns t r Turn-On Rise Time V GS =V, V DS =2.5V, R L =.Ω, 22 ns t D(off) Turn-Off DelayTime R GEN =3Ω ns t f Turn-Off Fall Time ns t rr Body Diode Reverse Recovery Time I F =2, di/dt=/µs 3 3 ns Q rr Body Diode Reverse Recovery Charge I F =2, di/dt=/µs 9 23 nc : The value of R θj is measured with the device mounted on in 2 FR- board with 2oz. Copper, in a still air environment with T =25 C. The Power dissipation SM is based on R θj and the maximum allowed junction temperature of C. The value in any given application depends on the user's specific board design, and the maximum temperature of 75 C may be used if the PCB allows it. B. The power dissipation is based on T J(MX) =75 C, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. C: Repetitive rating, pulse width limited by junction temperature T J(MX) =75 C. D. The R θj is the sum of the thermal impedence from junction to case R θjc and case to ambient. E. The static characteristics in Figures to are obtained using <3 µs pulses, duty cycle.5% max. F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of T J(MX) =75 C. G. The maximum current rating is limited by bond-wires. H. These tests are performed with the device mounted on in 2 FR- board with 2oz. Copper, in a still air environment with T =25 C. The SO curve provides a single pulse rating. Rev: prial 27 mω THIS PRODUCT HS BEEN DESIGNED ND QULIFIED FOR THE CONSUMER MRKET. PPLICTIONS OR USES S CRITICL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS RE NOT UTHORIZED. OS DOES NOT SSUME NY LIBILITY RISING OUT OF SUCH PPLICTIONS OR USES OF ITS PRODUCTS. OS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS ND RELIBILITY WITHOUT NOTICE. lpha & Omega Semiconductor, Ltd.

3 TYPICL ELECTRICL ND THERML CHRCTERISTICS V V.5V V DS =5V I D () 3.5V 3.V V GS = Fig : On-Region Characteristics I D () C 25 C Figure 2: Transfer Characteristics 93 R DS(ON) (mω) V GS =.5V V GS =V Normalized On-Resistance..2 V GS =V, 3 V GS =.5V, I D () Figure 3: On-Resistance vs. Drain Current and Gate Voltage Temperature 2( C) Figure : On-Resistance vs. Junction Temperature 2 I D =3 25 C R DS(ON) (mω) 25 C 25 C Figure 5: On-Resistance vs. Gate-Source Voltage I S () C V SD (Volts) Figure : Body-Diode Characteristics lpha & Omega Semiconductor, Ltd.

4 TYPICL ELECTRICL ND THERML CHRCTERISTICS 3 2 V DS =2.5V I D =2 Capacitance (pf) 2 2 C oss C iss Q g (nc) Figure 7: Gate-Charge Characteristics T J(Max) =75 C, 2 C rss Figure : Capacitance Characteristics 93 I D (mps) R DS(ON) limited DC µs µs ms Power (W) 2 T J(Max) =75 C.. Figure 9: Maximum Forward Biased Safe Operating rea (Note F) Pulse Width 2 (s) Figure : Single Pulse Power Rating Junction-to- Case (Note F) Z θjc Normalized Transient Thermal Resistance.. D=T on /T T J,PK =T C +M.Z θjc.r θjc R θjc =3 Single Pulse In descending order D=.5,.3,.,.5,.2,., single pulse..... Figure : Normalized Maximum Transient Thermal Impedance (Note F) T on T lpha & Omega Semiconductor, Ltd.

5 TYPICL ELECTRICL ND THERML CHRCTERISTICS I D (), Peak valanche Current T = C Time in avalanche, t (s) Figure 2: Single Pulse valanche capability t L ID = BV V T =25 C DD Power Dissipation (W) T CSE ( C) Figure 3: Power De-rating (Note B) 93 Current rating I D () 3 2 Power (W) 3 2 T =25 C T CSE ( C) Figure : Current De-rating (Note B) Figure 5: Single Pulse Power Rating Junction-to- mbient (Note H) Z θj Normalized Transient Thermal Resistance... In descending order D=.5,.3,.,.5,.2,., single pulse Single Pulse D=T on /T T J,PK =T +M.Z θj.r θj R θj = T on T..... Figure : Normalized Maximum Transient Thermal Impedance (Note H) lpha & Omega Semiconductor, Ltd.

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