Reliability of Nano-Scaled Logic Gates Based on Binary Decision Diagrams

Transcription

1 Reliility o Nno-Scled Logic Gte Bed on Binry Deciion Digrm Am Beg 1 nd Ajml Beg 2 1 College o Inormtion echnology, United Ar mirte Univerity, Al-Ain, UA 2 Cortex Buine Solution, Clgry, AB, Cnd Atrct Binry deciion digrm () hve een ueul or ynthei nd veriiction o digitl circuit. hi pper, or the irt time, look into the reliility o ew logic gte implemented uing. he gte were deigned uing n dvnced CMOS technology node nd uject to threhold-voltge vrition. he reult o the Monte Crlo Spice imultion how tht -ed gte re igniicntly more relile thn their conventionl CMOS counterprt. Keyword: Reliility, ttic noie mrgin (SNM), nnocircuit, inry deciion digrm (), threhold voltge (V H ) vrition, Monte Crlo imultion 1 Introduction 1.1 Nno-cled circuit nd their reliility Nnotechnology i cience, engineering, nd technology conducted t the cle etween 1 to 1 nm [1]. Nnotechnology i n importnt technology o the 21t century, nd i ued or producing dierent product including integrted circuit (IC). New nnodevice nd nnomteril re expected to continue improving o the qulity o humn lie. Scling the emiconductor technology deep into the nnocle llow novel ppliction uch wirele enor network, werle computer, implntle device, etc. he emergence o rel-lie ppliction depend to gret extent on the ility to ricte mll, ultr-low power/energy, yet relile circuit. However, the trnitor/device ie re ggreively hrunk, the mnucturing o IC ecome more complex nd unvoidly introduce more deect. he nnocled device require mll mount o energy or witching, ut re highly uceptile to trnient ilure [2], [3]. Prmeter vrition i yet nother chllenge or relile opertion o circuit nd ytem [4], [5]. hi men tht the reliility need to e dded to the lit o trditionl deign vector (power, dely, nd re) [6]. A trnitor re cled to nno-dimenion, it ecome hrder to limit the vrition o threhold voltge (V H ) o the myrid o trnitor on lrge IC. In MOS trnitor, the vrition o V H occur primrily due to the rndomne o the count nd the poition o the dopnt tom. he V H vrition cn e etimted uing norml ditriution with tndrd devition o [7]: e.4 A 8 tox N σ V (1) H L W where t ox i the oxide thickne, N A i the chnnel doping, W e i the eective chnnel width, nd L e i the eective chnnel length. Undertndly, the V H luctution cn e llevited y increing either L e or W e, or oth [8]. 1.2 Binry deciion digrm he high complexity o tody digitl IC neceitte tht the deign (CAD) tool hndle nd mnipulte the Boolen unction, eiciently poile. In the pt two decde, the inry deciion digrm () hve gined populrity or eicient ynthei nd veriiction o digitl circuit. he were introduced y Lee [9], nd populried y Aker [1] nd Boute [11]. he re ed on the principle o Shnnon expnion [12], nd cn e ued to repreent ny Boolen unction [13]. In generl, i levelied cyclic grph o node. he node on given level repreent one input o the unction. here i n dditionl level (t the ottom) with node nd 1. All node (except the - nd 1- node) hve two outgoing edge connecting to the lower level node. An upper level node cn hve multiple incoming input rom the lower level. A et o input reult in pth leding - or 1-node to the top-level node(), i.e., the output(). A ully-peciied input-et tke exctly one complete pth in the [14]. he typicl -ed deign procedure conit o the ollowing tep: 1. A truth tle o the Boolen unction i determined. 2. Output with 1 in the truth tle re mpped to. 3. he i reduced (while retining it logicl propertie). 4. ch node in the i implemented uing multiplexer circuit. Generlly, the cn e impliied uing thee two technique: e

2 x y y x () () Fig. 1. xmple o () in it non-impliied orm, nd () in the reduced orm (=true; =ele/le) 1. Redundnt node re deleted. A redundnt node i node whoe two child node re identicl. 2. quivlent node re hred. he equivlent node re two or more node tht hve the me vrile nd the me pir o child node. A mple repreenting the ollowing Boolen unction (um-o-product/sop) i hown in Fig. 1(). Ater impliiction, the reduce to the orm drwn in Fig. 1(). 1.3 Aout thi pper Our i the irt known eort to evlute the reliility o -ed circuit relied with n dvnced (22nm CMOS) technology node. hi pper preent our inding out the reliility o three ic logic gte implemented with multiplexer. We ue ttic noie mrgin (SNM) the metric or the gte reliility [15]. 2 Relted work he hve een extenively ued or deigning optimum logic circuit [14] [16]. Simple Boolen unction like dder nd comprtor h een implemented uing [17] [19]. More complex computing circuit uch cipher nd crypto hve lo een deigned [2]. he evlution time o i relted to it pth length nd thi reltionhip w invetigted nd modeled in [21][22]. Low power -ed deign hve een invetigted in [23] [26]. In ddition to power, [25] lo conider dely o the circuit. Power nd re-eicient deign o n ynchronou dder w looked t in [27]. he repreenttion hve een ued to model the reliility o dierent ytem [28] [3] ut the reliility o -ed circuit themelve h not een reported in ny reerch literture. he reliility o gte uing trditionlly- nd nonconventionlly-ied trnitor hve een looked into [31] [36]. hi pper preent the reult o our invetigtion o the reliility o three ic logic gte implemented uing. 3 xperimentl reult nd nlyi For etimting V H nd it vrition, we hve ued the MOS model rom BSIM4 v4.7 level 54 [37]. For modelling the conventionl nd -ed gte, we hve ued 22 nm PM HP v2.1 (high-k/metl gte nd tre eect) trnitor model [38], [39]. We hve imulted the gte uing NGSpice [4]. he or the three undmentl gte, INV, NAND2, nd NOR2 re hown in Fig. 2 () (c), nd the correponding multiplexer-ed implementtion re hown in Fig. 2 (d) (). he multiplexer re uilt uing the well-known compound-aoi22 conigurtion o Fig. 3. he trnitor dimenion in ll the experiment re ixed t: L nmos = L pmos = L min = 22 nm, W pmos = 88 nm, nd W nmos = 44 nm. he upply voltge (V DD ) i et t.8v (i.e., the nominl voltge peciied in 22nm PM HP model [38], [39]). We ued the SNM meure o relile opertion o logic gte. In order to meure the SNM, we ued the tet etup o Fig. 4() or the INV, nd the etup o Fig. 4() or oth NAND2 nd NOR2. Undertndly, or the INV, ingle rmp timulu i uicient, while the other gte need dierent comintion o contnt nd rmp input tht reult in trnitioning o the output. For NAND2, the input re: 1 11, 1 11, nd 11; nd or NOR2, the input re: 1, 1, nd 11. We ue Unix-hell nd Mtl cript to ind the SNM. he hell cript pre the imultion log ile to extrct clen,

3 () () 1 (c) 1 (d) (e) () Fig. 2. or () INV, () NAND2, nd (c) NOR2; multiplexer-ed implementtion o (d) INV, (e) NAND2, nd () NOR2 Mtl-riendly text ile. he Mtl cript utomticlly determine: the highet llowed input voltge or logic low (V IL ); the lowet llowed input voltge or logic high (V IH ); the highet output voltge or logic low (V OL ); nd the lowet output voltge or logic high (V OH ). hee our voltge level re then ued to clculte the SNM ollow: SNM low = V IL V OL (2) SNM high = V OH V IH (3) SNM = min (SNM low, SNM high ). (4) An INV h ingle vlue o SNM; ee the voltge trner curve (VC) o Fig. 5(). In comprion, NAND2 nd NOR2 hve three dierent et o VC, hown in Fig. 5(), reulting in three dierent SNM we chooe the wort/let o the three vlue the gte SNM. In thi pper, we hve elected 2% ( common threhold) the minimum cceptle SNM. Stted dierently, gte h iled, i it SNM i le thn 2% o V DD. We conducted 1 Monte Crlo imultion or ech o three gte (INV, NAND2, nd NOR2) in two dierent conigurtion (in other word, totl o 6 imultion): (1) the norml/conventionl CMOS deign [41], nd (2) ed deign (Fig. 2(d) ()). he V H o the trnitor in the gte (o oth type) were vried ccording to eqution (1). A numericl comprion o the SNM vrition or the three gte in the norml- nd the -implementtion i hown in le 1 nd 2. he hitogrm o the SNM o the gte re hown in Fig From le 1, we oerve tht -ed gte hve conitently lower ilure thn the norml one. he norml INV h 6% ilure compred to none or the verion. NAND2 ilure rte re 25% nd 2.7% or the norml nd the -type, repectively. Norml NOR2 il 17.5% o the time, while the -verion il in jut.2% o the imultion. hee ttitic how tht -ed gte i pprecily more relile thn norml one. Additionlly, the INV due to it impler contruction h lower ilure rte thn the two-input gte. Both type o NOR2 hve higher reliility thn NAND2. Beide the tructurl dierence etween the NAND2 nd NOR2, the reliility o NAND2 nd NOR2 lo depend on the input vector [42]. le 2 ummrie the eect o V H vrition on the SNM o the three gte. INV o oth type, norml nd, hve the highet SNM. NOR2 hve higher verge- SNM (5-7%) thn NAND2. he -ed INV h 71% higher verge-snm thn the norml one, where NAND2 nd NOR2 hve 85% nd 83% higher SNM, repectively. he tndrd devition or SNM o norml nd -gte re quite comprle. -NAND2 how higher pred thn the norml one, while NOR2 i jut the oppoite.

4 he reult o our experiment how tht the -ed gte cn e more rout nd relile lterntive to the conventionl gte. However, it i oviou tht the mniettion o the three gte occupy more re thn the conventionl one. One lo h to compre the power nd the dely o the nd the norml gte ocu o our current work. 4 Concluion We hve explored the reliilitie (meured in term o SNM) o -ed gte nd compred them to the conventionl CMOS gte. he -gte hve igniicntly higher SNM thn the conventionl gte. V DD in in 1 Fig. 3. Schemtic o 2-1 multiplexer he higher noie mrgin come t the higher re cot nd poily the dely nd the power uject o our continued invetigtion. Ue o dierent multiplexer circuit or the relition o the -node i lo eing looked into. Rmp input Unit under tet he three -ed ic gte in thi pper hve een hndcrted. o cilitte reliility tudie o other gte/cell nd lrger circuit, we would need n utomted mechnim or creting oth the -decription nd the correponding multiplexer-ed implementtion yet nother plnned extenion to our work. Rmp input Contnt input () Unit under tet 5 Reerence () [1] [2] C. Contntinecu, rend nd chllenge in VLSI circuit reliility, I Micro, vol. 23, no. 4, pp , 21. [3] P. Shivkumr, M. Kitler, S. W. Keckler, D. Burger, nd L. Alvii, Modeling the eect o technology trend on the ot error rte o comintionl logic, in Fig. 4. et etup or meuring the SNM o () n INV, nd () NOR2 gte Interntionl Conerence on Dependle Sytem nd Network, 22, pp [4] SIA, Interntionl echnology Rodmp or Semiconductor (IRS), Semiconductor Indutry >11 1 >11 > V in V in () () Fig. 5. Voltge trner curve or meuring the SNM o () n INV, nd () NAND2,

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7 4 35 Stndrd 1 9 Stndrd Occurrence Occurrence SNM SNM Fig. 6. Hitogrm o SNM or norml nd -ed INV Fig. 7. Hitogrm o SNM or norml nd -ed NAND2 9 8 Stndrd 7 6 Occurrence SNM Fig. 8. Hitogrm o SNM or norml nd -ed NOR2