Calculation of Leakage Current in CMOS Circuit Design in DSM Technology

Transcription

1 Interntionl Journl of Coputer Applictions ( ) Volue 155 No 11, Deceer 2016 Clcultion of Lekge Current in CMOS Circuit Design in DSM Technology Shy Mni Pndey Tru College of Science nd Technology Bhopl, Indi Presh Rwt Tru College of Science nd Technology, Bhopl, Indi ABSTRACT With the continuously growing quest for inituriztion of circuit technology, one of the prie focuses of the reserch hs shifted in the direction of ultr low power circuit designs. As the size of chips is shrinking nd the density is incresing siultneously, losses re incresing ostly in the for of power dissiption. Bsed on vrious preters of perfornce evlution in VLSI circuit nd the continuously growing quest for highly efficient nd ultr shrunk devices, hs copelled the reserchers nd designers to coe up with iproved designs which re highly efficient nd fesile. In this Pper we hve clculte lekge power t different input vector cointion with different technology to identify the effect of chnnel length reduction in CMOS technology. All siultion is perfored over on Conventionl NAND gte with vrition of trnsistor y using Berkley Predictive Technology Mode t 65n technology y using HSPICE siultor nd nlyse in ters Power consuption, dely nd PDP with supply voltge of 1V t 0MHz frequency. Keywords Low Power, Vrition in NAND Gte, CMOS, GIDL, PDP. 1. INTRODUCTION The rpid dvnceent in seiconductor technology in electronic devices, over the yers hs resulted in etter perfornce nd higher circuit densities. Astonishing technicl dvnces in seiconductor friction, circuit design techniques nd coputer rchitecture hve enled n exponentil increse in the perfornce nd integrtion density of icroprocessors. As feture size continues to shrink, ore nuer of trnsistors cn e pcked into the se chip re, enling lrge increses in the trnsistor count per chip. However, s the size is getting sller nd the integrtion density increse, the incresing power dissiption hs ecoe priry concern for further developent of VLSI circuit technology. A nuer of techniques hve lredy een proposed for reducing power dissiption. The two iportnt types of power dissiption in VLSI circuits re 1) Sttic power dissiption nd 2) Dynic power dissiption. While sttic power dissiption is due to internl lekges in devices during the off stte of circuit [1], dynic power dissiption is ecuse of the energy loss during chrging nd dischrging of the output node cpcitnce of trnsistor when switching tkes plce. Ltely, dynic power dissiption hs een the priry concern of designers. Different technologies hve een introduced over the yers which re su-threshold logic [3], ulti-threshold logic [4] nd sttic logic circuit [2]. Sttic logic, which utilizes AC voltge supply s opposed to DC voltge supply so s to recycle the energy of circuits, proising lterntive to CMOS, is novel low power circuit technology. In contrst to conventionl CMOS circuits where energy stored in lod cpcitors is dissipted to ground, ditic logic offers wy to reuse this energy. Coining the ides of conventionl logic with the ditic logic circuits together, power dissiption cn e reduced drsticlly [5-7]. This pper hs huge potentil for reduction of lekge power in section 2 previous reserch work done so fr in the field of Low power technology. It sus up work of different uthors which hs een pulished in different journls over the yers. Section 3 shows the results nd siultion prt coprison is drwn in etween ll the siultions done to show the effectiveness of different logic filies over others. In Section IV drwn conclusions sed on the entire work done nd fro the siultion work nd results evluted 2. LITERATURE SURVEY 2.1 Lekge Power Consuption in CMOS IC Scling down of the technology needs to reduce supply voltge due to PD nd tter of consistency. However, it requires the reduction of threshold voltge (VTH) of the devices to intin resonle gte overdrive (VDD-VTH) [8], the VTH reduction result in n exponentil increse in ISUB, oreover to control Short Chnnel Effects (SCE) nd to intin the trnsistor derive strength t low VDD, Oxide thickness (TOX) need to e lso scles down. The ggressive scle of TOX result in high tunneling current over the gte dielectric [8], dditionlly, scled devices require the use of the higher sustrte doping density. It cuses considerly lekge current through these Drin (D) nd Source(S) to sustrte (B) junction under higher reverse ising [8-11]. These re the three jor contriutor of the lekge echnis: Suthreshold lekge current (ISUB), gte oxide tunneling current (IGATE) nd reverse is PN junction current (IBTBT). In ddition to these three jor lekge coponents, there is other ones like Gte Induced Drin Lekge (GIDL) nd punch through, those coponents cn e neglected in typicl ode of opertion. In DSM technology three dointion lekge current occurred in the CMOS device such s ISUB, IGATE, nd IBTBT, s shown in Figure 1. S G Sustrte Bulk D Gte Lekge Suthrehold Lekge Reverse Bised Junction BTBT Figure 1. Shows Vrious Lekge current in DSM technology 22

2 Interntionl Journl of Coputer Applictions ( ) Volue 155 No 11, Deceer Lekge power dissiption Totl Power dissiption is clculted s:- P T = P D + P ST + P Short-circuit + P Sttic-DC Where PT is the dynic or switching power dissiption, occurs due to chrging or dischrging the prsitic cpcitnces in node voltge trnsition. PST is the sttic or lekge power dissiption, cointion of the suthreshold lekge power due to the not idel off stte. PShort-circuit is the short circuit power dissiption occurs during switching opertion when oth the Pull Up nd Pull Down networks re in ON stte. P Sttic- DC is the sttic DC power dissipted The in power contriution is CMOS technology is siclly Su-threshols Lekge nd gte oxide lekge current is the doinnt in nnoeter regie [12-16]. ) Su-threshols Lekge Su-threshold lekge current is very significnt coponent of the lekge power nd this current psses fro drin to source through the chnnel [6-7]. The su-threshold lekge current is cused siclly due to crrier diffusion etween the source nd drin region of the trnsistor in wek inversion. For prticulr MOS trnsistor whenever pplied gte to source voltge is less thn the threshold voltge of the trnsistor, there is no flow of current. Mtheticlly When I ds =0 V gs < V t ) Gte oxide tunnelling current Tunnelling through gte oxide occurs ecuse thickness of gte oxide lyer is grdully reduced s technology is reducing[7]. The gte oxide tunnelling current is cused ecuse of tunnelling of electrons through nmos cpcitor with hevily doped n+ polysilicon gte nd p type sustrte. M1 VDD M3 M4 Figure.2. Grphicl representtion of 2input NAND gte During opertion of two input NAND gte (i.e. input vector 00 ), then trnsistor M1 nd M2 turn ON nd trnsistor M3 nd M4 turns of in which tke prt in lekge current. When input vector(i.e. is 01) the trnsistor M2 nd M4 turn off nd tke prt in lekge contriution, t input vector M1 nd M3 turns off nd tke prt in lekge current contriution. When input vector is 11 xiu lekge current flows y the two M1 nd M2 trnsistor. These preters re Lekge Current (ILek), Sttic Power dissiption (PST) nd Dynic Power dissiption (PD), Totl Power (PT), dely nd PDP. Perfornce of CMOS circuits is depends on these preters. M2 y For DSM circuits inly ISUB is the dointing coponent of power dissiption in CMOS IC s shown in Figure.2. Hence dynic nd short circuit power dissiption re jointly clled switching power dissiption. The resons for sttic or lekge power dissiption re lekge currents, reverse ised currents nd sustrte injection currents, which flow through the trnsistors in its stedy sttes [20-24]. Switching power dissiption rises due to the chrging nd dischrging of output lod cpcitnce during switching. Short- Circuit power dissiption is cused y currents flowing directly fro supply to ground for very short period of tie when the p-device is eing turned OFF nd the n-device is eing turned ON during switching. When the logic 0 is pplied t the input terinl of CMOS, NMOS trnsistor will turn OFF nd PMOS will turn ON. As result logic 1 will e ville t the output node. When logic 1 is pplied t the input, NMOS turns ON nd PMOS goes in OFF stte, Thus there will e logic 0 t the output node. Power dissiption in CMOS trnsistors occurs inly ecuse of the device switching opertions. At ech chrging nd dischrging opertion, there is n inevitle energy loss of CV 2 dd for sttic CMOS circuits. During chrging opertion, the energy dissiption through pull-up lock fro power supply is equl 2 to CV dd, of which hlf of the energy (0.5CV 2 dd ) is stored in lod cpcitor. The other hlf is dissipted through the resistive pth, nd lost s het to the environent. Now during the opertion of dischrging, the residul energy stored in the lod cpcitor (0.5CV 2 dd ), will e relesed to the ground through pull-down network A grph is prepred y nodes nd links, which represented y trnsistors nd their interconnection respectively. Figure 2, shows the Grphicl representtion of 2 input NAND gte. Here, re the inputs nd y is the output of the given circuit. VDD nd re the power supply nd ground nodes. This logic gte is used s sic gte for ipleenttion of every other gte for siultion. It is used CMOS logic design style. Here two input NAND logic gte is used s sic gte for ech logic nd cointionl circuit. Firstly NAND gte nd its vrints re creted using CMOS design style. Secondly ll the test circuits re ipleented y NAND gte nd nlyzed y using these vrints. it. For Siultion HSPICE is tken s siultor tool. It requires spice code (Trnsistor level netlist) of the desired circuit for their preters clcultion. All the circuits re pped with 180n, 130n, 90n, 65n nd 45n BPTM technology file. This file contins every physicl design detils of CMOS trnsistor, where 45n is the effective length of CMOS trnsistor. All kind of nlysis with pping of this file is shown through the flow of HSPICE design flow. 3. RESULTS AND SIMULATION Fro the siultion we nlyse tht s we scle town the technologies in deep suicron regie lekge current dointed fro Tle I. it is oserve tht when we ove for 180n towrds 45n thn lekge current increses drsticlly upto 94.94% due to reduction of the threshold voltge of CMOS trnsistor, s we scle down the chnnel length lekge current increses. Siultion of two inputs Nnd is done for ll the input vector cointion fro the Tle I. We oserve tht xiu lekge current flows t 11 input vector cointions t 90n, 65n, nd 45n CMOS technology respectively. All the siultion is perfored y using BPTM lirries in HSPICE siultor t 180n, 130n, 90n, 65n nd 45n with lod cpcitnce of 1pF with MHz frequent t supply voltge of 1.8V, 1.5V, 1.2V, 1V nd 0.9V power 23

3 Lekge(nA) Interntionl Journl of Coputer Applictions ( ) Volue 155 No 11, Deceer 2016 supply to nlyse the vrition of lekge current with different technology nd different supply voltge over sller chnnel device. In Tle II. We hve copred vrious lekge reduction techniques to develop new technique for fruit full reserch. Tle I. Lekge current of 2 Nnd Gte Lekge Current (A) for 2 input Nnd Gte Technology (0,0) (0,1) (1,0) (1,1) 180n 6.560p 254.4p 208.3p 41.83u 130n 36.66p 6.227n 4.874n 15.45n 90n 88.33p 1.924n 1.593n 4.122n 65n 167.7p 2.630n 1.975n 2.526n 45n 129.6p 3.607n 2.239n 4.4u Averge power clcultion is done for 2 inputs Nnd Gte t different technology we oserve tht s we scle down the chnnel length verge power lso reduces fro Tle II. We nlyse tht sving of verge power 86.82% with 130n, 12.25% with 90n, 17.85% with 65n t 00 input vector cointions. We lso oserve tht verge power consuption is lower t 00 input vector cointion nd xiu t 11 input vector cointions respectively. Tle II. Averge Power consuption of 2 NAND Gte Averge Power consuption (µw) for 2 input Nnd Gte Technology (0,0) (0,1) (1,0) (1,1) 180n 130n 90n 65n 45n 4.5E- 1.6E E- 2.8E- 3.7E- 3.7E- 7.3E- 1.4E- 1.8E- 2.3E E E E E E- 7.5E E E- 2.7E- 3.7E- 06 Fro Tle I nd II. we oserve the ipct of technology scling nd drw the grph lekge current versus technology it is clculted tht lekge current increse s we ove fro 130n towrds 90n, 65n nd 45n respectively s shown in Figure Lekge Current(nA) Technology 130 n 90n 65n 45n Figure.3. Grph for vrition of lekge current with the vrition of technology. Cointionl circuit ipleenttion nd siultion detils re discussed in this chpter. Here two input NAND logic gte is used s sic gte for ech logic nd cointionl circuit. Firstly NAND gte nd its vrints re creted using CMOS design style. Secondly ll the test circuits re ipleented y NAND gte nd nlyzed y using these vrints s shown in Figure.4. P1 V DD P2 P3 N1 Vout N2 () 24

4 Interntionl Journl of Coputer Applictions ( ) Volue 155 No 11, Deceer 2016 V DD For Siultion HSPICE is tken s siultor tool. It requires spice code (Trnsistor level net-list) of the desired circuit for their preters clcultion in Tle III. P1 P2 P3 N1 Vout N2 () Figure.4. Vrition of two input NAND Gte for Lekge Reduction Tle.III. Clcultion Two input NAND gte with Vrints V1, V2, V3, nd V4 results (i) For Stndrd NAND Gte I Lek (na) P ST (nw) + P DY (uw) = P T (uw) [00] =.1906 Dely (ii) NAND Gte with Vrition one I Lek (na) P ST (nw) + P DY (uw) = P T (uw) [00] =.1706 [01] =.2005 [01] = [] =.1925 [] =.1725 [11] =.2170 [11] =.1853 (iii) NAND Gte with Vrition two (iv) NAND Gte with Vrition Three Dely 8.58 I Lek (na) P ST (nw) + P DY (uw) = P T (uw) Dely I Lek (na) P ST (nw) + P DY (uw) = P T (uw) Dely [00] =.1206 [00] =.1506 [01] =.1224 [01] = [] =.1225 [] =.1525 [11] =.1238 [11] = Aove tles shows results for verge power dissiption, dely nd power dely product for the conventionl NAND Fro the grphicl nlysis presented chieves even lesser power dissiption s copred to ll other NAND Gte s shown in Tle.III. Vrition of V1 NAND gte consues 43.24% lesser power s copred to conventionl NAND gte. Vrition of V2 gte consues 39% lesser power s copred to conventionl NAND gte. Vrition of V3 consues 29% lesser power s copred to conventionl XOR gte nd Vrition of V4 chieves 35% lesser power. 4. CONCLUSION The reserch provides intense focus on lekge current/power nlysis nd next genertion DSM technology. It reflects upon dointing fce of lekge power dissiption such s ISUB, IGATE, nd IBTBT which re creting higher lekge in DSM VLSI design during idle ode. It proposes technique for reducing the lekge current during idle ode of circuit. As the quest for ultr-low power circuit designs goes on incresing, these iproved circuit technologies would prove to e very useful in serving the need for ultr low power circuit designing. We hve copred the results for the lest power dissiption chieved using proposed 5. REFERENCES [1] Bohr MT. Nnotechnology gols nd chllenges for electronic pplictions. IEEE Trnsctions on Nnotechnology, pp , Mrch [2] The Interntionl Technology Rodp for Seiconductors, Nov

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