High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology

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1 High Rdix Addition i onditionl hrge Trnport in Single Electron Tunneling Technology or Meenderinck, Sorin otofn nd per Lgeweg omputer Engineering L Delft Univerity of Technology Delft, The Netherlnd Atrct Thi pper invetigte the implementtion of high rdix ddition ed on the Electron ounting logic deign tyle in Single Electron Tunneling (SET) Technology. A previou propol for uch n dder umed the preence of conditionl chrge movement (Mke) lock which w only decried lck ox. Firt, thi pper propoe two poile Mke lock implementtion, ech of which i decried in detil nd vlidted y men of imultion. Second, one of the propoed Mke implementtion i utilized in the deign of 6-it rdix-8 dder. The reulting dder circuit i verified y imultion nd evlution indicted tht it require 87 circuit element, h dely of.5 n (uming n error proility P error = 8 ), nd conumed energy of me.. Introduction Expected limittion to the clility of exiting emiconductor technologie neceitte the invetigtion of nnoelectronic technologie uch Single Electron Tunneling (SET) [7]. Although SET ed logic nd rithmetic circuit cn e deigned in conventionl logic deign tyle, e.g., uing Boolen nd/or threhold gte (ee for exmple [6]), the recently propoed Electron ounting (E) prdigm pper promiing for the efficient implementtion of SET ed rithmetic opertion. The electron counting methodology i ed on repreenting integer vlue y numer of electron. Electron re kept in chrge reervoir nd rithmetic computtion re done mong thee reervoir. Uing thi prdigm, lgorithm nd circuit for performing ddition/utrction nd multipliction hve een devied []. The propect for E circuit re good in theory, however prcticl pect my reduce their effective performnce. Firt, the numer of electron tht cn e moved y E circuit i limited. Second, the dely of the circuit i proportionl to the numer of electron tht mut e moved. Becue of thee two pect high-rdix E ed ddition cheme w lo propoed in []. While thi propol cn certinly del with the retriction impoed y certin SET friction technology t the lgorithmic level, ome circuit level pect where left open. The cheme for high rdix ddition ume key circuit element conditionl chrge trnporttion lock (Mke) tht w decried lck ox only. In thi pper we propoe two poile implementtion of the Mke lock, ech of which i decried in detil nd vlidted y men of imultion. Second, one of the propoed Mke implementtion i utilized in the deign of 6-it rdix-8 dder. The reulting dder circuit i verified y imultion nd evluted in term of re, dely, nd conumed energy. The reminder of thi pper i orgnized follow. Section riefly decrie the electron tunnel SET phenomenon nd introduce the E ed high rdix dder. Section 3 decrie the two propoed Mke implementtion. Section preent 6-it rdix-8 dder ed on the propoed Mke lock nd Section 5 conclude the pper.. Bckground SET circuit re ed on tunnel junction which conit of n ultr-thin inulting lyer in conducting mteril (ee Figure ). In clicl phyic no chrge trnport i poile through n inultor. However, when the inulting lyer i thin enough the trnport or tunneling of chrge cn e controlled in dicrete nd ccurte mnner, i.e., one electron t time. Tunneling through junction ecome poile when the junction current voltge j exceed the junction criticl voltge c = q e ( e j) [], where q e =.6 9, j the cpcitnce of the junction nd e the cpcitive vlue of the reminder of the circuit een from the junction. In other word, tunneling cn occur if nd only if j c. Electron tunneling i tochtic in nture nd uch the dely cnnot e nlyzed in the trditionl ene. Inted, for ech trnported electron one cn decrie the witching dely t d = ln(perror)qert j c, where R t i the junction Proceeding of theth Interntionl onference on Appliction-Specific Sytem, Architecture nd Proceor (ASAP 5) 3-686/5 $. 5 IEEE

2 metl Emedding ircuit inultor metl ymol Figure. Schemtic repreenttion of the tunnel junction. reitnce nd P error i the chnce tht the deired chrge trnport h not occurred fter t d econd. In thi pper we ume R t = 5 Ω nd P error = 8. Ech trnported electron reduce the ytem energy y E = q e ( j c ) from which the conumed energy cn e clculted. Note tht the implementtion dicued in here re technology independent. SET tunnel junction cn for exmple e implemented y clicl emiconductor lithogrphy nd y cron nnotue [3]. Therefore, circuit re i evluted in term the totl numer of circuit element (cpcitor nd junction). The ility to control the trnport of individul electron mke it poile to encode integer vlue X directly chrge Xq e. hrge encoded vlue re tored chrge on reltively lrge cpcitor ( chrge reervoir). Once integer vlue hve een encoded numer of electron, one cn perform rithmetic opertion directly in electron chrge. Thi revel rod rnge of novel computtionl cheme which re generlly referred to Electron ounting (E). An E ed n-it dder cheme w propoed in []. Expected prcticl limittion impoed y the mximum mount of trnportle electron were reolved y n E ed n-it rdix-r dder cheme. A 6-it rdix-8 dder ed on the ltter i depicted in Figure. Ech M i e lock dd i q e chrge to their repective chrge reervoir (R or R ) when the correponding input ( i or i )i logic. onequently, chrge reervoir R nd R contin the intermedite um IS =Σ i= ( i i i i )q e nd IS =Σ 5 i=3 ( i i i i )q e, repectively. If the intermedite um IS > 7q e, crry ignl i generted y the Me lock, dding q e chrge to R, thu conditionlly moving q e chrge. Finlly the chrge vlue preent in R nd R re ech converted to inry repreenttion y men of three nd four lock, repectively. A poile implementtion of the Mke uilding lock (Figure 3) w propoed in [] nd operte follow. While R (reet) nd re zero nd input E (enle) i et to, the voltge over junction () pproche it criticl voltge. If now i et to the criticl voltge i exceeded nd one electron tunnel from node M to node N. A reult of thi event poitive chrge i preent on node A B R Me A B R Figure. Orgniztion of the 6-it rdix-8 dder. R E r e v N M P t i Electron Reervoir Figure 3. Mke lock implementtion. M, which cue the voltge over junction () to exceed it criticl voltge nd o one electron tunnel from node P to node M. Thi proce of two tunnel event continue until the voltge over junction h dropped elow the criticl voltge gin. The numer of electron k tht i removed from the chrge reervoir i proportionl to the mgnitude of oth nd v. A lock with input I implement periodic ymmetric function whoe output i logic within n intervl T, trting t I = T, nd with period P. For exmple, the lock clculting h T =, P =, nd implement n XOR function. An implementtion of the lock i depicted in Figure nd w lo propoed in []. The cpcitor c nd the tunnel junction t form n electron trp, which h periodic trnfer function. If the input voltge rie, the output voltge follow, due to cpcitnce diviion. At ome point, though, the voltge over the tunnel junction exceed the criticl voltge nd n elec- 3 5 out Proceeding of theth Interntionl onference on Appliction-Specific Sytem, Architecture nd Proceor (ASAP 5) 3-686/5 $. 5 IEEE

3 tron tunnel to the output node. The output voltge drop therefore. A the input voltge continue to rie, the output voltge rie gin until it reche the criticl voltge. To otin implementtion SET inverter [5] cn e dded, which function literl gte. A long the input i elow the threhold vlue, the output i, if the input exceed the threhold, the output vlue ecome. c t T g g g g Figure. lock implementtion. While the implementtion of the Mke nd the lock were propoed in [] no implementtion of the Me uilding lock w introduced. The next ection propoe two poile implementtion of generlized verion of the Me lock, i.e., the Mke lock, tht move kq e chrge into chrge reervoir if it input vlue exceed certin vlue. Such lock contitute generliztion of the Me lock nd it i lo ueful for wider rnge of E ed rithmetic opertion including multipliction []. 3. onditionl hrge Trnport Block The Mkelock h two Boolen input (enle e nd reet r ), one nlog input v, nd one output connected to chrge reervoir. Note tht the voltge v cn e either voltge ource or the vlue of chrge reervoir. If e =, r =, nd v exceed threhold ψ, then the lock remove k electron from the chrge reervoir connected to the output. If r = (reet) nd e = ll the electron which were removed from the reervoir re returned. In the following uection we propoe two poile implementtion of the Mke lock. 3.. Implementtion A The functionlity implemented y n Mke lock cn e thought of coniting of two tge. The firt tge detect whether v exceed the threhold vlue ψ. If v >ψ, the Boolen output Y of the firt tge i et to, otherwie it i et to. onequently, the opertion performed y the firt tge of the Mke lock cn e decried n -input threhold function. The SET threhold gte propoed in [] cn e utilized to relize the firt tge of Implementtion A. o Fp The econd tge of the lock remove k electron from chrge reervoir when r = nd e = y =. The Mke lock propoed in [] perform imilr function nd cn e djuted to operte pecified ove. onequently, the econd tge of Implementtion A i formed y n Mke lock, reulting in the circuit depicted in Figure 5. Note tht the OpAmp in Figure 5 erve uffer. We note here tht OpAmp cn potentilly e implemented uing hyrid FET-SET technology [, 8]. To properly et the prmeter vlue of the Mkelock the following eqution were ued. When input y of the Mke lock i, the input e hould cue the voltge over junction (J) to e very cloe to it criticl voltge. Thi i decried y Eqution (), in which c i the criticl voltge of J, nd Σn, Σm re the totl cpcitnce connected to node N, M, repectively. [ Σm ] e Σn e = c Σm ɛ () The fctor ɛ repreent the mll vlue tht the voltge cro J i elow it criticl voltge nd cn e clculted from the following eqution ɛ = q e [ cr [ Σm ] Σn ], () where cr i the cpcitor implementing the chrge reervoir. The numer of electron k tht i trnported y the Mke lock i proportionl to the input voltge y, which i expreed y the following eqution: [ ] Σn v y = cr [ Σm ] kq e. (3) For complete overview of the eqution decriing the Mke the reder i referred to [9]. r r e e j Y y N X M v v p w t Threhold gte Mke lock Figure 5. Mke lock Implementtion A. We hve verified n intnce of Implementtion A y men of imultion uing the SET imultion pckge SI- MON []. Simultion reult were otined uing the following circuit prmeter. In the reminder of thi pper we ue logic = m, logic = m, nd cpcitnce F for ll chrge reervoir, in correpondence with previouly deigned E uilding lock []. Auming threhold voltge of.m, needed for the high i P cr Proceeding of theth Interntionl onference on Appliction-Specific Sytem, Architecture nd Proceor (ASAP 5) 3-686/5 $. 5 IEEE

4 rdix dder preented in Section, we clculted the following prmeter for the threhold gte: w = F, j =.5F, p =5F nd =7.F. The voltge wing on the output of the threhold gte w clculted 5m. Fork =the following prmeter were derived for the Mke lock: v =.F, e =6.F, t = 3.F, r =5F, i =F nd = =.5F. The imultion reult re preented in Figure 6. The top three r repreent the input R, E nd while the two ottom r repreent the chrge preent in the output reervoir nd the voltge cro cr, which implement the reervoir. The input trt t.m nd witche to.3m t t =.35, t which point the threhold vlue i exceeded nd chrge trnport occur. Implementtion A w imulted for everl vlue of k nd ll imultion indicte tht thi uilding lock function correctly..8. R (m) E (m) (m) Q_cr (q_e) _cr (m) Time () Figure 6. Simultion reult for k =for the Mke Implementtion A. 3.. Implementtion B A didvntge of Implementtion A i the need for uffer to connect the threhold gte to the Mke lock. To void the ue of uch uffer the Mke lock w modified reulting in new uilding lock clled the Modified Move k electron (MMke) lock. The econd implementtion of the Mke lock i ed on the utiliztion of n MMke lock in the econd tge nd it i depicted in Figure 7. The MMkeuilding lock function lightly different thn the Mke lock. The enle ignl e i ued to et poitive voltge over junction (J) nd junction (J). pcitnce vlue re uch tht the voltge over junction i cloe to it criticl voltge while the voltge over junction ty elow it criticl voltge. The driving input y i connected through cpcitor to the centrl node M. If y = no tunnel event cn tke plce, ut if y = the voltge over J exceed it criticl voltge nd k electron tunnel from node P to node N. Actully the input i not voltge driven ut chrge driven ince it i connected to the chrge reervoir w. The preence of chrge in the reervoir reult in voltge y, o the ttement ove remin vlid. In decriing the functionlity mthemticl, though, we do not ue thi voltge ut only the chrge in the reervoir. To properly et the prmeter vlue of the MMke lock the following eqution were ued. Auming the input y i, while r =, the input e hould cue the voltge over J to e cloe to it criticl voltge, which i expreed e Σn e = c Σm ɛ m, () where c i the criticl voltge over J. The fctor ɛ m repreent the mll vlue tht the voltge over J i elow it criticl voltge nd cn e clculted from the following eqution ɛ m = [ q e [ ] Σm ]. (5) Σn cr In order to keep the voltge over J elow it criticl voltge we derived tht the condition > Σm mut e tified. Auming the voltge e i while r = nd the numer of electron preent on the chrge reervoir w equl y, the following reltion w found. [ v y = ] Σm k (6) v w Σn cr The numer of electron removed from the output reervoir k i proportionl to y ut lo depend on lot of other prmeter. For n extenive overview of the eqution decriing the MMke lock the reder i referred to [9]. Uing the me umption for Implementtion A, the following prmeter vlue for k = were derived: p =5F, =5.5F, j =.5F, w =5F, v =F, =7.3F, =.5F, e = F, t = F nd r =5F. The imultion reult for thi implementtion re imilr thoe depicted in Figure 6 nd re therefore omitted. For k = the following prmeter vlue were derived: p =.5F, =5.8F, r e v r e j Y y N P X M J J p w t cr v Threhold gte MMke lock Figure 7. Mke lock Implementtion B. Proceeding of theth Interntionl onference on Appliction-Specific Sytem, Architecture nd Proceor (ASAP 5) 3-686/5 $. 5 IEEE

5 j =.5F, w =5F, v =F, =9.F, =.5F, e = 33F, t = 77F nd r =5F. The imultion reult for thi implementtion re depicted in Figure 8. Implementtion B w imulted for everl more vlue of k nd ll imultion indict tht thi uilding lock function correctly..8 R (m) E (m) (m) Q_cr (q_e) _cr (m) B, on the other hnd, i more enitive to dynmic feedck through the output thn Implementtion A. Thi i minly due to the fct tht the witching in the MMke lock occur t junction, which i directly connected to the output. Therefore the numer of electron in the output chrge reervoir i ound to certin limit, which proved to e pproximtely 3 for the implementtion uing the prmeter vlue we preented in Suection 3.. oncluding, Implementtion B i etter t firt glnce ecue it i fter, mller nd ue le energy. But when the numer of electron in the output reervoir exceed the limit it cn not e ued nd Implementtion A h to e ued inted Time () Figure 8. Simultion reult for k =for the Mke Implementtion B omprion of the Implementtion The previou uection preented two poile implementtion of the Mke lock. Thi ection compre the implementtion y evluting their re, dely nd conumed energy, which re tted in Tle. Building Block Are Dely Energy Implementtion A element.55 n.3 me Implementtion B element.3 n.6 me Tle. Are, dely nd conumed energy of the Mke implementtion.. Exmple: 6-it Rdix-8 Adder The Mke lock cn, mongt other, e utilized for the reliztion of E high rdix dder. In thi ection we utilize the 6-it rdix-8 E dder, depicted in Figure, n exmple to demontrte thi ility. The prmeter of the utilized Mke nd uilding lock re thoe ued in the E dder preented in []. A tted erlier, crry of one electron mut e generted y the Mkelock when the R reervoir contin eight or more electron. Thu the threhold voltge of the Mke lock hould e the voltge correponding with chrge of 7.5 electron on the cpcitnce of the R reervoir. Therefore, the threhold voltge vth w et to.m, which correpond with the threhold voltge ued in Section 3. Step Input A Input B Output S From the tle it pper tht Implementtion A i the et, ut the numer reported in the tle do not include the uffer re, dely nd conumed energy. We did not include them due to the fct tht the implementtion preented in thi pper re friction technology independent while the re, dely nd energy of the OpAmp ed uffer re dependent on the SET technology one my ue to implement it. When ccounting for the dely of the uffer, the dely of Implementtion A mot likely exceed the dely of implementtion B. OpAmp uffer, potentilly implemented uing hyrid FET-SET technology, re expected to conume lrge mount of energy when compred to SET circuit, thu the totl energy conumed y Implementtion A lo exceed tht of Implementtion B. Implementtion Tle. The input nd output vector for the 6-it rdix-8 dder imultion. The reulting 6-it rdix-8 dder w imulted uing Implementtion B uming the circuit prmeter utilized in Suection 3.. The choen et of input dt, tted in Tle, llow to tet the Mke lock for correct functionlity under ome extreme opertion condition. For the firt four input vector the numer of electron in the R reervoir i zero while for the lt three input vector the numer of electron in the R reervoir i the mximum. Thi mximum numer of electron cue mximum dynmic feedck through the output of the Me lock, though Proceeding of theth Interntionl onference on Appliction-Specific Sytem, Architecture nd Proceor (ASAP 5) 3-686/5 $. 5 IEEE

6 Time () Figure 9. Simultion reult for the 6-it rdix- 8 dder. thi hould not ffect it functionlity. For oth et we hve two vector (,3 nd 5,6) to tet the loction of the threhold, which hould e etween even nd eight electron in the R reervoir. The vector nd 7 cue the numer of electron in the R reervoir to e mximum which llow to tet for correct opertion under the mximum input voltge. The imultion reult re depicted in Figure 9. The top lock of two ignl repreent the reet nd the enle, repectively. The econd two lock, ech contining ix ignl, repreent the input vector A nd B, repectively. The ottom lock, contining even ignl repreent the output vector of the dder. For ech vector diplyed in the grph, the top r repreent the let ignificnt it while the ottom r repreent the mot ignificnt it. The imultion indicte tht the high rdix dder function correctly. The dder require 87 circuit element, h dely of.5 n (uming P error = 8 ) nd n energy of me. 5. oncluion in Single Electron Tunneling (SET) Technology. Firt we dicued the high rdix ddition cheme, which utilize conditionl chrge movement (Mke) lock. Second, we propoed two poile Mke lock implementtion, ech of which we decried in detil nd vlidted y men of imultion. Third, one of the propoed Mkeimplementtion w utilized in the deign of 6-it rdix-8 dder. The reulting dder circuit w verified y imultion nd evlution indicted tht it require 87 circuit element, h dely of.5 n, nd conumed energy of me. Reference [] S. Bnerjee, S. Hung, nd S. Od. Opertion of Nnocrytlline-Silicon-Bed Few-Electron Memory Device in the Light of Electron Storge, Ejection nd Lifetime hrcteritic. IEEE Trnction on Nnotechnology, ():88 9, 3. [] S. otofn,. Lgeweg, nd S. ilidi. Addition Relted Arithmetic Opertion vi ontrolled Trnport of hrge. IEEE Trnction of omputer, 5(3):3 56, Mrch 5. [3] K. Ihihi, D. Tuy, M. Suzuki, nd Y. Aoygi. Friction of Single-Electron Inverter in Multiwll ron Nnotue. Applied Phyic Letter, 8(9): , Ferury. []. Lgeweg, S. otofn, nd S. ilidi. A Liner Threhold Gte Implementtion in Single Electron Technology. In IEEE omputer Society Workhop on LSI, pge 93 98, April. [5]. Lgeweg, S. otofn, nd S. ilidi. Sttic uffered et ed logic gte. In nd IEEE onference on Nnotechnology (NANO), pge 9 9, Augut. [6]. Lgeweg, S. otofn, nd S. ilidi. Binry Addition ed on Single Electron Tunneling Device. In th IEEE onference on Nnotechnology (NANO), Augut. [7] K. Likhrev. Single-Electron Device nd Their Appliction. Proceeding of the IEEE, 87():66 63, April 999. [8] K. Likhrev nd A. Korotkov. Ultrdene Hyrid SET/FET Dynmic RAM: Feiility of Bckground hrge Independent Room Temperture Single Electron Digitl ircuit. In Proceeding of the Interntionl Semiconductor Device Reerch Sympoium, pge , hrlotteville, irgini, Octoer 995. [9]. Meenderinck. Single electron tunneling ed rithmetic opertion. Mter thei, Delft Univerity of Technology, 5. []. Whuer. Aout Single-Electron Device nd ircuit. PhD thei, TU ienn, 998. []. Whuer, H. Koin, nd S. Selerherr. SIMON - A Simultor for Single-Electron Tunnel Device nd ircuit. IEEE Trnction on omputer-aided Deign, (9):937 9, Septemer 997. Thi pper invetigted the implementtion of high rdix ddition ed on the Electron ounting logic deign tyle Proceeding of theth Interntionl onference on Appliction-Specific Sytem, Architecture nd Proceor (ASAP 5) 3-686/5 $. 5 IEEE