High Speed Design Issues and Jitter Estimation Techniques. Jai Narayan Tripathi

Transcription

1 High Speed Design Issues and Jitter Estimation Techniques Jai Narayan Tripathi

2 Outline Part 1 High-speed Design Issues Signal Integrity Power Integrity Jitter Power Delivery Network Building the cumulative PDN model for entire system Effects on supply ripple on output Importance of optimal PDN design vs under/over design Impedance and Ripple profiles before and after optimization Part 2- Jitter Estimation Techniques System under consideration Method1: Numerical Method Method2: EMPSIJ Method3: Delay based Modeling

3 Part 1 High-speed Design Issues

4 Signal Integrity and Power Integrity Interconnects behave as transmission lines at high frequencies. Signal Integrity (SI) refers to the quality of signal propagating from one point to another point in a network in terms of distortion, attenuation and noise. Power Integrity (PI) refers to the quality of power in a system in terms of sufficiency, efficiency and stability. Jitter is timing variation of a rising/falling edge from its ideal timing. It is measured at the midpoints of the rising/falling edges. Jitter is one of the most important timing metrics used for characterizing high-speed systems for signal/power integrity. Jitter is affected by both signal and power integrity. Fig: A sample rising edge having jitter

5 Signal/Power delivery Network (PDN) Most of the electronics systems are typically implemented with multi-layer PCB, Packages where operating circuits need constant supply voltages to function properly. SDN consists of bond wires, PCB traces, package nets, on-chip interconnects, etc. Typically PDN consists of: - Voltage Regulator Module (VRM), Traces, Vias, Power-GND planes and decoupling capacitors (decaps) on PCB. - Traces, Vias, Power-GND planes, Bond wires or RDL on Package - Supply GND rails, supply grids/mesh implemented on Die PCB Package Die Supply Grid/Mesh Supply GND rails

6 Package Supply routing System Description DDR3 based system implemented with Noisy supplies wire-bond BGA package, multi-layer PCB with shared power supplies PACKAGE PCB system on chip (SoC) running multiple processor cores thus leading to very high core current consumption. The core supply is also shared by internal clock tree (buffer -chain), which is susceptible to supply noise and thus adds jitter during clock propagation. 32-bit memory interface operating at 1334 Mbps SoC PLL Supply rail + On-die decaps Core Logic Clock tree DDR Contr -oller Clock manager DDR I/O pad ring Clock jitter at memory input DDR3 Memory 32 bits for storage of application data, thus leading to high IO switching current due to SSO. OSC Core supply VRMs Wire bond package contributes to high PDN impedance. PCB Supply routing + decaps IO supply Fig: A DDR3 memory based system

7 System level co-simulation environment Power delivery network modelling On DIE PDN (I/O ring, CPM) Package PDN PCB PDN with decap network VRM Model Core supply (ideal) I/O supply (ideal) Core Chip power model Noisy supplies at clock tree and Clock IO due to PDN impedance I/O Ring modelling to generate worst case SSN. CPM representing core switching. SoC Clock (Ideal) Internal SoC Clock tree Eye diagram and jitter analysis I/O buffer SPICE model DDR Differential Clock (Ideal) 667 MHz Package Signal trace model PCB Signal trace model High speed clock path modelling Termination Memory IBIS Model Fig: SI/PI Co-simulation environment

8 PDN Impedance extraction and optimization S-parameters for PDN interconnects can be extracted using EM solver tools. Z-parameters or impedances for power delivery network model can be computed from S- parameters. Voltage ripple generated at any location in a PDN can be analysed and contribution of self and transfer impedances can be quantified. PDN should be optimized, such that values of self and transfer impedances are within permissible limit which is known as Target impedance. Target impedance can be determined as : Z(target) = V/I Where V is the acceptable voltage ripple and I is the switching current at the location where Z(target) is determined.

9 PDN Impedance Composite PDN model and resonance Due to interaction of inductors and capacitors, PDN exhibits resonance and anti-resonance, where magnitude of impedance peaks at certain frequencies. Anti-resonance peaks can be suppressed by selection of appropriate decaps based on resonant frequencies. Resistive Inductive Capacitive VRM Model PCB Model with decaps VRM PCB with Decaps Package Die Anti-resonance peaks Frequency Package Model with Decaps On die Model IO supply PDN Core supply PDN Impedance seen from die side is PDN impedance

10 Eye Diagrams Ideal PDN Eye diagrams are used to visualize and measure amplitude noise and timing noise (jitter), over a large number of bits by superimposing them in one time interval. There are various measurements can be performed by creating eye-diagrams e.g. eye-height, SNR, jitter etc.

11 Effects of Power Supply ripples Effect of Power supply ripple are directly transferred to the output of driver circuit. Amplitude distortion and jitter are two adverse effects. Clock Buffer Jitter effects are worse as it impacts the setup hold margins and thereby cause system failure.

12 Importance of optimal PDN design PDN plays important role is ensuring stable and ripple-free power supply to the operating circuits. Both Self impedance and Transfer impedance should be analysed to mitigate self generated ripple and transferred ripple from other aggressor. Thus PDN optimization is an essential task during system design. Under-designed PDN may lead to excessive supply ripple at certain frequencies where PDN impedance is very high due to anti-resonance. Over designing the PDN may require more decoupling capacitors, more PWR-GND plane layers, more area on-die and thus lead to higher cost of system.

13 IO Supply: Impedance profiles with original and optimized PDN Impedance reduction could be achieved at 30MHz and at around 200 MHz by Package decap optimization. Addition of on-die decap indicates improvement in anti-resonance peak at higher frequency. 2 rows of on-die caps are added to reduce the antiresonance peak. Peak impedance is reduced from 3.5 ohm to 1 ohm.

14 Core supply: Impedance profiles with original and optimized PDN VDD PDN Impedance PDN impedance peak reduced from 690mohms to 100mohms. Supply ripple peak reduced from 41mV to 26mV.

15 IO Supply: Ripple profiles in different implementations

16 Differential Clock jitter with original and optimized PDN implementation PCB, PKG default PDN Optimized PKG decaps Additional on-die decaps Eye Jitter (PP) = e-10 Eye Jitter (PP) = e-11 Eye Jitter (PP) = e-11

17 Part II Jitter Estimation Techniques

18 Jitter Estimation Techniques Numerical Method Slope Based Modeling (EMPSIJ) Delay based Modeling

19 Basic Idea Finding large-signal and small-signal analysis separately. Approximating the system response as a linear sum of both the responses. D Fig : (a) System response without PDN and (b) System response with PDN

20 Numerical Method: Circuit Overview A voltage-mode low-voltage signaling driver circuit is analyzed for Power Supply Induced Jitter (PSIJ). Used in high-speed data links e.g. serial links for differential signaling. Differential signaling reduces common-mode noise. Fig : Voltage-Mode Driver* *J. N. Tripathi et al., An Analysis of Power Supply Induced Jitter for a Voltage Mode Driver in High Speed Serial Links, Proc. 20th IEEE Workshop on Signal and Power Integrity (SPI), pp , May 2016, Torino, Italy,

21 Voltage-Mode Driver Fig : Impact of noise on output in Voltage-Mode Driver

22 Voltage-Mode Driver Fig : Voltage supply with PDN noise and Vsup node Voltage is fairly stable at node Vsup, so it can be used as a voltage source for equivalent large-signal model.

23 Numerical Method An equivalent model can be used for large-signal analysis. Fig : Large-signal equivalent model

24 Numerical Method Fig : Path of noise from PDN to DP/DN

25 Numerical Method An equivalent model can be used for small-signal analysis. Fig : Small-signal equivalent model

26 Numerical Method The complete system response can be written as: This can be used to find time interval error using root-finding approach. Fig : Small-signal equivalent model

27 Numerical Method A function can be defined as: This can be used to find time interval error using root-finding approach. TIE for the k th bit can be found as:

28 Numerical Method: Results Fig: PSIJ estimation for noise as sin wave (850 MHz)* Fig: PSIJ estimation for noise as triangular wave (time period: 1.53 nsec)* *J. N. Tripathi, F. G. Canavero, An Efficient Estimation of Power Supply Induced Jitter by Numerical Method, IEEE Microwave and Wireless Components Letters (MWCL), pp. 1-3, 2017 (in press).

29 Slope based Method Instead of using Numerical methods, a nonlinear approximation can be used to speed-up the estimation time (having all other assumptions intact). For the case of VM driver used in earlier case study, the same is demonstrated. Instead if using the large-signal response as a sum of exponentials, it can be approximated as nonlinear functions of time, in different time interval. To estimate jitter the point of interest is midpoint, thus the nonlinear function of that time interval can be used as instead of the complete large-signal model.

30 Slope based Method Fig: Piecewise nonlinear modeling of the output differential voltage for the case when noise = 0

31 Slope based Method

32 Slope based Method Time intervals can be divided into even smaller time intervals. In the limiting case, the time interval having the midpoint, can be modeled as with three points, as a straight line.

33 Slope based Method Thus jitter can be modeled as a ratio of noise output to the slope of output (without noise). If there are multiple frequencies in PDN noise, the output noise can be modeled using Fourier series coefficients of the. Instantaneous Jitter (TIE) for the k th bit can be calculated as*: *J. N. Tripathi et al., An Efficient Modeling of Power Supply Induced Jitter (EMPSIJ), IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), pp. 1-11, July 2017 (early access).

34 Slope based Method: Results Fig: Comparison of PSIJ for a sinusoidal input in 55nm technology Approach-1 is nonlinear modeling and Approach-2 is slope based modeling. Conventional approach is estimation by simulations in EDA tools.

35 Slope based Method: Results Fig: Comparison of PSIJ using both the Proposed and Conventional methods for saw-tooth noise input in 28-nm FD-SOI technology

36 Slope based Method: Results PDN noise contains 8 dominant frequency components. Speed-up is >400 with accuracy being more than 95%. Fig: A practical PDN noise and its impact on the output

37 Delay based Method: Circuit Description A current-mode low-voltage signaling driver circuit is analyzed for Power Supply Induced Jitter (PSIJ). Used in high-speed data links e.g. serial links for differential signaling. Differential signaling reduces common-mode noise. Fig : Current-Mode Driver* *J. N. Tripathi et al., Analysis of a Serial Link for Power Supply Induced Jitter, 27 th IEEE System-On-Chip Conference, pp , Beijing, Sept

38 Delay based Method Fig : Illustration of the current (I s (t)) delivered by the transistor M s (dashed line) and the differential output voltage (v R (t), solid line) across terminals DP and DN Fig : Large-signal equivalent for Current-Mode Driver

39 Delay based Method: Circuit Description Large-signal output response can be modeled by following set of equations:

40 Delay based Method Based on midpoint delays, s single-ended outputs can be modeled as per their effective time constants. ; ; Fig : Input signals v IN1 and v IN2 at gates of M 2 and M 3 respectively, their corresponding output voltages at v X (t) and v Y (t) with delays shown by the markers.

41 Delay based Method Based on the equivalent model, time interval error can be formulated. For differential signal, v Rn (t) = 0 at t m Fig : Comparison of v R (t) obtained using the approximate Model and Simulation by EDA tool

42 Delay based Method Differential small-signal output can be modeled as: where Fig : Small-signal equivalent circuit for CM driver

43 Delay based Method: Results (Ex. 1) Fig: Comparison of PSIJ using both the Proposed Approach and the Conventional methods for pulse train noise input in 55nm technology

44 Delay based Method: Results (Ex. 2) Fig: Construction of a Pulse Train waveform from 20 frequencies Fig: PDN noise (represented by pulse train wave) superimposed on supply voltage (V DD + v n (t); right-y axis, dotted line) and the corresponding differential output (v Rn (t); left-y axis, solid line)

45 Delay based Method: Results (Ex. 3) Fig: Comparison of PSIJ using both the Proposed Approach and the Conventional methods for pulse train noise input in 55nm technology

46 Delay based Method: Results (Ex. 3) Fig: Comparison of PSIJ using both the Proposed and Conventional methods for saw-tooth noise input in 28- nm FD-SOI technology* *J. N. Tripathi et al., Fast Estimation of Time Interval Error in Current-Mode Drivers, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), pp. 1-11, 2017 (in press).

47 Summary/Conclusions Signal/Power Integrity issues are very critical in high-speed Soc designs. Jitter estimation techniques with good accuracy are required to reduce the design time of SoCs. Some of the recently proposed/developed estimation techniques were discussed. The proposed techniques can significantly reduce the estimation time and speed-up the complete design cycle of SoCs.

48 Summary System level PDN modelling carried out with PCB, Package and on-die (CPM, lumped) models. Optimization areas are identified based on resonance profile of PDN. Decap network optimized with appropriate parts based on their resonant frequencies. Significant improvement achieved in Clock tree and Clock IO jitter with optimized PDN.

49 Acknowledgements/Collaborations Prof. Ramachandra Achar, Carleton University, Ottawa, Canada. Prof. Hitesh Shrimali and Vijender Kumar Sharma, Indian Institute of Technology Mandi, H.P., INDIA. Prof. Flavio G. Canavero, Politecnico Di Torino, Turin, Italy. Pratik Damle, Texas Instruments, INDIA. Hiten Advani and Rajkumar Nagpal, Synopsys Inc., INDIA.

50 Thank You.