The Role of Voltage Regulation in Power Integrity for Multi-Gbps Parallel I/O Interfaces. Yue Yin

Transcription

1 The Role of Voltage Regulation in Power Integrity for Multi-Gbps Parallel I/O Interfaces by Yue Yin A thesis submitted in conformity with the requirements for the degree of Master of Applied Science, The Edward S. Rogers Sr. Department of Electrical & Computer Engineering University of Toronto Copyright c 2017 by Yue Yin

2 Abstract The Role of Voltage Regulation in Power Integrity for Multi-Gbps Parallel I/O Interfaces Yue Yin Master of Applied Science, The Edward S. Rogers Sr. Department of Electrical & Computer Engineering University of Toronto 2017 Strategies for power supply distribution in high speed I/O interfaces including the design of low dropout regulators (LDOs) and allocation of decoupling capacitance are proposed to minimize power supply induced jitter (PSIJ) in load circuits (aggressors and victim circuits) sharing the same supply. Different LDOs should be used for the aggressor and victim circuits and it is preferable to allocate available decoupling capacitance to the aggressor circuit. A prototype is developed in 28nm CMOS with the aggressors - 4 transmitters (aggressors) and the victim circuit - 1 injection locked oscillator (ILO) sharing a common supply but operating under separate LDOs. LDO1 employs a conventional topology with a bandwidth of 10MHz for the transmitters and LDO2 employs tri-loop topology with a worst-case PSR of-15db at 400MHz for the ILO. The resulting simulated transmitter jitter is 3.5ps-pp at 20Gbps and the ILO jitter is 710fs-pp at 10GHz. ii

3 Acknowledgements I would like to express my gratitude towards my supervisor Professor Tony Chan Carusone for his guidance and support during my graduate study. It has been a truly rare pleasure to work with an advisor who not only provided me with academic guidance, but also insightful discussions on all aspects of life. I wish to thank the members of my evaluation committee: Prof. Antonio Liscidini, Prof. Trevor Caldwell and Prof. Paul Chow for taking their time to help evaluate my thesis. For all the joy and laughter that makes BA5000 the best office, I d like to extend my thanks to all my current and previous officemates. A special thanks goes to Behzad Dehlaghi and Jeffrey Wang, who have supported me a lot and gave me many helpful advices and suggestions on research. Finally, I am, as always, grateful to my husband, my parents and all of my friends for their unwavering support. iii

4 Contents 1 Introduction Motivation Objective Thesis Organization Background Introduction to Power Integrity Analysis for Parallel I/O Interfaces Power Supply Induced Jitter Methodology of PSIJ Simulation and Measurement Techniques of Improving PSIJ Supply Partitioning Load Current Shaping PDN Optimization Voltage Regulation involving LDOs System Overview Load circuits Transmitters ILO System Design Consideration Use of LDOs iv

5 3.3 Parallel Aggressors (TXs) System Level Design Package Model Decoupling Capacitor Allocation Circuit Implementation System Overview Transmitters ILO LDO for Aggressors (Transmitters) Background on Conventional LDOs LDO Design for Aggressor Circuits LDO Design: for Victim Circuits Background of High PSR LDOs LDO Design Operation of LDOs Supply Noise Injection Measurement Methodology and Results Supply Noise Measurement On-Board Probing Measurement Using On-chip Buffer Testing Setup Results Conclusion Summary v

6 List of Tables 2.1 Table of decoupling capacitor allocation for 3 separate supply domains in [1] Values of package inductance and decaps used in this work with corresponding package model shown in Fig Decap values based on decap sweep simulation study Circuits and decoupling caps under each supply domain on chip Transistor sizes of folded cascode amplifier in LDO Transistor sizes of folded cascode amplifier biasing circuit in LDO Settings for LDO2 s PSR simulation Transistor sizes of the pass devices in LDO Transistor sizes of the single stage amplifier in Fig (a) Current range of VCR Transistor sizes of the single stage amplifier used in supply monitor buffer, schematics shown in Fig (b) vi

7 List of Figures 2.1 Circuit model of a load circuit with PSIJ output and its supply connected to ideal supply with package model Impedance of the power distribution network identifying the frequency ranges where the packaging inductance and decaps on the die, package and board predominate [2] Methodology of predicting PSIJ [2] Circuit of ground-referenced signaling transmitter [3] Typical test bench for PDN impedance modeling Time and frequency domain illustration of the supply current of a single transmitter lane operating at 20Gbps Time and frequency domain illustration of current profile of the ILO operating at 10GHz Jitter sensitivity profile of one slice of TX and the ILO Simplified schematics for studying power integrity of the system showing two load circuits with separate LDOs Simplified schematics for studying power integrity of the system showing two load circuits with no LDOs Parallel aggressors (TXs) with correlated or uncorrelated data sequences; 1 dedicated LDO for each transmitter Current spectrum of 4 parallel TXs with correlated data sequences vii

8 3.8 Current Spectrum of 4 parallel TXs with uncorrelated data sequences Parallel aggressors (TXs) with 1 LDO sharing for all transmitters Ratio of V DD1 rms of correlated case to uncorrelated scenarios versus the delay between neighbouring transmitter PRBS7 data patterns at 20Gbps. The noise V DD1 rms is normalized to case with zero delay, which corresponds to identical synchronized data patterns on all 4 lanes Illustration of data sequences in the 4 transmitters with time delay Package impedance spectrum with 180pF on-chip decoupling capacitors Conceptual graph of Z VDD1 as C D1 varies; LDO1 bandwidth changes with C D Conceptual graphofpsr 2 asc D2 varies; LDO2bandwidthremainsconstant Peak-peak V DD1 noise as C DH is swept, assuming the sum of C DH and C D1 is held constant at 35pF/lane and C D2 equals 10pF/lane Peak-peak V DD2 noise as C DH is swept, assuming the sum of C DH and C D2 is held constant at 15pF/lane and C D1 equals 30pF/lane Supply voltage noise of V DDH when LDOs are on/off Supply voltage noise of (a) V DD1 and (b)v DD2 when LDOs are on/off Eye diagrams of transmitter output with correlated data sequences at 20Gbps when LDOs are (a)off, and (b)on Eye diagrams of ILO output operating at 10GHz when LDOs are (a)off, and (b)on PSIJ of the TX and ILO circuits are simulated as the decoupling capacitance C D2 is swept, assuming the sum of C D2 and C D1 is held constant at 40pF/lane, when LDOs are on Top level diagram of the system implemented on chip Schematics of TXs withreal output tooff chip for TX1 anddummy output for TX viii

9 4.3 Schematics of ILO Block diagram of ILO and its clock driver for off-chip Schematics of 2 conventional LDOs with (a)pmos and (b)nmos pass devices respectively Conventional LDO with 2 poles: f O is the pole at LDO output; f G is the pole at amplifier output The small signal schematic of a basic voltage regulator Schematics of LDO Loop gain of LDO showing shifted second pole with light and heavy load Schematics of folded cascode amplifier in LDO Schematics of folded cascode amplifier biasing circuit in LDO Bode plot of LDO1 loop gain Illustration of 4 paths that supply noise feeds to the LDO output Schematics of replica biased LDO [4] Schematics of LDO PSR of LDO Simplified schematics of LDO2 with the loop broken at V REP node Illustration of the loop gain of 3 individual paths in LDO Bode plot of loop gain in LDO a) Type A b) Type B single stage amplifier [5] Schematics of OP2: folded cascode amplifier in LDO Schematics of the VCR - voltage controlled resistor Schematics of LDO1 and LDO2 with power down connections Cross sectional view of the stacking of the chip, package substrate and PCB board Schematics and modeling of the supply monitor path AC response of the supply monitor path ix

10 5.4 Die photo a) DC PCB used for supply and biasing and b) high speed PCB with the chip and SMA connectors PSIJ versus decap sweep as in Fig along with top-level simulation results of the PSIJ of the TX and ILO with back annotated parasitics in schematics view (a) Transmitter eye diagram operating at 20Gbps with correlated data sequences and (b) ILO eye diagram operating at 10GHz Transmitter eye diagram operating at 20Gbps with uncorrelated data sequences PDN design and performance comparison with other published works.. 72 x

11 Acronyms ILO Injected Locked Oscillator LDO Low Dropout Regulator PDN Power Distributed Network PKG Package PSIJ Power Supply Induced Jitter PSR Power Supply Rejection TX Transmitter xi

12 Chapter 1 Introduction The extent to which an integrated system delivers reliable power supplies to its constituent circuits is referred to as power integrity. In the context of high-speed I/O, we are particularly interested in the extent to which fluctuations on the power supply impact signal integrity, quantified here in terms of timing uncertainty (jitter). Typically, in an integrated system, the power distribution network needs to be designed and characterized as part of the power integrity analysis. The power distribution network (PDN) in such a system refers to all the interconnect, decoupling capacitances (and even active circuits) that impact the source impedances via which power is delivered to circuits. In this chapter, challenges in power integrity for multi-gbps I/O interfaces and the need for an optimized PDN are first described. After that, three objectives of this thesis are mentioned and the thesis organization is explained. 1.1 Motivation There is a growing demand for higher bandwidth memory interfaces and other highlyparallel interfaces between integrated circuits due to the need for massive data transfer in graphics, computing and networking systems. Multi-terabits/s throughput are sought for next generation I/O interfaces. For instance, the hybrid memory cube (HMC) spec- 1

13 Chapter 1. Introduction 2 ification [6] calls for an aggregate bandwidth of 8 Tb/s in next generation memory-toprocessor links. To meet next generation bandwidth requirements, more pins are desirable. However, the bandwidth demands continue to increase while package pins are limited [7]. Alternatively, the data rate per pin can be increased further. Recent trends indicate that this would lead to lower energy efficiency due to need for more equalization [8]. Ultimately, it is desired to reduce the energy/bit of interfaces to allow for increasing bandwidth with a fixed power budget. Based on these considerations, in order to maximize throughput, single-ended signaling is desirable so that, for any given number of signaling pins, the overall throughput is doubled compared with differential signaling. Meanwhile, it is common to provide separate Vdd and GND pads for each I/O macro, which costs tremendous overhead in pins and die area. This may not be necessary for very low-power interfaces where the current drawn per lane is significantly less than the current capacity of each power supply solder bump/pad. Therefore, sharing power supplies on-die among different circuits and/or across multiple lanes of a parallel interface can reduce the number of pins required for power supplies, leaving more pins for signals. It may also simplify package and system design if fewer isolated power supplies are needed for the entire chip. However, these solutions introduce power integrity challenges. Single-ended signalling introduces more significant supply voltage noise due to large transients in the supply current compared to differential signaling. By sharing a supply amongst multiple circuits, supply noise crosstalk between lanes occurs which potentially degrades I/O performance. This thesis targets the power integrity challenges in a single-ended parallel link where multiple circuits share the same supply. Supply noise crosstalk is modeled, monitored and mitigated by the use of proper regulators and allocation of decoupling capacitors.

14 Chapter 1. Introduction Objective The main objectives of this thesis are as follows: 1. Summarize existing power integrity analysis methods for multi-gbps parallel interfaces 2. Propose and demonstrate methodologies for the design of power delivery networks (PDN) that makes efficient use of linear voltage regulators and decoupling capacitors taking into account the supply current spectra and jitter sensitivities of each load circuit to permit single-ended signalling I/O circuits to share one supply voltage. 3. Demonstrate a prototype PDN suitable for parallel high-speed single-ended transceivers with simulations to validate the design. 1.3 Thesis Organization This thesis is organized as follows: Chapter 2. Background: Background Information on existing power integrity analysis methods for multi-gbps I/O systems are presented. Considerations in PDN design for single-ended parallel links are discussed in details. Chapter 3. System Overview: Load circuits used in the prototype are presented. Proposed strategies on voltage regulation and decoupling capacitance allocation are explained. Chapter 4. Circuit Implementation: Circuit implementations of the LDOs and other circuits included in the prototype are presented. Chapter 5. Testing and Results: Prototype and Printed Circuit Board (PCB) photos are presented. Supply noise measurement and probing methodologies are presented. Simulation results of the prototype are provided.

15 Chapter 1. Introduction 4 Chapter 6. Conclusion: This thesis is summarized and future work is discussed.

16 Chapter 2 Background 2.1 Introduction to Power Integrity Analysis for Parallel I/O Interfaces In high speed I/O interfaces, timing uncertainty, called jitter, is a key metric to identify the timing performance and signal integrity of the interfaces. Variations on the power supply introduce jitter by coupling into signal and clock waveforms, and may modulate the delay through signal-path circuits. The resulting power supply noise induced jitter (PSIJ) is a major source of the jitter that has a significant (sometimes dominant) impact on link timing margin in high speed I/O interfaces [9]. To study the impact of PSIJ, a rigorous and standardized methodology is desirable. In this chapter, definitions of parameters related to power integrity and previously reported methodologies for predicting PSIJ are covered. Then various ways of improving PSIJ are presented and discussed Power Supply Induced Jitter First, a few key parameters in the study of power integrity are introduced. Following the approach in [10], consider a load circuit as shown in Fig. 2.1 where its power supply 5

17 Chapter 2. Background 6 voltage includes some additive AC noise, denoted V n (f) and its AC switching current is denoted I n (f). Additionally, in the circuit model, I n (f) denotes the PDN impedance. PKG models the PCB/package inductances and decoupling capacitances, as shown in Fig. 2.5 and C D represents the decoupling capacitors placed on-chip at the supply node. The spectrum of power supply induced jitter (PSIJ) introduced by a circuit as a function of frequency is defined as a product of the supply voltage noise spectrum V n (f) and the jitter sensitivity of the circuit (J S (f)) as shown in equation (2.1). More detailed explanations of J S (f) and V n (f) respectively are provided in each of the following two paragraphs. Figure 2.1: Circuit model of a load circuit with PSIJ output and its supply connected to ideal supply with package model. PSIJ(f) = V n (f) J S (f) (2.1) Jitter Sensitivity The jitter sensitivity of a circuit relates the power spectral density of its power supply noise to the resulting output jitter spectrum, as in equation (2.2) [10]. Specifically, a tone at frequency f with amplitude N(f) added to the load circuit s supply while it is in operation will result in a time-varying phase at the output of the load circuit (be it

18 Chapter 2. Background 7 a clock or data pattern) that has a component at the frequency f with amplitude J(f). The jitter sensitivity of the load circuit is the ratio (2.2) expressed in ps/mv and is a function of the supply noise frequency. It depends on the circuit s architecture. J S (f) = J(f) N(f) (2.2) In [11], the jitter sensitivity profile of a typical PLL, clocking buffers and transmitter drivers are found illustrating the frequency range over which each load circuit has high jitter sensitivity. It also shows how sensitive the circuits are compared to each other. Specifically, the PLL in [11] is highly sensitive, showing a bandpass profile with peak sensitivity of 0.47ps/mV around 5MHz, while the output driver is not, showing a low pass profile with only 0.07ps/mV at 1MHz and even lower at higher frequency [11]. The jitter sensitivity of a circuit is one of the key parameters in power integrity studies as it has important impact on PDN design and PSIJ improvement strategies. Supply Voltage Noise The supply voltage noise spectrum is product of the load current spectrum and PDN impedance: V n (f) = I n (f) Z PDN (f) (2.3) The entire PDN impedance, Z PDN (f), depends on a combination of inductance from PCB and package substrate, parasitic resistance as well as decoupling caps on the board, package, and chip. Since the decoupling capacitors ( decaps ) on the PCB and package substrate are usually much larger than those on-chip ones, in the impedance profile they typically dominate at low frequencies. The resonance peak depicted in Fig. 2.2 is determined primarily by resonances between on-chip decaps and packaging inductances. The current profile of a load circuit, I n (f), depends on the architecture of the circuit itself. For example, an oscillator operating at 10GHzwill have I n (f) concentrated mainly

19 Chapter 2. Background 8 Figure 2.2: Impedance of the power distribution network identifying the frequency ranges where the packaging inductance and decaps on the die, package and board predominate[2] at 10GHz and higher. Clearly, large currents do not necessarily introduce large supply voltage noise. Supply voltage noise is worst in the frequency range where both the magnitudes of I n (f) and Z PDN (f) are large. Therefore, knowing the spectra of both the PDN impedance and current profile of a load circuit are equally important. PSIJ Prediction Fig. 2.3 summarizes how PSIJ is simulated from knowledge of the PDN and load circuits design [2]. The supply noise spectrum, V n (f), is obtained by multiplying the PDN impedance, Z PDN (f), and the current spectrum of the load circuit, I n (f). The jitter sensitivity spectrum, J S (f), depends on circuit implementation and may be observed from simulations. Knowing both the supply noise spectrum of the targeted circuit and its jitter sensitivity profile, one can estimate the PSIJ by multiplying these two parameters.

20 Chapter 2. Background 9 Figure 2.3: Methodology of predicting PSIJ [2] Methodology of PSIJ Simulation and Measurement PSIJ performance can be simulated either in frequency domain [9] or time domain [1]. Frequency domain analysis gives insights that can inform the design of the PDN, including the decaps and possibly voltage regulators. On the other hand, time domain simulations are usually more straight-forward to perform, and the supply noise peak to peak ripple amplitude is often specified as an indication of the supply integrity of an interface [1]. In addition, PSIJ can be shown in time domain by periodically overlaying many transient clock or data waveforms, similar to the eye diagrams that are familiar to high speed I/O designers. Frequency Domain Measurement A frequency domain approach to predict and measure PSIJ for high speed I/O interfaces is presented in[9]. Supply voltage noise spectra are simulated and measured. In addition, two methods for simulating the jitter sensitivity are presented. The conventional way is by transient simulation where noise at each frequency is introduced to the supply voltage and the resulting jitter at each corresponding frequency is obtained. Another method is to use period-steady-state (PSS) and periodic AC (PAC) simulation, where

21 Chapter 2. Background 10 PSS computes periodic steady-state response of a circuit and PAC linearizes the circuit over its PSS response. The resulting PSIJ is the product of the jitter sensitivity profile and the supply voltage noise spectrum, as in (2.1). The accumulated jitter percentage up to frequency f can be expressed as a percentage of the total jitter, as shown in equation 2.4. η(f) = f 0 J(f )df 100% (2.4) J(f 0 )df Time Domain Measurement Transient simulations and time domain measurements are better to capture transient behaviours such as voltage undershoots at the beginning of logic circuit activity [12]. Power integrity analysis of a 4.8Gbps-per-link single-ended I/O interface is presented in [1]. It combines time-domain and frequency-domain approaches to show the impact of PSIJ. For example, in a parallel I/O system, single or multiple lanes can be turned on/off and eye diagrams are inspected to identify the output jitter. The eye diagrams in [1] show the effect of simultaneous switching outputs (SSO). Specifically, more jitter is observed when all lanes turn on with the same data sequence than when only one lane is active. In this perspective, an eye diagram is an informative metric to inspect the PSIJ impact. If PSIJ is the major source of noise, the RMS jitter in the time domain is simply the integration of PSIJ in frequency domain. In addition, peak to peak voltage noise is another metric to compare the impact of a load circuit on power integrity in different scenarios. For instance, with a pseudo random bit sequence (PRBS) feeding all transmitter pins at 4.8Gbps, a peak to peak supply noise of 15mV is reported in [1]. When the PRBS input pattern is replaced with a clock pattern at the PDN resonance frequency(60mhz), 40mV peak to peak supply noise is reported.

22 Chapter 2. Background Techniques of Improving PSIJ Based on this understanding of the parameters that impact PSIJ, various techniques are used to improve PSIJ in multi-gbps I/O interfaces. The following sections illustrate 4 types of techniques: proper supply partitioning, load current filtering, PDN optimization, and linear voltage regulation Supply Partitioning The load circuits described in [2] include a PLL, clock buffer and voltage mode output drivers. Separate isolated supply voltages are used for the PLL and clocking buffers due to their high jitter sensitivity. The output driver operates under its own supply voltage because its data-dependent current spectrum overlaps typical resonances in the PDN impedance and causes significant supply noise. The drawback, however, is that separate supply domains may require additional I/O pads, thereby potentially increasing die size and complicating package design. Typically, metal layer in the package substrate is allocated to supply voltages, and must therefore be shared when there are multiple supplies. As a result, package impedance would increase due to smaller power traces in the package for each supply voltage. In addition, as mentioned previously, the additional supply voltage pins may limit the overall per-unitdie-area I/O interface bandwidth Load Current Shaping Based on equations (2.1), filtering or shaping the supply current spectra can result in PSIJ improvement. A single-ended transceiver with a ground-referenced signalling (GRS) transmitter is presented in [3]. The supply current spectrum of the transmitter is concentrated at higher frequencies where the PDN impedance, Z PDN (f), is smaller so that supply voltage noise is reduced. Fig. 2.4 shows the circuit of the ground-referenced

23 Chapter 2. Background 12 signalling transmitter, where the top and bottom are two charge pumps that operate alternately to make a 2:1 multiplexer. Every half clock cycle, the capacitors C0 (or C1) Figure 2.4: Circuit of ground-referenced signaling transmitter [3] gets fully charged. On the next half clock cycle, the capacitor gets discharged by connection to the 50-ohm channel with a polarity based on the data input data. In this way, the transmitter current is concentrated at the bit-rate (20GHz in this case) where it is easily filtered by on-chip supply decoupling capacitors. By contrast, for a typical transmitter with random data, the supply current spectrum is broadband, spread from dc up to the bit rate which includes the content around PDN impedance resonant frequency. A drawback of GRS is that the need for negative voltages (below ground) are generated, which complicates circuit design.

24 Chapter 2. Background PDN Optimization Packaging Design Packaging design plays an important role as the package inductance along with on-chip decoupling capacitors determine the PDN resonance frequency, as shown in Fig A typical model of the PDN is shown in Fig Different methods of packaging result in different packaging inductance. The structure of the packaging substrate can make a difference as well. For example, some packages place decoupling capacitors within the packaging layers and some do not. Common packaging methods include wire-bond and BGA (flip-chip). In wire-bond packaging, the package inductance comes mainly from the wires and the typical packaging inductance is around 1nH. In flip-chip design, BGAs, substrate traces and vias dominate the package inductance, which has a typical value of 0.1nH, much smaller than wirebond packaging [13]. Figure 2.5: Typical test bench for PDN impedance modeling On Chip Decoupling Caps Allocation With multiple supply domains in a system, the way on-chip decaps are allocated causes impact on the PDN impedances in each supply domain which in turn impacts the output

25 Chapter 2. Background 14 PSIJ. The allocation of a fixed total decoupling capacitances between 3 separate supplies is presented in [1], as shown in Table 2.1. More than 50% of decaps are assigned to the supply for the output drivers. Since the output driver supply current has broad spectrum, it would excite the PDN impedance resonance, so more decoupling capacitance is allocated to it to lower the resonance peak in its PDN impedance. Although adding on-chip decoupling reduces PDN impedance and thereby improves supply integrity, the area available for decoupling capacitors is limited by its cost consideration. Table 2.1: Table of decoupling capacitor allocation for 3 separate supply domains in [1] Voltage Regulation involving LDOs On-chip low dropout voltage regulators (LDO) are commonly used to reduce the supply voltage noise. An LDO with high power supply rejection ratio (PSRR) helps attenuate the existing voltage noise hence reduces the PSIJ of circuits operating under it. The trade off is the additional power consumed in the LDOs on top of the load circuits. A 64-lane parallel I/O with variable data rate using an optional LDO for its TX and RX bundles is presented in [14]. The LDO is turned on to suppress supply voltage noise and turned off to save power. Since this work presents a differential parallel I/O interface, power integrity challenges are more relaxed compared to the single-ended interface. And yet it shows the important roles LDO can play to reduce PSIJ in high speed parallel I/Os. The analysis of PSIJ on a low-power memory interface is presented in [15] where one supply is shared between clocking circuits (PLL and clocking buffers), and the output

26 Chapter 2. Background 15 transmit driver. An LDO is used for the driver to provide extra power supply rejection as well as generating a low voltage for the low-swing transmitter. Since the clock signal retimes data in the output driver, the final transmitter PSIJ is the combination of the jitter from clocking circuits and the driver itself. Again, the output driver is differential in [15], so the current profile is significantly less noisy than in a single-ended driver.

27 Chapter 3 System Overview This chapter presents system-level considerations in the design of PDNs to ensure supply integrity and low PSIJ in dense parallel I/O interfaces. To maximize the interface s bandwidth density(throughput per pin), single-ended signaling is assumed and all circuits are presumed to draw supply current from shared supply voltage package traces and pins. Moreover, standard NRZ transceivers are presumed to ensure interoperability with other standard transceivers. (e.g. GRS, which has a relatively benign supply current spectrum [3], is ruled out) The primary considerations explored are: A) The design of appropriate LDOs to isolate load circuits while operating from a common supply voltage. B) The efficient allocation of finite decoupling capacitance to reduce its area overhead. This chapter illustrates how both (A) and (B) are improved if the load current spectrum and jitter sensitivity of each load circuit are taken into account. First, typical load circuits that arise in parallel I/O transceivers are characterized. Then, based upon their supply current spectra and jitter sensitivities, appropriate methods for the design of LDOs and allocation of decoupling capacitance are presented. 16

28 Chapter 3. System Overview Load circuits In single-ended interfaces, the single-ended transmitters are a dominant source of supply noise due to their large broadband supply current spectrum. It has also been shown in [2] that clocking circuits tend to be the most sensitive to jitter in parallel transmitter signal paths. Hence, two exemplar circuits are considered to capture the challenges of operating these two types of circuits under a shared supply voltage: I) Parallel single-ended voltage-mode output drivers II) An injection-locked oscillator (ILO), which is commonly used in parallel I/O interfaces for clock division/multiplicaiton, generation of multiple clock phases, and phase shifts. Both load circuits are characterized in the ST28nm FD SOI process with supply voltage of 1V Transmitters Single-ended voltage mode transmitters are widely used in memory interfaces. Voltage mode transmitters are preferred over current mode drivers due to their better power efficiency. Four lanes are included in the prototype of this work to capture the challenges presented by parallel links such as crosstalk and SSO events. The transmitter circuits considered are described in [16]. Four parallel transmitters constitute one load circuit. Each transmitter consists of a 4-1 multiplexer, a pre-driver and an output driver [16]. Detailed implementation of the transmitter and its clock distribution are presented in Chapter 4. Current Profile The general pattern of the supply current drawn by a transmitter for a PRBS7 input pattern is plotted in Fig At 20Gb/s data rate, 1 UI is 50ps with the pattern

29 Chapter 3. System Overview 18 Figure 3.1: Time and frequency domain illustration of the supply current of a single transmitter lane operating at 20Gbps repeating every 6.4ns. Hence, the current spectrum peaks occur at MHz and its multiples, which aligns with typical PDN impedance resonances. As a result, the transmitters act as aggressors in the system. The average current of 1 transmitter is 4.5mA. The worst case is all 4 transmitters having identical and aligned current waveforms. The supply noise induced by the transmitters introduces PSIJ in other circuits sharing the same supply. Jitter Sensitivity To simulate jitter sensitivity, a tone with amplitude N(f j ) at frequency f j is added to the load circuits supply voltage and the resulting output jitter amplitude, J(f j ), observed. The jitter sensitivity is then a function of the jitter frequency, J s (f) = J(f)/N(f). For example, Fig. 3.3 shows the simulated jitter sensitivity of one slice of the voltage-mode transmitter exhibiting a low pass trend with the jitter sensitivity of 0.04ps/mV up to 4GHz ILO An ILO with targeted oscillation frequency of 10GHz is used as the other load circuit. This circuit is chosen because it is commonly used for multiphase clock generation, phase shifting, and frequency multiplication in memory interfaces [17]. The average current of

30 Chapter 3. System Overview 19 this ILO is 32mA. In Chapter 4, the schematics and detailed implementation of this ILO are shown. Current Profile Fig. 3.2 presents a conceptual illustration of the time and frequency domain current profile of the ILO. According to spectrum, the current concentrates at 10GHz and its multiples. At such high frequencies, the PDN impedance is small due to on-chip decoupling capacitors. Therefore, the ILO supply current induces negligible supply noise, especially compared to the supply noise introduced by the transmitters data-dependent current. Figure 3.2: Time and frequency domain illustration of current profile of the ILO operating at 10GHz Jitter Sensitivity Jitter sensitivity of the ILO is simulated and shown in Fig Comparing the jitter sensitivity of the two load circuits, the ILO is roughly 5 times more sensitive than the transmitters. Specifically, the ILO shows a sensitivity of ps/mv from low frequencies, up to 200MHz, and a maximum sensitivity of ps/mv at 800MHz. The ILO shows higher jitter sensitivity due to its ring architecture, where buffers are connected to each other and jitter is accumulated through the ring. Meanwhile the additional output stages of buffers add extra jitter to the ILO output.

31 Chapter 3. System Overview 20 By contrast, transmitter path is not considered sensitive since the rising and falling edgesarerelativelysharpduetothehalfvddvoltageswingaswellashighdatarate. This result is in agreement with prior art that indicates the low sensitivity of the transmitter drivers, for example: [15]. 0.2 Jitter Sensitivity (ps/mv) ILO TX Frequency (Hz) Figure 3.3: Jitter sensitivity profile of one slice of TX and the ILO Based upon the supply current and jitter sensitivity spectra, the 4 parallel TXs can be expected to act as aggressors upon the system while the ILO is a sensitive, victim circuit. 3.2 System Design Consideration Use of LDOs According to equation 2.1, to minimize output PSIJ, either jitter sensitivities of the load circuits, PDN impedance, and/or the load current spectra need to be improved. In

32 Chapter 3. System Overview 21 this thesis, the jitter sensitivities of both load circuits are unchanged and linear voltage regulation and the efficient use of decoupling capacitance are used to reduce both supply current and impedance. Specifically, different types of LDO circuits are proposed for aggressor and victim load circuits. Fig. 3.4 shows the two LDOs, LDO1 and LDO2, used for the TX and the ILO respectively. Here only 1 transmitter instead of 4 is shown for simplicity. Figure 3.4: Simplified schematics for studying power integrity of the system showing two load circuits with separate LDOs. Without adding theldos, thepsij ofthetxandtheilo areexpressed respectively in equation 3.2 and 3.1 and the block diagram is shown in Fig In the prototype, the LDOs can be turned off by connecting the gate of the PMOS pass transistors to ground. As a result, the LDO feedback loops are cut and the pass transistors are in triode, modeled as resistors R L1 and R L2 in Fig PSIJ TX (f) = Z PDN (f) (I TX (f)+i ILO (f)) J S TX (f). (3.1) PSIJ ILO (f) = Z PDN (f) (I TX (f)+i ILO (f)) J S ILO (f). (3.2)

33 Chapter 3. System Overview 22 Figure 3.5: Simplified schematics for studying power integrity of the system showing two load circuits with no LDOs. Directly sharing the supply between the load circuits results in the large supply noise term I TX Z PDN being multiplied by the relatively high jitter sensitivity of the ILO which results in poor PSIJ. Introducing LDOs for the load circuits introduces additional parameters in to the above equation so that PSIJ can be improved. Consider two LDOs, LDO1 and LDO2 each having different bandwidth for the aggressors and victim circuit respectively as shown in Fig For example, up to the bandwidth of LDO1, f 1, the current supplied to the TX load comes from LDO1, and above f 1 comes from its decoupling capacitor, C D1. As the bandwidth f 1 decreases, C D1, delivers a larger fraction of the current I TX, and LDO1 provides a smaller portion of the current. This may degrade the supply voltage noise at V DD1, but since these circuits are aggressors with low jitter sensitivity, it should have a relatively minor impact on the transmitter jitter. A benefit of setting the LDO1 f 1 bandwidth low is that the current drawn by the TX load circuits from V DDH would be limited to low frequencies only, specifically below f 1. Thus, LDO1 shields V DDH and, hence, the ILO from the PRBS7 current drawn by the

34 Chapter 3. System Overview 23 transmitters. By contrast, the relatively high jitter sensitivity of ILO, J S,ILO, motivates the need for a high PSR for LDO2 which provides further attenuation of noise from V DDH to V DD2. At typical PDN impedance magnitude peaks in the frequency range MHz [2]. Unfortunately, conventional LDOs show degraded PSR over this medium frequency range (as explained in Chapter 4). Therefore, Chapter 4 describes architectures for LDO2 that can offer improved PSR across this critical frequency range. ThePSIJoftheTXandILOcircuitswithLDO1andLDO2inplaceareapproximated in equation (3.4) and (3.5), where V DDH is expressed in equation (3.3). As discussed, in this scenario V DDH has much less noise compared to the scenario without LDOs since I L1 is a small portion of I TX. The PSR of the LDOs are denoted PSR 1 and PSR 2 for LDO1 and LDO2 respectively. In (3.4) and (3.5), only dominant sources of noise are considered. The source of the transmitter s supply noise is dominated by its own data-dependent current. For the ILO, supply noise due to its own switching current is negligible compared to the external noise, i.e. from the TX. Specifically, it is assumed that I ILO Z VDD2 << V DDH PSR 2 and I TX Z VDD1 >> V DDH PSR 1. V DDH (f) = (I L1 (f)+i L2 (f)) Z PDN (f). (3.3) PSIJ ILO (f) V DDH (f) PSR 2 (f) J S ILO (f). (3.4) PSIJ TX (f) I TX (f) Z VDD1 (f) J S TX (f). (3.5) 3.3 Parallel Aggressors (TXs) It is common to operate high-performance parallel transmitters each under their own separate LDOs, isolating their supply voltages to mitigate crosstalk between them, as

35 Chapter 3. System Overview 24 illustrated in Fig Fig. 3.6 shows 2 scenarios: 1) when the data patterns are correlated; 2) when they are uncorrelated. The impedance looking into each supply node is denoted Z VDD1a, Z VDD1b, Z VDD1c or Z VDD1d respectively. Figure 3.6: Parallel aggressors (TXs) with correlated or uncorrelated data sequences; 1 dedicated LDO for each transmitter Fig. 3.7 shows the current spectrum of the sum of I TX1 to I TX4 when the data in the 4 transmitters are identical PRBS7 sequences at 20Gbps. In the uncorrelated case, the magnitude of the total current is smaller and the pattern is more random, as shown in Fig Although each data sequence is still PRBS7, with different initial conditions for each PRBS generator, the supply current will sometimes get added and subtracted, resulting into a more random spectrum. Alternatively, the outputs of all 4 LDOs can be connected together, as shown in Fig. 3.9 so that the impedance Z VDD1 at V DD1 is 1 of Z 4 VDD1a, Z VDD1b, Z VDD1c or Z VDD1d. Consider 4 totally random uncorrelated data sequences to the transmitters. The rms supply voltage in the two cases in Fig. 3.6 (LDO outputs not connected) and Fig. 3.9 (LDO outputs connected) are shown in the following equations, (3.6) and (3.7) respectively. As a result, the overall supply voltage noise at V DD1 is 1 2 the original case. V DD1a,rms = I TX1 Z VDD1a (3.6)

36 Chapter 3. System Overview Magnitude(dBA) Frequency(Hz) x Figure 3.7: Current spectrum of 4 parallel TXs with correlated data sequences Magnitude(dBA) Frequency(Hz) x Figure 3.8: Current Spectrum of 4 parallel TXs with uncorrelated data sequences V DD1,rms = 1 2 (4I TX1) ( 1 4 Z VDD1a) = 1 2 I TX1 Z VDD1a (3.7) A few cases are simulated to investigate the RMS supply voltage noise with the transmitters operating mesochronously and the 4 data patterns subject to different time delays between the 4 transmitters. Fig plots the relationship between time delay

37 Chapter 3. System Overview 26 Figure 3.9: Parallel aggressors (TXs) with 1 LDO sharing for all transmitters 1 V DD1 (rms) Amplitude Ratio Delay between Data Sequences (s) x 10 9 Figure 3.10: Ratio of V DD1 rms of correlated case to uncorrelated scenarios versus the delaybetween neighbouringtransmitterprbs7datapatternsat20gbps. ThenoiseV DD1 rms is normalized to case with zero delay, which corresponds to identical synchronized data patterns on all 4 lanes and rms supply voltage noise induced on V DD1. The delay time is measured between each neighbouring pair of transmitters, as illustrated in Fig The best case in this sweep

38 Chapter 3. System Overview 27 Figure 3.11: Illustration of data sequences in the 4 transmitters with time delay occurs when each sequence is delayed by 1.6ns from the previous sequence, corresponding to 1 4 ofthecompleteprbspattern, whichis6.4nsindurationat20gbps. Thiscaseshows the lowest correlation between the 4 sequences, therefore shows the smallest amplitude in supply voltage noise, only one-quarter the value observed with identical synchronous data patterns on all 4 lanes. An even better case for supply noise would be, for example, of 2 of the transmitter data sequences were exact inverse of the other 2 inverting sequences as in differential signalling, in which case the total supply current would be zero across a wide frequency range. 3.4 System Level Design Package Model In this section, we consider the problem of optimizing the use of a finite resource (area for on-chip decoupling capacitance) to minimize PSIJ in a parallel transmitter. In this work, it is assumed that sufficient area for 180pF of total decoupling capacitance is available. In the targeted 28nm FD-SOI CMOS technology, a MOM/MIM capacitance has a density of

39 Chapter 3. System Overview 28 9fF/um 2. Hence, 180pF will occupy 20,000 um 2. Assuming a 4-lane transmitter designed to fit under 4 C4-bump I/O pads having a 160um centre to centre pitch, this corresponds to a reasonable 20% of the total area of the transmitter. PCB and package parasitics and decoupling capacitance are modeled as in Fig The values of inductance and capacitance in the model are shown in Table 3.1. Table 3.1: Values of package inductance and decaps used in this work with corresponding package model shown in Fig Fig shows Z PDN versus frequencies. It shows a large peak at around 238MHz which coincides with the resonant frequency of the 180pF decoupling capacitance and a package inductance of 1.9nH. 15 Z PDN (Ohm) Frequency(Hz) x 10 8 Figure 3.12: Package impedance spectrum with 180pF on-chip decoupling capacitors In order to limit supply noise on V DDH, (3.3) - (3.4) show that it is important that no large current from the LDOs arises around 238MHz.

40 Chapter 3. System Overview 29 The two LDO specs need to be set for the system simulation sweep. Remarkably, the LDOs stability and performance are closely related to the values of the decoupling caps. Any change of values in C D1 and C D2 would potentially shift the pole at the LDO output, hence has an impact on the overall LDO bandwidth, PSR and more importantly, stability of the LDOs. From previous discussions, the general spec for the LDOs is to design LDO1 with low bandwidth and design LDO2 with excellent PSR. For this simulation, an ideal model of a conventional LDO topology is used for LDO1 and of a replica biased topology for LDO2 [4]. Details of these LDO implementations are elaborated in Chapter Decoupling Capacitor Allocation The values of the decaps, C D1, C DH and C D2, shown in Fig. 3.4 are swept in this section to find an optimum allocation of decoupling capacitance for each. Throughout, the total decoupling capacitance is kept constant at 180pF. The test bench consists of the package model as shown in Fig. 2.5, schematics of the 4 transmitters and ILO (shown in details in Chapter 4), and schematics of LDO1 and LDO2 where the LDOs amplifiers are modeled in Verilog-A. The package model and the corresponding values of the passive components are described in sections and A Verilog-A model of PRBS generators is used to generate a PRBS7 sequence for each slice. The data streams are synchronized in this sweep in order to capture the worst case transmitter load current transients. To ensure the optimization performed here is predictive of real results, realistic models and specifications are needed for both LDO1 and LDO2. Implementation details of the LDOs are provided in Chapter 4. For LDO1, it has been established that the primary requirement is to reduce the current spectrum drawn from V DDH, I L1 (f), particularly at frequencies exceeding 50MHzwhere Z PDN resonates. This is achieved with a conventional LDO topology having a relatively low bandwidth. Specifically, a first-order feedback

41 Chapter 3. System Overview 30 system is presumed with unity-frequency f 1, is set to 0.37 times the LDO output pole, which is defined as 1/(R O1 C D1 ), guaranteeing a phase margin of 70 degrees for LDO1. R O1 denotes the output resistance of the LDO which consists of r ds of the pass transistor and the equivalent resistance of the transmitter load. Meanwhile the dc gain of the LDO, defined as A LDO, was set to 60dB. The LDO amplifier is therefore modeled as having a first-order low pass response with dc gain A OP and pole frequency f P1. Based on these assumptions, f P1 is set as in equation (3.8). f P1 = π(R O1 C D1 ) A LDO (3.8) Figure 3.13: Conceptual graph of Z VDD1 as C D1 varies; LDO1 bandwidth changes with C D1 Fig shows a conceptual graph of how Z VDD1 changes as C D1 varies. As C D1 increases, the frequency of the dominant pole of LDO1 decreases. Z VDD1 starts degrading from a smaller frequency and the worst case value (at LDO1 bandwidth) occurs at a smaller frequency as well. Basically the entire impedance curve moves to leftward which would improve the impedance at medium-high frequency range based on the low bandwidth nature of this LDO. For LDO2, it is desirable to maintain a low PSR across a wide range of frequencies,

42 Chapter 3. System Overview 31 Figure3.14: ConceptualgraphofPSR 2 asc D2 varies; LDO2bandwidthremainsconstant particularly including the PDN resonant frequencies around MHz where supply noise is expected to be worst. Therefore, a high-bandwidth replica-biased LDO is presumed with < -12dB of PSR this frequency range, which is consistent with results obtained for similar LDO topologies in [1] and [18]. Note that assuming -12dB PSR across all frequencies restricts the minimum amount of C D2 to certain value, as discussed in section The bandwidth of the replica-biased LDO is set so that -12dB worst case PSR is satisfied at MHz range at the worst case of C D2 being swept. Fig shows a conceptual graph of how PSR 2 changes as C D2 varies. As C D2 increases, the worst case PSR gets improved, while the setting for LDO2 bandwidth remains unchanged. Since there are 3 values of decoupling capacitors to be set, first C DH is determined. Fig and 3.16 show the peak-to-peak supply voltage noise on V DD1 and V DD2 with a sweep of C DH versus C D1 and C DH versus C D2 respectively. The decap C DH is swept from a minimum value of 5pF/lane because that is the value for minimum decoupling capacitance extracted from the power tiles connection in the layout. In Fig. 3.15, 10pF/lane is kept constant for C D2 while C DH is swept with the sum of C DH and C D1 kept constant at 35pF/lane. It shows the supply noise of V DD1 is lowest for small values of C DH. In addition, the peak-peak amplitude of V DD2 noise is constant at 3mV throughout these scenarios.

43 Chapter 3. System Overview 32 V DD1 peak peak noise amplitude (mv) C DH /lane (pf) Figure 3.15: Peak-peak V DD1 noise as C DH is swept, assuming the sum of C DH and C D1 is held constant at 35pF/lane and C D2 equals 10pF/lane In Fig. 3.16, C D1 kept constant at 30pF/lane while C DH is swept with the sum of C DH and C D1 kept constant at 15pF/lane. It again shows the supply noise on V DD1 is lowest for small values of C DH. When C D2 gets significantly smaller, supply variation on V DD2 is mainly switching noise at 10GHz and above, which indicates the decoupling capacitance C D2 is too small to filter the self-induced noise from the ILO. In addition, the peak-peak amplitude of noise on V DD1 is constant at 60mV throughout these scenarios. It can be seen that allocating available area for C D1 and C D2 has a more direct effect onimprovingpsijthanc DH becausev DD1 andv DD2 arethetwosupplynodesthatsupply current directly to the load circuits. Therefore, C DH was first set to a minimal value of 5pF/lane (20pF total) and the remaining 160pF is allocated to be shared between C D2 and C D1. With the value of C DH set, C D1 and C D2 can be swept. The LDOs are turned on/off

44 Chapter 3. System Overview 33 V DD2 voltage noise AC (mv) C DH /lane (pf) Figure 3.16: Peak-peak V DD2 noise as C DH is swept, assuming the sum of C DH and C D2 is held constant at 15pF/lane and C D1 equals 30pF/lane so that the PSIJ of the load circuits can be compared to show the effect of the LDOs. As mentioned earlier, to turn the LDOs off, a switch to ground is closed at the gate of their PMOS pass transistors, biasing them in triode so they act like resistors. Fig to Fig show example plots of the supply noise spectra of V DDH, V DD1 and V DD2 for the case where C D1 is 30pF/lane and C D2 is 10pF/lane. Compared to the scenario where the LDOs are turned off, the supply noise on V DDH and V DD2 are improved significantly when the LDOs are on, while V DD1 noise is comparable in the two cases. The resulting eye diagrams of one transmitter and of the ILO output clock with the LDOs turned on or off are shown respectively from Fig to Fig The transmitter output goes through ac coupling and a 50-Ohm (ideal) termination resistor. The swing of the transmitter is 500mVpp. The ILO output has rail to rail swing (i.e. 1Vpp). The peak-to-peak jitter is measured for both eye diagrams.

45 Chapter 3. System Overview 34 Figure 3.17: Supply voltage noise of V DDH when LDOs are on/off (a) (b) Figure 3.18: Supply voltage noise of (a) V DD1 and (b)v DD2 when LDOs are on/off The result of the decoupling capacitors sweep is shown in Fig Note that increasing C D1 improves PSIJ TX directly, but has very little impact upon PSIJ ILO. The reason is that jitter in the transmitter is dominated by I TX and Z VDD1, and increasing C D1 improves Z VDD1 at med-high frequencies. On the other hand, jitter in ILO as a

46 Chapter 3. System Overview Voltage(V) Voltage(V) Time(s) x Time(s) x 10 7 (a) (b) Figure 3.19: Eye diagrams of transmitter output with correlated data sequences at 20Gbps when LDOs are (a)off, and (b)on Voltage(V) Voltage(V) Time(s) x Time(s) x 10 7 (a) (b) Figure 3.20: Eye diagrams of ILO output operating at 10GHz when LDOs are (a)off, and (b)on. victim circuit is dominated by the noise transferred from the aggressors data dependent current noise. The increase in C D1 (decrease in C D2 ) results in an improvement in supply noise at V DDH and degradation of PSR 2. The cancellation of these two effects result in an unchanged jitter output in the ILO. Based on Fig. 3.21, C D2 was set to be 10pF/lane, and C D1 was set to 30pF/lane. C D2 was chosen to be 10pF/lane not 5pF/lane because larger C D1 makes it more challenging

47 Chapter 3. System Overview Peak peak jitter (ps) TX ILO C D2 /lane (pf) Figure 3.21: PSIJ of the TX and ILO circuits are simulated as the decoupling capacitance C D2 is swept, assuming the sum of C D2 and C D1 is held constant at 40pF/lane, when LDOs are on. to stabilize LDO1 and more dominant pole compensation is required, which costs extra area. In summary, this means LDO2 has total 40pF output decoupling capacitors, LDO1 has total of 120pF and C DH has 20pF connected to V DH, as shown in Table 3.2. Based upon this optimization, some general conclusions can be offered. As mentioned, it is more efficient to place decaps at C D1 and C D2 rather than C DH because C D1 and C D2 are directly connected to the supply nodes of the load circuits, impacting the impedance at the supply nodes directly. In order to determine allocation between C D1 and C D2, the frequency range where load currents switch need to be known. In this case PRBS sequences in the transmitters show a broadband current switching spectrum whereas the ILO generates switching current only at 10GHz and above. The advantage of allocating more decoupling capacitance at C D1 is two-fold: first it lowers the supply variation at

48 Chapter 3. System Overview 37 V DD1 directly, reducing PSIJofthetransmitters; second, increasing C D1 reducesi L1 which resultsinsmallervariationinv DH. Ontheotherhand, Theimpactofsupplyvariationson V DD2 due to ILOs own switching current is negligible because switching current at 10GHz and above gets easily filtered compared to the broadband PRBS current. Increasing C D2 improves the PSR of LDO2, which further rejects noise from V DDH. To maintain the same worst-case PSR in LDO2, a larger decap C D2 allows for a smaller LDO bandwidth, hence less power in the consumption in the LDO2 amplifier. In this work, reducing PSIJ is established as the primary design criteria and simulations show allocating the majority decoupling capacitance to C D1 is therefore preferable. Table 3.2: Decap values based on decap sweep simulation study.

49 Chapter 4 Circuit Implementation 4.1 System Overview Fig. 4.1 shows a block diagram of all the circuits included in the 28nm SOI CMOS prototype I.C. to study power management in high-speed I/O transceivers including four transmitters (supply noise aggressors), an ILO (supply noise victim), LDOs for the load circuits, supply monitoring and injection circuits. In this chapter, implementation details of each are presented. Figure 4.1: Top level diagram of the system implemented on chip 38

50 Chapter 4. Circuit Implementation 39 Table 4.1 shows the power supply partitioning of the chip. Table 4.1: Circuits and decoupling caps under each supply domain on chip There are three power domains in this prototype: V DDH, V DDSR and V DDC. The LDOs can be either bypassed or enabled. In this way, the difference in PSIJ between these two scenarios can be compared. With the LDOs bypassed, all supplies are set to the technology s nominal value of 1V. When the LDOs are on, V DDH is slowly increased to 1.3V while the regulated supply voltages go to 1V. The supply V DDSR powers the digital control blocks, which consists of 6 12-bit shift registers. The supply V DDC powers the rest of the circuits, listed in the same table. A total of 2nF decoupling capacitance is placed under this supply as it is important to keep this voltage quiet to avoid introducing extra PSIJ to the outputs. The total current consumption is around 200mA from V DDC. Due to its relatively large dc current consumption, 3 I/O pads are used for V DDC. 4.2 Transmitters Each transmitter has its own PRBS generator and clock distribution circuit, as shown in Fig First, a half-rate differential clock, Ckin and Ckip, is provided from off-chip and terminated with nominally 50-ohms per side on-chip. After the termination, the clock is divided to quarter-rate and outputs 4 phases of clock, Φ 0 -Φ 270, among which Φ 0 and Φ 180 are the input signals to the quarter-rate PRBS generators, and all 4 clock signals go

51 Chapter 4. Circuit Implementation 40 to the 4-1 multiplexer in each transmitter. Each slice of transmitter has its own clocking distribution circuits consisting of CMOS buffers and frequency dividers. Details of the clocking distribution circuits can be found in [16]. The initial condition of the PRBS generators can be adjusted to allow for experimental study of how correlation between the data patterns on multiple single-ended transmitter lanes impacts the integrity of a shared power supply. The clocking circuits and PRBS7 generators consume a large current and are not of focus of the power integrity studies in this work, so they are operated under a common separate supply voltage, V DDC, which is designed to have large decoupling capacitance (2nF) and therefore induce negligible PSIJ. Figure 4.2: Schematics of TXs with real output to off chip for TX1 and dummy output for TX2-4 The transmitter circuits consist of 4 to 1 multiplexers, pre-drivers and output drivers.

52 Chapter 4. Circuit Implementation 41 They are designed using CMOS logic circuitry so that higher power efficiency is achieved compared to CML logic. The output stage is identical to that of [16], except that the passive de-emphasis equalizer is removed; as described in [16], the worst-case injection of supply noise is generated with no passive equalization at the driver output. The output driver has nominally 50-Ohm output impedance. The total average current of the transmitter under V DDH is around 4.5mA, assuming 50-Ohm termination, a 1-V supply, and the output swing is 0.5V. Not all 4 transmitter outputs are brought off-chip for testing. To save pins, only one transmitter output is connected to a pad for measurement. On chip dummy termination is designed for the other 3 transmitters. Fig. 4.2 shows the block diagram of both the TX with output pin and one of the other three transmitters including the dummy termination on chip, consisting of a 50-Ohm resistor and 50pF capacitor. The capacitor is to hold the DC value of the transmitter outputs around to 0.5V, as will be the case in TX1 which is driving an ac-coupled off-chip 50-Ohm termination. 4.3 ILO The block diagram of the ILO is shown in Fig It takes the same half-ratedifferential clock from off-chip and an 8-bit digital control word to adjust its free running frequency. The ILO is followed by a 50-Ohm clock driver, as shown in Fig The supply V DDC is used for this driver so that it is excluded from the power integrity study, as it would not be part of a practical transmitter. Fig. 4.3 shows the schematics of the ILO. The input differential 10GHz clock signal is provided from off-chip and terminated on-chip. Input control bits are converted to an analog control voltage that tunes the free running frequency of the ILO. The main part of the ILO consists of two-stage ring along with additional buffers to generate quadrature

53 Chapter 4. Circuit Implementation 42 Figure 4.3: Schematics of ILO output clock signals. Details of the ILO are provided in [19]. Figure 4.4: Block diagram of ILO and its clock driver for off-chip

54 Chapter 4. Circuit Implementation LDO for Aggressors (Transmitters) Background on Conventional LDOs Choice in Pass Device LDO topologies may be categorized according to the pass device type. Figure 4.5: Schematics of 2 conventional LDOs with(a)pmos and(b)nmos pass devices respectively. Fig. 4.5 (a) and (b) show the schematics of a conventional LDO with PMOS pass device and NMOS pass device respectively. With NMOS pass device, the drain is connected to the supply. Hence Vgs of the pass device is not impacted by supply noise, therefore the LDO has better PSR than a PMOS pass device. However, a relatively high voltage is required at the gate. For example, for a source voltage of 1V and Vgs of 500mV, 1.5V needs to be generated at the gate of the pass device. By contrast, a PMOS pass device can operate with a gate voltage below V REG, and therefore can have a much lower dropout voltage and better power efficiency. But, it has worse PSR because supply modulates Vgs and, hence, the large drain current. Stabilities of LDOs Fully integrated LDOs are commonly used to improve power integrity, but stability considerations make it difficult to ensure stability without consuming large area and/or

55 Chapter 4. Circuit Implementation 44 power consumption. As shown in Fig. 4.6, a large pass device is usually required to provide enough supply current to the load, therefore the gate capacitance of the pass device is usually substantial. One of the two most significant poles in the LDO feedback open-loop response, f G and f O identified in Fig. 4.6 must be made dominant to ensure stability. Figure 4.6: Conventional LDO with 2 poles: f O is the pole at LDO output; f G is the pole at amplifier output. Figure 4.7: The small signal schematic of a basic voltage regulator The corresponding small signal schematics ofsuch anldoisshown infig. 4.7, where V 1 and V reg are the two nodes as labeled in Fig. 4.6 [20] and a single-stage operational transconductance amplifier is assumed. If f G is made the dominant pole, supply rejection starts to degrade at f G due to dropped loop gain until the second pole f O provides a first

56 Chapter 4. Circuit Implementation 45 order roll-off to the supply rejection. When necessary, additional capacitor at the output of the amplifier needs to be added for dominant compensation. In contrast, by making f O dominant, the amplifier needs to have very high bandwidth and/or the capacitance C REG has to be large to ensure f G >> f O. Since the pass device gate capacitance is usually large, making f G very high makes the amplifier design very challenging, generally consuming high power LDO Design for Aggressor Circuits PMOSpassdevices areusedtoprovidehighpower efficiency, andf G issetasthefeedback loop s dominant pole to save quiescent power. It is not realistic to set f O as dominant pole in this case because with a modest output capacitance of 30pF, it would require enormous power consumption in the LDO amplifier to push f G high enough to provide good phase margin. However, as described in [20], the result is degraded PSR at midfrequencies. To improve the worst case PSR, a compensation cap Cc of 3pF is placed between V G and V DDH. It helps to ensure that Vgs of the pass device is less influenced by the supply noise. It is also used for dominant pole compensation in this configuration. The schematics of LDO1 are shown in Fig For open loop analysis, the load TX is replaced with an ideal resistor which draws the same current as the average current in the transmitter load. In this work, 1 unit LDO is designed for each transmitter, and all unit LDOs have their outputs shorted together. As discussed in Chapter 3, connecting the LDO outputs across all lanes can reduce the supply voltage noise when the transmitter s input data streams are uncorrelated. The reason to build a unit LDO for each lane instead of one single LDO for all transmitters is: a) to allow the LDO to be scaled down in a situation where some transmitters are powered off, but others remain active; b) to distribute the pass transistors and decoupling capacitance evenly across all lanes; c) to provide a regular layout.

57 Chapter 4. Circuit Implementation 46 Figure 4.8: Schematics of LDO1 Both the transistors in the amplifier and the pass device used in the LDOs are the thick oxide devices since the raw supply voltage is 1.3V instead of 1V when the LDOs are in use. The minimum length of these transistors are 100nm. Figure 4.9: Loop gain of LDO showing shifted second pole with light and heavy load From system simulations, 30pF of output capacitance C D1 per lane is used. The average load current is 4.5mA, while a range from 3mA to 6mA depending on PVT

58 Chapter 4. Circuit Implementation 47 variations is assumed as the load current requirement for the LDO design. The value of decoupling capacitance and load current defines the pole location at the LDO output. Changes in load current have a direct effect on stability of LDOs, as shown in Fig When the output pole is the non-dominant pole in the feedback system, lower current brings it to a lower frequency which degrades phase margin. The target is to make the phase margin at least 60 degrees at the minimum anticipated load current, 3mA. Pass Device Design The PMOS pass device acts as current source to provide current to the load. It is important that this transistor is large enough to provide the required load current while keeping the transistor in saturation. If the transistor is too large, the opamp power consumption may have to increase and/or the circuit area will increase. The PMOS pass device has a total gate width of 352um and gate length of 100nm. Opamp Design In addition to having a dominant pole at the amplifier output node, it is preferred for the amplifier to have large DC gain to achieve DC accuracy. Based on these considerations, a folded cascode topology meets the requirements. Fig shows the schematics of the folded cascode amplifier. The input common mode voltage of the amplifier is 1V, so an NMOS input pair is used. Based on the bandwidth of the LDO and the size of the pass device, the current for each of the input pair transistors in the amplifier is approximately 5uA. Table 4.2 shows the sizes of each transistor in the opamp. Both W and L of the input pair are relatively large in order to minimize the opamp offset, in spite of the relatively small current consumption in this LDO. The gate length of the current sources is 300nm (3x larger than the minimum drawn gate length of 100nm) to achieve small mismatch. The gate length of the cascode devices is the minimum so that its parasitic capacitance is

59 Chapter 4. Circuit Implementation 48 Figure 4.10: Schematics of folded cascode amplifier in LDO1 Table 4.2: Transistor sizes of folded cascode amplifier in LDO1 minimized to increase the non-dominant pole frequencies in the folded cascode amplifier. The amplifier DC gain is 57dB and its first pole is at 4.5kHz. Biasing Circuits Fig shows the schematics of the biasing circuits for the folded cascade amplifier. A wide swing current mirror is used to generate the bias voltages for the cascode devices. Table 4.3 shows all the sizes of the transistors in the biasing circuit. Since the LDO has

60 Chapter 4. Circuit Implementation 49 very small current consumption and only 5uA is mirrored, all of the transistors have only 1 finger. Transistors M6 to M10 generate the bias voltage for the cascode PMOS in the amplifier. Transistor M6 has the same size as the cascode PMOS for better tracking. Transistors M7-M10 are in series since 100nm is the minimum gate length for thick oxide devices. The lengths of these transistors are tweaked until the Vdsat of M6 is around 70mV. Similarly, transistors M12-M16 are used to generate the bias voltage for cascode NMOS in the amplifier. Transistors M17 to M19 are the power down transistors to ensure there is no current flowing through all transistors during power down mode. Transistor M3 is made in the spare area in the layout for decoupling purposes. Figure 4.11: Schematics of folded cascode amplifier biasing circuit in LDO1 The total quiescent current of this LDO is 30uA including the biasing circuits. Fig shows the simulated open loop gain bode plot of the LDO unit. This bode plot was simulated at a slow-slow process corner at 80 degrees Celcius and 4.5mA load current.

61 Chapter 4. Circuit Implementation 50 Table 4.3: Transistor sizes of folded cascode amplifier biasing circuit in LDO1 The simulated DC gain is 67dB, and the first pole is at 4.5kHz. Phase margin is 70 degrees Loop gain(db) Phase(deg) Frequency(Hz) Figure 4.12: Bode plot of LDO1 loop gain

62 Chapter 4. Circuit Implementation LDO Design: for Victim Circuits The discussion in Chapter 3 indicates the importance of wide spectrum PSR for LDO2. However, a conventional LDO topology like LDO1 is not suitable for this LDO design. In this section, high PSR LDO topologies are discussed and a detailed implementation of the LDO is presented Background of High PSR LDOs Supply noise impacts the LDO output by 4 sources, according to the analysis in [21]. Fig shows the 4 paths where the noise is introduced: 1. r ds of transistor, 2. g m of the pass transistor, 3. through the amplifier, 4. through Vref. LDO research has focused on minimizing the impact of 1 and 2 on the PSR. In this work, path 3, the PSR of the amplifier is also analyzed and tackled. Regarding path 4, in this work the generation of Vref is not considered and is assumed to be ideal in the analysis. Researchers have developed many ways of improving power-supply rejection in LDOs. The idea of including another PMOS transistor whose gate is biased with a charge pump in series with the PMOS transistor is presented in [22]. This idea complicates the design and an additional clock is required for the charge pump which increases power consumption. An alternative LDO architecture with PSR better than -56dB up to 10MHz and low quiescent current is presented in [21]. A feed-forward path is proposed in [21] so that the combination of paths 1 and 2 cancel. However, this approach only enhances PSR at low-mid frequencies. Once loop gain starts degrading, PSR is degraded as in a conventional LDO.

63 Chapter 4. Circuit Implementation 52 Figure 4.13: Illustration of 4 paths that supply noise feeds to the LDO output The worst case PSR occurs at the point where loop gain decreases to minimum while the output RC filter has not come into effect. However, pushing these two points close to each other would result in instability in this feedback system. Figure 4.14: Schematics of replica biased LDO [4] This scenario is analyzed in [4] and [23] and a solution known as a replica biased LDO is proposed, as shown in Fig Instead of having two low-med frequency poles in the system, the replica biased LDO relaxes the loop by placing the output pole outside of the loop. A replica of the output node is created by a replica load drawing a small but

64 Chapter 4. Circuit Implementation 53 constant fraction of the load current. The main challenge in this topology is the difficulty in implementing a replica load. The main load circuitry has to be known exactly and it has to be feasible to replicate a small fraction of it in the replica load. A replica biased LDO is presented in [24] with a method of building a replica load that automatically tracks the real load. Specifically, an additional feedback loop is added whichadjustsreplicaloadcurrentsothatv DD2 followsv REP, asshowninfig Inthis way, the main loop involving Op1 regulates V REP with high bandwidth, since no large output decoupling capacitor is required there. The second loop ensures V REG follows V REP. Since there are two loops, the second loop has to be slow enough not to affect the stability of the entire system LDO Design The design of LDO2 is based upon [24] with a few modifications which are discussed in the following sections. Figure 4.15: Schematics of LDO2

65 Chapter 4. Circuit Implementation 54 The PSR of this LDO may be understood as follows. Its PSR at dc is inversely proportional to the DC gain of Op1 in the main loop (L1 as shown in Fig. 4.17). Once the dominant pole of L 1 (j2πf) loop kicks in, the PSR starts degrading. In the absence of C D2, the worst PSR happens at the unity gain frequency of the loop L 1 (j2πf). If the pole at the output due to C D2 occurs at or below that unity gain frequency, then the worst case PSR is improved. In summary, in order to improve the worst case PSR, either C D2 or the unity gain bandwidth of L 1 (j2πf) needs to be increased. Since C D2 is constrained by the available area, it becomes important to push all non-dominant poles of L 1 (j2πf) to higher frequencies. 0 Magnitude(dB) Frequency(Hz) Figure 4.16: PSR of LDO2 Fig shows a PSR simulation result of this LDO. At low frequency, -41dB of PSR is achieved. The worst case PSR is around -15dB, which is at least 15dB improvement than the worst case PSR of a conventional LDO (typically approximately 0dB [25]). This PSR result was obtained under the simulation conditions shown in Table 4.4. An even better PSR result (worst case) was obtained in [21] (-22dB). One reason is

66 Chapter 4. Circuit Implementation 55 Table 4.4: Settings for LDO2 s PSR simulation. thatinthis workc D2 isset to 40pF,while in[21], the capacitorvalueis 80pF.Inaddition, it is found the unity gain frequency, f t, of the thick oxide devices in this technology is much lower than those used in [21], which translates into lower unity gain bandwidth. Since there are multiple loops in this LDO, stability analysis is more complicated than conventional LDOs. The loop gain analysis for this multi loop system is obtained by breaking the loop at V REP, as showed in Fig The overall loop gain is the superposition of the 3 transfer functions of all 3 paths, as shown in equation 4.1. This equation is elaborated in the following equations 4.2, 4.3 and 4.4 in details. Specifically, path 1 is from the positive terminal of Op1, through A MPr to V REP ; path 2 is from the positive terminal of Op1, through A MP, Op2 and a voltage controlled resistor (A VCR ), finally to V REP ; path 3 is from the positive terminal of Op2, through A VCR to V REP. L LDO2 = L 1 +L 2 +L 3 (4.1) L 1 = A OP1 A MPr (4.2) L 2 = A op1 A MP A OP2 A VCR (4.3) L 3 = A OP2 A VCR (4.4) A zero is formed where L 1 (2πf z ) = L 2 (j2πf z ). Compared to L 1 (j2πf) and L 2 (j2πf), L 3 (j2πf) has smaller dc gain and a lower frequency pole, thus its effect is negligible in the final transfer function.

67 Chapter 4. Circuit Implementation 56 Figure 4.17: Simplified schematics of LDO2 with the loop broken at V REP node Figure 4.18: Illustration of the loop gain of 3 individual paths in LDO2. Fig shows a conceptual diagram of the transfer function of the 3 paths mentioned above. The bode plot of the loop gain of the entire system is shown in Fig First pole is at 3kHz at the output of OP2. The second pole is at 1MHz at the output of OP1. Then a zero occurs at around 6MHz introducing a phase lead. The resulting phase margin is

68 Chapter 4. Circuit Implementation Loop gain(db) Phase(deg) Frequency(Hz) Figure 4.19: Bode plot of loop gain in LDO2 65 degrees. The transistor sizes of the LDO circuits are specified in the following sections respectively. Main and Replica Pass Devices The ratio of load current to replica current provides a trade-off between the LDO s quiescent current and stability. Lower replica current reduces quiescent current and, thus, increases LDO current efficiency. However, to achieve smaller replica current, value of R FIX as labeled in Fig has to increase which pushes the non-dominant pole at V REP to a lower frequency, degrading stability of the loop. In this work, the replica to main current ratio is set to 1:15, resulting in better efficiency than in [24] where the ratio was 1:10. The size of the main and replica pass devices are shown in Table 4.5.

69 Chapter 4. Circuit Implementation 58 Table 4.5: Transistor sizes of the pass devices in LDO2. OP1 Design Gain and Bandwidth Considerations The DC gain of OP1 determines the LDO output voltage accuracy and PSR at dc. As in LDO1, the large capacitive load at the output of the amplifier (i.e. the pass device gate capacitance) gives rise to the dominant pole of the loop. Since one of the key considerations is to extend the bandwidth of this regulator, it is desirable to push the non-dominant poles to the highest possible frequency. Hence, a simple single-stage amplifier is used. PSR in Opamps The PSR of the LDO s main amplifier in (OP1) may impact the overall PSR of the LDO (path 3 in Fig. 4.13). Figure 4.20: a) Type A b) Type B single stage amplifier [5]. In [5], the two types of amplifiers shown in Fig are distinguished. Ideally, in the

70 Chapter 4. Circuit Implementation 59 type A amplifier, the supply noise appears at the amplifier output with unity gain, while in the type B amplifier supply noise is rejected. This can be interpreted intuitively as follows. In the type A amplifier, source of the current mirror transistor is connected to the supply. Noise on the supply therefore results in a change in the gate of the current mirror transistor, thus impacting the output. On the other hand, in the type B amplifier, the supply voltage connects to the bias tail current source, thus any noise in supply does not transfer to output, resulting in better supply rejection. Therefore, a type A amplifier is better suited to a LDO with PMOS pass device so that both the gate and source of the pass device see the same noise and thereby keep its V gs relatively constant. This potentially helps enhance the PSR of the overall LDO at low frequency. On the other hand, a type B amplifier is good for NMOS pass devices so that both gate and source of the pass device are shielded from supply noise. OP1 Implementation The schematics of the single stage opamp is the same as Fig a), and table 4.6 shows the transistor sizes. The DC gain of OP1 is 33dB and the dominant pole is at 1MHz. This opamp consumes 245uA of current. Table 4.6: Transistor sizes of the single stage amplifier in Fig (a). Op2 and VCR Design The second feedback loop includes Op2 and VCR as shown in Fig The purpose of this loop is to make V REG track V REP by adjusting the equivalent resistance in the VCR. Op2 A folded cascode amplifier very similar to the one in LDO1 is reused for LDO2. Fig shows the schematics of the amplifier with transistor sizes as in Table 4.2.

71 Chapter 4. Circuit Implementation 60 The only difference compared to Fig is that the current mirror is formed from the NMOS devices instead of PMOS devices. Similar to the previous discussions on opamp PSR, the amplifier used inldo1 shown infig.4.10 will couple supply noise to the opamp output, which is desirable in LDO1, whereas Fig will not, which is desirable since it is used to drive a NMOS VCR [5]. The biasing circuits and transistor sizes are given in Fig and Table 4.3, respectively. Figure 4.21: Schematics of OP2: folded cascode amplifier in LDO2 VCR The VCR input Vcr controls adjusts Vgs of the NMOS, M2, thus controls the current drawn from V REP, i.e. its equivalent resistance. The schematics are shown in Fig The choice of the transistor sizes and R fix depends on the desired variable resistance range and has an effect on a non-dominant pole frequency in the feedback loop location. A larger R fix results in a smaller fixed current thus larger current tuning range; meanwhile the overall resistance is higher which decreases the pole frequency at V REP, degrading the bandwidth and PSR of the LDO. Therefore, R fix is chosen based on the minimum expected ILO current. Table 4.7 shows the maximum and minimum Vcr and

72 Chapter 4. Circuit Implementation 61 their corresponding replica current. The nominal 32mA ILO average current is centered within the range. Figure 4.22: Schematics of the VCR - voltage controlled resistor Table 4.7: Current range of VCR 4.6 Operation of LDOs In order to compare PSIJ performance with and without the presence of the voltage regulation by the LDOs, the LDOs have the option to be bypassed. In bypass mode, the LDO s internal opamps are powered down and pass device gates are grounded, putting the pass device deep into triode region acting like a resistor. Fig shows the power down mechanism in LDO1 and LDO2. During the power down phase, the PD signal is set high so that the biasing circuit of the opamp is turned off.

73 Chapter 4. Circuit Implementation 62 A separate power down signal is applied to OP2 in LDO2. Figure 4.23: Schematics of LDO1 and LDO2 with power down connections. 4.7 Supply Noise Injection In order to measure the PSR of the LDO, an on-chip supply noise generator is included to create supply noise at desired frequencies, which can also be used to measure supply noise. One single large NMOS transistor, Q n as shown in Fig. 4.1 with a total width of 240um and length of 100nm is connected with drain to V DDH to optionally create sinusoidal supply voltage noise at a specific frequency, as shown in Fig A clock signal from off-chip is terminated with a 50-Ohm resistor to ground on-chip and applied tothegateofq n. Theresulting draincurrent variesupto60mapeak-to-peak, depending upon the input clock amplitude, and introduces supply noise, V DDH = I D,n Z PDN. The modulation frequency can be varied from 1MHz up to 1GHz depending on the clock frequency, which covers the frequency range where Z PDN peaks and where large digital logic circuits are clocked. Below 1MHz, even large currents result in small supply voltage noise due to the low dc impedance of supply and ground nodes. Beyond 1GHz, the decoupling capacitance makes Z PDN small, again making it difficult to introduce supply

74 Chapter 4. Circuit Implementation 63 noise. It is important for this study that the supply noise on-chip is accurately measured. Circuitry enabling supply noise measurement up to 1GHz are discussed in Chapter 5.

75 Chapter 5 Measurement Methodology and Results 5.1 Supply Noise Measurement Developing a proper way to measure the supply noise is important in this work because the transient/spectrum measurement of V DDH, V DD1 and V DD2 are of great interest. Onboard probing is a direct way of measuring the supply noise [12]. However, the method works only up to a few MHz due to packaging inductance. As mentioned in section 4.7, it is desired to capture the supply noise from 1MHz to 1GHz. Therefore, an alternative method needs to be developed in this work to meet this bandwidth target. On-chip supply noise measurement was tackled in [4]. An on-chip ADC was used to digitize the supply noise. A time-based ADC based upon a VCO and a counter was used. The drawback is the design would become more complicated to achieve high resolution, and offset/gain error might vary with temperature variations. As this testing circuitry is a small portion of the chip, it is expected to be simple and robust. Alternatively, an onchip buffer is considered to drive the packaging parasitics so that the bandwidth target can be met. The digitization is realized using off-chip equipment such as a real-time 64

76 Chapter 5. Measurement Methodology and Results 65 scope and spectrum analyzer, which provides high sensitivity. In this work, both on-board probing and measurement using buffer are utilized for supply measurement On-Board Probing In this work, on-board probing is utilized to measure V DDH. There are two main motivations to implement this probing solution. One reason is to enable some quick and direct supply noise measurements during testing. The other reason is for gain calibration for the measurement method using buffer, which is elaborated in the next section. Figure 5.1: Cross sectional view of the stacking of the chip, package substrate and PCB board. In [12], the on-board probing method named spy hole is introduced for supply noise measurement in flip-chip package design. A pair of supply and ground BGAs routed out on PCB are used for probing. However, the main problem is that high frequency supply noise gets filtered by the significant amount of decoupling capacitances in the package substrate and on the board. To reduce the filtering of the supply noise, one of the V DDH I/O pads on-chip is routed to its dedicated BGA separately from other supply I/O pads, as shown in Fig In other words, it is treated as a signal instead of supply as it does not get connected to the power plane in the package substrate or the decoupling

77 Chapter 5. Measurement Methodology and Results 66 capacitors on-board, resulting into smaller decoupling capacitances thus less filtering of supply noise Measurement Using On-chip Buffer Three supply voltages, V DDH, V DD1 and V DD2, are sent to off-chip for measurement. Fig. 5.2 shows the schematics of the supply monitor circuits along with the off-chip model. The three supply voltages, V DDH, V DD1 and V DD2, each have their own switch and control bit. A decoder ensures only one of the switches is on at a time to avoid a short circuit between supplies. These supply nodes pass through a high pass RC filter so that no dc component is passed through. A unity gain feedback buffer is designed to bring the signals off-chip. Then the signals go though the package substrate and PCB traces, which are shown as the package model and micro-strip model in Fig. 5.2 respectively. Finally, the scope model is shown, where typical values of the passive termination are labeled. Figure 5.2: Schematics and modeling of the supply monitor path Fig. 5.3 shows the AC response of the supply monitor path in Fig. 5.2 under 3 PVT conditions. The targeted bandwidth from 1MHz to 1GHz is achieved across PVT corners. The nominal mid-band gain of the path is around -6dB with ± 0.5dB variation over PVT variations, thus needs to be calibrated. Single-point calibration is performed at lowfrequency (e.g. 1MHz) by introducing asinusoidal supply noisetov DDH at1mhz. By comparing the supply noise measured directly via on-board probing and via the on-chip buffer, the gain of the buffer path can be calibrated, and (based upon the simulations in

78 Chapter 5. Measurement Methodology and Results 67 Fig. 5.3) is assumed constant over the entire frequency range 1MHz - 1GHz. 0 AC supply noise gain (db) SS, 80deg FF, 40deg TT, 27deg Frequency (Hz) Figure 5.3: AC response of the supply monitor path Implementation of Unity Gain Buffer The unity gain buffer requires a closed-loop bandwidth exceeding 1GHz, but gain accuracy is not critical since the gain will be calibrated anyway. Therefore, a simple single stage amplifier is used. The common mode of the input is set to be 300mV by a resistive divider so that the input pair is PMOS, which rejects supply noise [5], as described in section The supply for this amplifier and the resistive divider that establishes the common-modeinput isv DDC, sothat itis isolatedfromv DDH, uponwhich power integrity analysis is performed. The schematics of the amplifier inside this buffer is identical to 4.20 (b), where PMOS input pair is used. Table 5.1 shows the transistor sizes of this amplifier. The amplifier consumes 3mA and has a unity gain bandwidth of 3.5GHz. The phase

79 Chapter 5. Measurement Methodology and Results 68 Table 5.1: Transistor sizes of the single stage amplifier used in supply monitor buffer, schematics shown in Fig (b). margin is 75 degrees. 5.2 Testing Setup Figure 5.4: Die photo The prototype was implemented in ST 28nm FD SOI process and Fig. 5.4 shows the die photo. The die has dimension of 1mm x 1mm, and it is flip-chip packaged onto a customized organic substrate. Then the packaged prototype is mounted on a high speed

80 Chapter 5. Measurement Methodology and Results 69 (a) (b) Figure 5.5: a) DC PCB used for supply and biasing and b) high speed PCB with the chip and SMA connectors PCB via BGAs as shown in Fig. 5.5 (b). Regarding the PCBs, there are two boards. The DC board shown in Fig 5.5 (a) is made dedicated for power supply, dc biasing and digital control. The supply pins, reference pins and shift register pins are set/programmed on this board and sent to the high speed board in 5.5 (b). The high speed board consists of the packaged chip, pins from the dc board, decoupling capacitors and high speed SMA inputs/outputs. It is more reliable to have dc and high speed testing on two separate boards. DC signals and digital control bits can be verified on dc board before connecting them to the packaged prototype. 5.3 Results Fig. 5.7 to Fig. 5.8 show the simulation results in 27 degrees Celsius, typical corner with back annotated parasitics in Cadence schematics view while LDOs are turned on. The ILO output eye diagram with peak-to-peak jitter of 710fs, consistent with the ideal simulation result. Fig. 5.6 shows both the PSIJ versus decoupling caps sweeps shown in Chapter 3 and