Respin by Pin-Block Design and Floorplanning for Package-Board Codesign

Transcription

1 Fast Flip-Chip Pin-Out esignation Respin by Pin-Block esign and Floorplanning for Package-Board Codesign Ren-Jie Lee, Ming-Fang Lai and Hung-Ming Chen epartment of Electronics Engineering and SoC Research Center National Chiao Tung University, Hsinchu, Taiwan

2 Outline Introduction and Motivation Proposed design flow Constraints and Considerations Pin-Block esign and Floorplanning Experimental Results Conclusion R. J. Lee 2/26

3 Introduction Conventional esign Flow of Chip-Package-Board Codesign R. J. Lee 3/26

4 Motivation To speed up turn around time of chip- package-board codesign To account for practical experience and techniques in automatically designing interface To optimize package size R. J. Lee 4/26

5 Outline Introduction and Motivation Proposed design flow Constraints and Considerations Pin-Block esign and Floorplanning Experimental Results Conclusion R. J. Lee 5/26

6 Proposed esign Flow (Chip-Package-Board Codesign) R. J. Lee 6/26

7 Outline Introduction and Motivation Proposed design flow Constraints and Considerations Pin-Block esign and Floorplanning Experimental Results Conclusion R. J. Lee 7/26

8 Constraints and Considerations (1/5) A general layout of PCB board. 4 3 V SSN V N L tot di = NLtot dt : Simultaneous Switching Noise : Number of drivers switching : Equivalent inductance in current loop SSN IC Package R. J. Lee 8/26

9 Constraints and Considerations (2/5) ie-package-pcb cross-section view R. J. Lee 9/26

10 Constraints and Considerations (3/5) The routing pattern on PCB top layer (a) (b) and package bottom layer (c) (d). R. J. Lee 10/26

11 Constraints and Considerations (4/5) The row number of signal-pin with different package size. (ball pitch=1.0mm, net width=5 mil, net spacing = 5 mil, for four layer PCB board). Package size (mm) (Width x Height) Pin number (Row x Column) Row number of outer-pin (power-pin, ground-pin and signal-pin) Row number of outer-pin (signal-pin only) Max. Avg. Max. Avg x x x x x x x x (Top View) R. J. Lee 11/26

12 Constraints and Considerations (5/5) Return path pin Shielding pin I I C noise, C noise, C m m = m : dvdriver Cm dt Noise induced by mutual : Mutual capactance capacitor _N6 _N7 _N4 _P6 _N5 _P7 -I _P4 _P5 _N2 _N3 _N0 _P2 _N1 _P3 I _P0 _P1 R. J. Lee 12/26

13 Outline Introduction and Motivation Proposed design flow Constraints and Considerations Pin-Block esign and Floorplanning Experimental Results Conclusion R. J. Lee 13/26

14 Pin-Block esign and Floorplanning (1/6) Proposed pin pattern (1), (2), (3) _N6 _N7 _N4 _P6 _N5 _P7 _P4 _P5 (1) _N2 _N3 _N0 _P2 _N1 _P3 _P0 _P1 _N7 _P9 _N9 _N5 _P7 _P8 _N8 _P5 _P6 _N6 (2) _N2 _P4 _N4 _N0 _P2 _P3 _N3 _P0 _P1 _N1 _P9 _N9 _N7 _P8 _N8 _N6 _P7 _P5 _N5 _P6 (3) _P4 _N4 _N3 _P1 _N1 _N2 _P3 _P0 _N0 _P2 R. J. Lee 14/26

15 Pin-Block esign and Floorplanning (2/6) Proposed pin pattern (4), (5), (6) (4) (5) RST 0 RST 1 RST 2 RST 3 EN0 EN1 TIN 4 TIN 5 TIN 6 TIN 7 TIN 8 TIN 9 B 6 B 7 TIN 0 TIN 1 TIN 2 TIN 3 (6) B 0 B 1 B 2 B 3 B 4 B 5 TR AP2 TR AP3 TR AP4 TR AP5 TR AP6 TR AP7 SEL 0 SEL 1 SEL 2 SEL 3 TR AP0 TR AP1 R. J. Lee 15/26

16 Pin-Block esign and Floorplanning (3/6) Characteristics of signal-pin patterns. Applications, pin-designation efficiency, pin-to-pin crosstalk immunity, net balance,..., etc. Pattern (1) Application Signalpin NO. Pin-to-pin crosstalk immunity PCB board Net balance Package substrate Signal shielding on package substrate (Power/Ground) Top layer Bottom layer Top layer Bottom layer Top layer Bottom layer Power delivary aware Pindesignation efficiency ifferential signal 16 Excellent Good Good Good Good Ground Ground Without Not good Pattern (2) Pattern (3) Pattern (4) Pattern (5) ifferencial signal / Single-ended signal ifferencial signal / Single-ended signal ifferencial signal / Single-ended signal ifferencial signal / Single-ended signal 20 Good Good Good Good Not good Ground Ground Without Average 20 Good Not good Good Good Good Ground Ground Without Average 24 Excellent Not good Good Good Not good Ground Ground Without Good 24 Excellent Not good Good Good Not good Power Ground With Good Pattern (6) Single-ended signal 36 Not good Not good Not good Not good Not good None None With Excellent R. J. Lee 16/26

17 Pin-Block esign and Floorplanning (4/6) An example of pin configuration chart and pin block. Signal-pin name I/O buffer type I/O width (um) I/O height (um) Selected signal-pin pattern Group Side Order Power-pin name Power-pin NO. _P[0:7] AIO1XH0J A 10 _N[0:7] AIO1XH0J A 10 [0:15] BIO1XH0J B 8 TEST_IN[0:6] CIO1XH0J C 5 TEST_OUT[0:6] CIO1XH0J C 5 TRAP[0:6] CIO1XH1J C 5 R. J. Lee 17/26

18 Pin-Block esign and Floorplanning (5/6) Package size optimization E1 to E4 represent the width (height) of the excess or empty area in each side. w 33 w 32 w 31 E 2 h 3 A 33 A 32 A 31 A 22 h 22 A 33 A 32 A 31 A 31 E 3 h 41 A 41 F A 21 h 21 Floorplanning H min A 33 A 41 F A 22 E 4 h 42 A 42 w 4 A 11 A 12 h 1 w 2 A 42 A 11 A 12 A 21 A 21 w 11 w 12 E 1 W min E > 0, = 0, < 0, Excess Exact Empty (Side, Order) A 11 : (1, 1) A 12 : (1, 2) A 21 : (2, 1) A 22 : (2, 2) A 31 : (3, 1) A 32 : (3, 2) A 33 : (3, 3) A 41 : (4, 1) A 42 : (4, 2) R. J. Lee 18/26

19 Pin-Block esign and Floorplanning (6/6) Problem formulation to minimize package size R. J. Lee 19/26

20 Outline Introduction and Motivation Proposed design flow Constraints and Considerations Pin-Block esign and Floorplanning Experimental Results Conclusion R. J. Lee 20/26

21 Experimental Results (1/3) R. J. Lee 21/26

22 Experimental Results (2/3) Case (I): (b) Automated pin-out designation. (c) Manual pin-out designation R. J. Lee 22/26

23 Experimental Results (3/3) Case (II): (e) Automated pin-out designation. (f) Manual pin-out designation. R. J. Lee 23/26

24 Outline Introduction Motivation and proposed design flow Constraints and Considerations Pin-Block esign and Floorplanning Experimental Results Conclusion R. J. Lee 24/26

25 Conclusion We have designed six signal-pin patterns (template) for pin block construction in package design. We have proposed a near optimal approach to minimize package size. We automate this pin-out designation process for package-board codesign. R. J. Lee 25/26

26 R. J. Lee 26/26