Low-Frequency Noise in TFETs

Transcription

1 Lund University Master Thesis Low-Frequency Noise in TFETs Author: Markus Hellenbrand Supervisor: Prof. Lars-Erik Wernersson A thesis submitted in partial fulfilment of the requirements for the degree of Master of Science in the Nanoelectronics Group Electrical and Information Technology Faculty of Engineering, LTH May 30, 2015

2 The Road goes ever on and on Down from the door where it began. Now far ahead the Road has gone, And I must follow, if I can, Pursuing it with eager feet, Until it joins some larger way Where many paths and errands meet. And whither then? I cannot say. J. R. R. Tolkien, The Fellowship of the Ring

3 LUND UNIVERSITY Abstract Faculty of Engineering, LTH Electrical and Information Technology Master of Science Low-Frequency Noise in TFETs by Markus Hellenbrand Nanowire tunnel field-effect transistors (TFETs) were investigated by carrying out noise measurements and low-temperature DC measurements. The TFET tunnelling junction was realised by a GaSb/InAs heterojunction resulting in a broken band gap. TFET noise currents were measured at frequencies between 10 Hz and 1 khz. The results imply that noise in TFETs at the current state of development is dominated by generationrecombination processes caused by traps in the gate oxide. Trap densities between cm 3 ev 1 and cm 3 ev 1 were extracted from the noise measurements. The temperature-dependent DC measurements show that the TFETs off-current is sensitive to the temperature, with lower off-currents at lower temperatures. This indicates that it is not only the tunnelling junction which is governing the off-current. It is concluded that in the devices off-state electrons can still tunnel into the channel area through the broken band gap but require additional thermionic excitation over the bent channel conduction band to constitute a current.

4 Acknowledgements A father s goodness is higher than the mountains, a mother s goodness is deeper than the seas. As a physicist I briefly considered extending the mountains to the stars and the seas to outer space. However, while this would get even closer to the truth, I decided to leave this presumably Japanese proverb unaltered for the sake of poetry. And in the same way as my parents goodness reaches beyond all borders, so does my gratitude. I thank my parents for all their love, their patience and their faith in me, for their guidance and their advice, all of which I can always be sure of, no matter if I live right next door, if I move a thousand kilometres away or to the other side of the world. The same applies to my grandparents and to my siblings, Stefan and Anne, all of whom I am just as thankful to. Without you all I would not be where and who I am thank you. While my family has always given me the energy to reach further and beyond, there always has to be using J. R. R. Tolkien s words a road [that] goes ever on and on, down from the door where it began to direct this energy. The one who opened the door for me and showed me the road that I have travelled for the last eight months is Lars-Erik Wernersson. Always optimistic, enthusiastic about the ways of nature and inspiring the same enthusiasm in those working with him, Lars-Erik refined my general interest in solid state physics and showed me the huge world of the very small. Thank you, Lars-Erik, for opening the door for me and for letting me be part of your vision. Pursuing the large way of this thesis I found myself on many paths and errands. On all of them I always received great support. I thank Karl-Magnus Persson for introducing me to the tuneful world of noise, its measurement and evaluation and for helping me with all my questions, Erik Lind for helping me to make sense of all the noise, Elvedin Memisevic for letting me in on the secrets of cleanroom processing and Guntrade Roll for valuable feedback on this thesis, for helping me with all kinds of measurements, from low-temperature measurements to solving setup peculiarities. Especially for the latter I also thank Göran Jönsson and Martin Nilsson who know the measurement lab better than anyone else and often provided helpful assistance. Furthermore, I thank my second supervisor and programme coordinator Dan Hessman and apart from the concrete support mentioned above I thank the whole Nanoelectronics research group for a welcoming and harmonious environment from my first work day on. How exciting and fascinating a journey may be, every wanderer needs a place to rest a home to stay. For Lund to feel like home and for me to be able to recharge my batteries over and over again I thank my friends my dearest collective Dödsboets festkommité who made me feel at home in Lund more than anyone else, my dear fellow iii

5 Acknowledgements iv physicists and experts from related sciences here in Lund as well as back in Heidelberg, my dear friends from Domino who are a family in their own right and of course my oldest friends from Trier. Please forgive me if I do not name all of you here there are just so many of you whom I would like to thank. However, from this plea I have to make but two exceptions. First, I thank you, Sudha. You have been here with me the longest and will hopefully stay with me for several years to come. And second and in the end, looking back to the beginning and closing the circle, I thank my best friend Kevin. Thank you for always bringing me back in tune when I run the risk of losing the main melody among too many variations, for understanding even the most adventurous of my trains of thought and both most simply and most complex for your friendship. Thank you all. Markus Hellenbrand

6 Contents Abstract ii Acknowledgements iii Contents Acronyms Physical Constants Symbols v vii viii ix 1 Introduction 1 2 Theory Overview and Comparison with MOSFETs Modelling MOSFET Subthreshold Slope Wentzel-Kramers-Brillouin Approximation for Tunnelling D Tunnelling Junction Extension to Complete 1D Treatment and 3D TFET Subthreshold Slope TFET Transconductance Noise General Noise Properties White Noise: Thermal Noise and Shot Noise Generation-Recombination Noise and Number Fluctuations Random-Telegraph-Signal Noise Mobility Fluctuations /f Noise Overview TFET Fabrication 19 4 Experimental Setup General Setup and Measurement Process v

7 Contents vi 4.2 Probe Station Parameter Analyser Low-Noise Current Amplifier Lock-In Amplifier Cooling System Setup Issues Setup Overview Results and Analysis Reference Measurements on MOSFETs TFET DC Characteristics TFET Noise Measurements Frequency Sweeps Frequency Sweep Error Considerations Hz Measurements Hz Measurement Error Considerations Extraction of Gate Oxide Trap Densities Temperature-Dependent DC Measurements Conclusion and Outlook 47 Bibliography 50

8 Acronyms MOSFET TFET BTB WKB MOVPE EBL SEM ALD EOT PSD SMU GPIB DUT NDR RF Metal-Oxide-Semiconductor Field-Effect Transistor Tunnelling Field-Effect Transistor Band-To-Band Wentzel-Kramers-Brillouin Metal-Organic Vapour Phase Epitaxy Electron Beam Lithography Scanning Electron Microscope Atomic Layer Deposition Effective Oxide Thickness Power Spectral Density Source/Monitor Unit General Purpose Interface Bus Device Under Test Negative Differential Resistance Radio Frequency vii

9 Physical Constants Speed of Light c = m / s Elementary Charge q = C Boltzmann Constant k B = J / K Planck Constant h = Js Free Electron Mass m 0 = kg Vacuum Permittivity ɛ 0 = F / m viii

10 Symbols E F Fermi Level ev E V Valence Band Energy ev E C Conduction Band Energy ev I Current A V Voltage V D Diffusion Coefficient m 2 / s n(x) Carrier Concentration m 3 ; m 2 L Length m T Temperature K S Subthreshold Slope V / decade C Capacitance F k Wave Vector m 1 m T W KB Effective Mass WKB Tunnelling Probability E Energy ev J 1D 1D Current Density A / m E G Band Gap ev v Velocity m / s F (E) Fermi Distribution W Width m A Area m 2 N Number of Carriers t Time s S(f) Power Spectral Density A 2 / Hz; V 2 / Hz f Frequency Hz ix

11 Symbols x X 2 (t) Noise Power A 2 ; V 2 g m Transconductance S ɛ Permittivity F / m Ψ Potential V ξ Maximum Junction Electric Field V / m τ Time Constant s λ Tunnelling Attenuation Length m µ Mobility m 2 / Vs α H Hooge Parameter

12 Chapter 1 Introduction One of the most important elements of electronic devices omnipresent in our daily life is the transistor. Its most prominent realisation is the metal-oxide-semiconductor fieldeffect transistor (MOSFET). Over the last 50 years it has undergone continuous development, ever increasing speed and integration density. This improvement of transistors as the most basic processing unit was and is necessary to be able to cope with the ever increasing amount of information being processed on all levels of our society be it by trivial smartphone games, life support machines or global trade. However, the improvement of MOSFETs is facing increasing difficulties. The main developing factor has been geometrically scaling down MOSFETs and thus increasing their speed. One of the major problems of this approach is an also ever increasing energy dissipation. The energy dissipation of closely packed transistors has reached the limit of what can be dealt with. To be able to continue the improvement of transistors, their supply voltage has to be reduced to lower their energy dissipation [1]. For MOSFETs this is not possible because at a lower supply voltage the ratio between the on- and the off-current would be diminished unacceptably [2]. A quantitative measure for this problem is the subthreshold slope, which expresses the change in gate bias necessary to change the source-drain current by one order of magnitude. For MOSFETs the lower limit of the subthreshold slope is 60 mv / decade, which will be shown in the theory part. This limit comes about because the electron energies in the device contacts are governed by the Fermi-Dirac distribution. To constitute a current the electrons in a MOSFET are thermionically injected into the conducting channel. As the Fermi-Dirac distribution s high-energy tail is infinitely extended in energy and the MOSFET device design does not introduce an upper limit to the electron energies, there will always be electrons which can enter the channel even in the device s 1

13 Chapter 1. Introduction 2 off-state [3]. So, to reduce transistor supply voltages and thus the energy dissipation, new device physics has to be introduced, different from that of MOSFETs. Tunnel field-effect transistors (TFETs) are among the most promising devices to overcome the subthreshold slope limit of 60 mv / decade [2]. Instead of overcoming an energy barrier to enter the conducting channel, in a TFET the electrons tunnel through the barrier constituted by the semiconductor band gap [4]. The band structure MOSFET e - e - TFET Figure 1.1: Schematic depictions of band structures to illustrate the different working principles of MOSFETs and TFETs. which enables this mechanism also imposes an upper limit on the temperature-dependent electron energies in the source contact (Fig. 1.1). Thus, the subthreshold slope is not temperature-dependent anymore and can reach far below the MOSFET limit [5]. The TFETs examined in this thesis combine the tunnelling physics with another revolutionary transistor design approach utilising nanowires instead of the conventional planar or fin-based device design. Nanowires are epitaxially grown crystals, forming rods with only a few nanometres in diameter but a few hundred nanometres length. Using nanowires as the backbone of transistors brings about two huge advantages. First, nanowires allow a gate-all-around device design which enhances the electrostatic gate control and reduces parasitic effects during device operation [6][7]. Second, nanowires allow the immediate combination of materials with different crystallographic lattice constants because of the nanowires large surface-to-volume ratio. This ratio allows the crystal structures to relax from the strain induced at the different materials contact area where lattices of two different lattice constants meet [8]. This possibility to combine different materials is very advantageous for the realisation of TFETs [9]. To be able to create a tunnelling junction the energy band structure at the junction has to exhibit a certain form (Fig. 1.1) which to realise is much easier by using two different materials instead of only varied doping. The TFETs examined in this thesis use an GaSb/InAs combination resulting in a broken band gap at the material junction. This broken band gap constitutes a large tunnelling window for electrons to pass through in the on-state and thus leads to large on-currents [9]. As much as MOSFETs are facing the end of their development there is still a long way to go for TFETs until they can be used industrially. In this thesis the transport and material properties of TFETs are studied by the means of low-frequency noise

14 Chapter 1. Introduction 3 measurements and temperature-dependent DC measurements. The term noise refers to random and spontaneous fluctuations in an otherwise well-controlled signal. Noise stems from different sources, some of which will be examined in the theory part later on. These sources can be identified from characteristic measurement results. As noise occurs in all electrical devices noise measurements on TFETs can provide information about the mechanisms diminishing device operation. These mechanisms again indicate which parts of the measured TFETs require improvement. The temperature-dependent measurements can reveal in how far TFETs are really free from the temperature effects which limit the MOSFET off-currents. To approach the working principles of TFETs and to gain a basic understanding of noise mechanisms a brief theoretical background will be provided on both topics. To relate theory to practice an overview of the TFET fabrication process will be presented. After that, the different instruments of the measurement setup will be described, focussing on their intrinsic noise to secure the instruments usability for noise measurements. The measurement results will be presented and analysed afterwards, completed by conclusions and and outlook on future research.

15 Chapter 2 Theory 2.1 Overview and Comparison with MOSFETs First, the differences between MOSFET and TFET working principles will be elaborated on with the help of energy band structures. The main difference is shown in Fig. 2.1: In a MOSFET the current through the device is set by an energy barrier whose height determines the amount of carriers thermionically injected into the channel (Fig. 2.1(a)). In contrast to that in a TFET the carriers tunnel through a barrier to reach the channel [4] (Fig. 2.1(c)). (a) Source Channel Drain (b) E (c) Source Channel E F e - E C E V E F 0 1 p-gasb E F n-inas e - E V Figure 2.1: Figure from the introduction in more detail together with the electron energy distribution (Fermi-Dirac distribution). (a) For a MOSFET, electrons in the high-energy Fermi-Dirac tail (b) can overcome the channel energy barrier even in the transistor s off-state. (c) For a TFET this tail is cut off by the source valence band. E F, E C and E V denote the Fermi level, the conduction and the valence band, respectively. To switch a MOSFET between its on- and its off-state the energy barrier shown in Fig. 2.1(a) is raised or lowered so that more or less electrons can surpass it. The bands in the channel area of a TFET are raised and lowered as well but the on- and off-conditions are different from those in a MOSFET. In a TFET s on-state the channel conduction band has to be lowered below the source valence band to open a tunnelling window between source and channel. In the off-state this window is closed again when the channel conduction band is raised above the source valence band. The band structure 4

16 Chapter 2. Theory 5 necessary to achieve this behaviour (Fig. 2.1(c)) can be realised by using a semiconductor heterostructure to create the tunnelling junction. III-V material combinations have been found to be very versatile in band-engineering. As mentioned in the introduction the TFETs used during this thesis are based on GaSb and InAs which results in a band structure very similar to the one shown in Fig. 2.1(c) [9][10]. Comparing Figs. 2.1(a) and 2.1(c) reveals how the tunnelling mechanism brings about a smaller off-current than the thermionic carrier injection. While in a MOSFET there are always electrons in the high-energy Fermi-Dirac tail (Fig. 2.1(b)) which can overcome the energy barrier from the source side, in a TFET this tail is cut off by the source valence band. Instead, the off-current in an ideal TFET originates in direct source-to-drain tunnelling. But as the barrier for this process is quite thick (the whole channel region) a TFET s off-current is much smaller than that of a MOSFET. The MOSFETs lower limit of 60 mv / decade at room temperature for the subthreshold slope originates in this fact that the Fermi-Dirac high-energy tail reaches beyond the source-to-channel energy barrier. The 60 mv / decade limit prevents MOSFETs from being operated at lower voltages as lowering the drive voltage V DD, but maintaining the on-performance (V DD V T ), where V T is the threshold voltage, exponentially increases the off-current and thus the power dissipation (Fig. 2.2). As in TFETs the high-energy Fermi-Dirac tail is cut off, the subthreshold slope for a TFET is not dependent on the temperature anymore and can be smaller than 60 mv / decade. This allows operation at lower V DD than in MOSFETs [2] (Fig. 2.2). The downside of the tunnelling mechanism, log I DS I off V - V DD T S = 60 mv/dec VG Figure 2.2: By keeping a MOSFET s on-state performance and thus (V DD V T ) constant, the off-current is increased exponentially if the gate bias range is not changed as well [2]. To overcome this, devices with a lower subthreshold slope are required. however, is that it reduces the on-current, as the tunnelling probability exponentially depends on the barrier thickness and the band gap [11].

17 Chapter 2. Theory Modelling In the following the above-mentioned properties will be treated mathematically MOSFET Subthreshold Slope A MOSFET s subthreshold slope s temperature dependence follows directly from the MOSFET off-current I off which can be found in literature (e. g. [3]): I off = qzd n dn(x) dx = qzd n n(0) n(l). (2.1) L Here, q is the elementary charge, z the channel thickness, D n the charge carrier diffusion coefficient, n(x) the electron sheet density in the channel and L the channel length. The electron sheet density inserted into Eq. 2.1 can be derived with the help of Fig. 2.3 [3]. For a drain bias V DS > 3k B T/q this results in the off-state current I off = qzd n L ( ) n q(ψs Ψ B ) i exp k B T (2.2) with the temperature T, the intrinsic carrier concentration n i and Ψ S and Ψ B given in Fig As the subthreshold slope S gives the change in gate voltage necessary to change the off-current by one order of magnitude it is defined as [3] [ ] log(ioff ) 1 [ ] log(ioff ) Ψ 1 S S := =. (2.3) Ψ S This expression for S can be solved by using the relation = Ψ S + V OX = Ψ S + 2ɛS Ψ S qn D C OX (2.4) qψ S E FM Gate metal Gate oxide Channel qψ B E C E V E FS E i Figure 2.3: Energy diagram in proximity of the gate oxide [3]. Ψ B and the surface potential Ψ S are given as the differences between the intrinsic Fermi level E i and the semiconductor Fermi level after doping E FS and the difference between E i and the bent E i close to the gate oxide, respectively. E FM is the gate metal Fermi level, E C the semiconductor conduction band and E V the semiconductor valence band. describing the potentials in a structure like the one in Fig In Eq. 2.4 is the applied gate voltage, Ψ S the surface potential as before, V OX the part of the gate voltage dropping over the gate oxide, ɛ S the channel semiconductor permittivity, N D the channel doping and C OX the gate oxide capacitance. Inserting Eq. 2.4 into Eq. 2.3 S becomes S = ln(10) k BT q ( 1 + C ) D > 60 mv / decade (2.5) C OX

18 Chapter 2. Theory 7 with the channel depletion capacitance C D = ɛ S qn D /(2Ψ S ). This lower limit of 60 mv / decade at room temperature is the fundamental problem for MOSFETs energy-efficiency and can only be overcome by changing the physical basis of the devices Wentzel-Kramers-Brillouin Approximation for Tunnelling In band-to-band (BTB) tunnelling electrons tunnel from one energy band through the forbidden band gap into another energy band. This process of tunnelling through an energy barrier is well-known from quantum mechanics and constitutes the underlying physical principle governing the current through TFETs. To calculate this current the transmission coefficient for a tunnelling barrier is required which will be derived in the following. (a) A exp(-ikx) E 0 B exp(-ikx) (b) E CS E G+ qvr + (E C- E F S ) E VS E E F qvr x 1 x 2 E FC0 x Figure 2.4: Quantum-mechanical tunnelling process and its application to a triangular barrier in a TFET. (a) Electron wave function transmitted through a rectangular barrier. The ratio of the wave amplitudes squared gives the transmission coefficient. (b) Triangular approximation of a TFET s tunnelling junction energy barrier with applied gate bias. E FC0 indicates the channel Fermi level in relation to the channel conduction band before applying a gate bias. An electron wave function arriving at a rectangular energy barrier is partially reflected and partially transmitted depending on the wave function s energy and the energy barrier height. The transmission coefficient T can be calculated as T = B 2 /A 2 where A and B are the amplitudes of the incoming and the transmitted wave, respectively [12] (Fig. 2.4(a)). In the Wentzel-Kramers-Brillouin (WKB) approximation it is assumed that the barrier potential which the wave function is subjected to varies slowly on the order of the de Broglie wavelength. This allows to find a solution to the Schrödinger equation as in a situation where the potential is constant [13]. For a non-rectangular barrier the WKB approximation can be applied by dividing the barrier into small rectangular sections and multiplying all transmission coefficients. This results in [11] ( x2 ) T W KB = exp 2 k x dx x 1 (2.6)

19 Chapter 2. Theory 8 with the barrier boundary points x 1 and x 2 and the wave vector k x inside the barrier. From quantum mechanics k x inside the barrier can be calculated as k x (x) = 2m (E 0 (x) E), (2.7) where m is the effective mass, E 0 (x) the barrier potential and E the electron energy [12]. In a TFET structure as shown in Fig. 2.4(b) the barrier the electrons have to tunnel through can be approximated as triangular. For the barrier energy profile this results in E 0 (x) = E G +qv R +(E VS E F ) qξx with the band gap E G, the maximum electric field ξ = (E G + qv R + (E VS E F ))/(q(x 2 x 1 )) at the junction and x 1 < x < x 2. Calculating WKB transmission coefficient T W KB for this structure results in T 1D W KB = exp ( 4 2m E 3/2 G 3q ξ if one-dimensional (1D) transport is assumed [5]. ), (2.8) For the calculation of the current through a nanowire TFET in the following, 1D transport will be assumed as well, although this assumption is actually ahead of the current state of development. It will be discussed later on D Tunnelling Junction To be able to enter the channel from the source side the source electron energy has to be higher than the highest occupied state in the channel, so there will only be a current in the energy window set by the source and channel energy levels. Compared to a junction where the charge carriers do not have to tunnel through an energy barrier the current through a tunnelling junction is diminished by the tunnelling probability. Thus, the current through a tunnelling junction can be calculated as the sum of all electrons moving from source to channel in the respective energy window multiplied by the tunnelling coefficient (e. g. [14]): I = J 1D = 2 q v x (F S F C ) T W KB. (2.9) L k x Here L is the junction length (x 2 x 1 ) (Fig. 2.4(b)), k x is the wave vector in tunnelling direction, v x the group velocity and F S and F C are the Fermi-Dirac distributions governing the electron energies in the source and the channel, respectively. The Fermi-Dirac distributions are denoted by a capital F to avoid confusion with the frequency f later on. The factor 2 results from spin degeneracy. Assuming that the wave vectors are

20 Chapter 2. Theory 9 closely spaced the sum 2.9 can be converted to the integral I = 2q L L 1 E x (F S F C ) T W KB dk x, (2.10) 2π k x where the group velocity v x = 1/ E x / k x has been inserted and the pre-factor L/(2π) results from the transformation from a sum to an integral. As the group velocity v x contains a derivative of the energy E x with respect to k x the integral over k x becomes an integral over the energy. In the case of an n-doped channel where the Fermi level in equilibrium lies above the channel conduction band the energy window in which the electrons can tunnel through the junction is directly given by the voltage V R applied to the junction (Fig. 2.4(b)). Assuming this to be true in the given case and assuming (F S F C ) = 1 as an approximation the integral becomes I = 2q qvr 1 2π 0 T W KB de x = 2q2 h V R T W KB. (2.11) This result resembles that of the current in a 1D nanowire MOSFET in the quantum capacitance limit [14], which means that the oxide capacitance is much larger than the semiconductor capacitance. The result from Eq could be expected from calculating the TFET current in the same way as calculating a non-tunnelling device current and then multiplying it by an energy-independent factor accounting for the tunnelling as has been done here. Strictly, assuming (F S F C ) = 1 to arrive at the given result is only valid for a temperature T = 0 K and will be discussed in the following section Extension to Complete 1D Treatment and 3D For a complete derivation the integral 2.10 has to be carried out over the whole energy range with (F S F C ) remaining in the integral. With the thermal voltage V T = k B T/q the result for this is ( ( I = 2q2 1 h V T ln 1 + cosh V )) R T W KB, (2.12) 2 V T which yields a slightly reduced current as compared to Eq due to the smoothed out Fermi distributions at temperatures above zero. The derivation of this result can be found in [5]. At T = 0 K Eq simplifies to I = (2q 2 /h) V R T W KB again [5] which is consistent with the result above. For a nanowire to exhibit 1D transport characteristics the separation of the energy sub-bands due to confinement in radial direction should be much larger than k B T. As a simplification for an estimation the nanowire is assumed to have a square base area with the nanowire diameter as side length. For a situation like this the sub-band energy

21 Chapter 2. Theory 10 is known from quantum mechanics to be E = 2 π 2 2m ( p 2 W 2 y ) + q2 Wz 2 (2.13) with the sub-bands p and q and the confinement widths W y and W z in y- and z-direction, respectively [12]. The nanowire diameters were ca. 35 nm which results in a separation of E = 0.04 ev = 1.6 k B T between the first two sub-bands, so 1D transport is not really given. If the tunnelling current is treated in 3D instead the term exp( E /Ē) will appear in the tunnelling coefficient to attribute for the transverse-energy-states carriers diminishing influence on the tunnelling current. Here, E = 2 (k 2 y + k 2 z)/(2m ) is the transverse energy and Ē = (q ξ)/(2 2m E G ) [5]. The integral used for the calculation of the current from the charge carrier flux and the tunnelling coefficient will of course also include the transverse-energy states. Here, the derivation in the 1D case has been given preference to the 3D case to show the possibility and aim of future nanowire development TFET Subthreshold Slope From the current found in Eq a 1D TFET s subthreshold slope will be examined to point out one of the most important TFET advantages over MOSFETs. Summarising constants with a and b and writing the result from Eq as ( I = 2q2 h V R T W KB = av R ( ) T W KB ( ) = av R ( )exp b ) ξ( ) (cp. Eq. 2.8 for T W KB ) the subthreshold slope becomes [15] [ log(i) S = ] 1 [ 1 V R ( ) = ln(10) V R b ξ 2 ( ) (2.14) ] ξ( ) 1. (2.15) None of the terms in the equation above depends on the temperature which in contrast to MOSFETs allows TFETs to reach subthreshold slopes below 60 mv / decade TFET Transconductance For the evaluation of the noise measurements later on the transconductance g m will be used. It is defined as I DS /. With I DS from Eq. 2.11, this results in g m = 2q2 h T W KB, (2.16)

22 Chapter 2. Theory 11 as V R = V OX (Fig. 2.4(b)), where V OX is the part of the applied gate voltage that drops over the gate oxide. 2.3 Noise Up to now noise in TFETs has barely been studied [16][17][18]. Therefore, not much reference can be found regarding the topic. To achieve a basic understanding of noise properties nevertheless, a brief overview over noise in MOSFET devices will be given. The gated area of a TFET does not only consist of a tunnel junction but also of a channel adjacent to the junction. Although this channel does not limit the maximum current level it can still be assumed that the channel contributes to the devices noise behaviour in a similiar way as in a MOSFET, so studying MOSFET channel noise properties will also reveal information about TFET channel noise behaviour. Junction related noise properties are not covered in detail as they could not be experimentally examined so far. Furthermore, it will turn out that at room temperature the channel noise dominates the state-of-the-art TFETs noise behaviour. The following treatments are based on [19] General Noise Properties Electrical noise is a random and spontaneous fluctuation in an otherwise well-controlled electrical signal. For a current this can be expressed as I(t) = Ī + I(t), (2.17) where I(t) is the total signal, Ī is the well-controlled part of the signal and I(t) the fluctuation referred to as noise. The average current through a conductor of length L can be expressed as Ī = qnv d A = qnv d /L, (2.18) where q is the electron charge, n the free charge carrier density, v d the drift velocity, A the conductor cross section, N the total number of free charge carriers and L the length of the conductor. For a homogeneous conductor subjected to a uniform electric field the average drift velocity is the same for all carriers. Due to noise, however, both N and v d

23 Chapter 2. Theory 12 for single carriers can deviate from their average value: N(t) = N + N(t) v i (t) = v i + v i (t). (2.19) Using 2.18 for the noise current I(t) this leads to I(t) = q L v d N(t) + q L N v i (t). (2.20) i=1 In this sum the first term expresses number fluctuations and the second term expresses velocity fluctuations which can be related to mobility fluctuations via v i = µ i E with the individual carrier mobilities µ i and the applied electric field E. A measure often used to describe noise is the power spectral density S(f) which gives the power of a signal distributed over its frequency components. Integrated over the whole frequency range the power spectral density (PSD) gives the total signal power X 2 (t): 0 S x (f)df = X 2 1 T (t) = lim X 2 (t)dt. (2.21) T T White Noise: Thermal Noise and Shot Noise If the PSD introduced in the section above is frequency-independent (Fig. 2.5) the underlying noise is referred to as white noise. The dominant part of white noise originates in the thermic motion of charge carriers present in any material above absolute zero. Due to constant scattering of charge carriers their randomised velocities can introduce small net currents in varying directions. For a resistor with resistance R at temperature T the PSD for its thermal noise current is S I = 4k BT R, (2.22) where k B is the Boltzmann constant. This type of noise is also referred to as Johnson- Nyquist noise after its discoverers John Bertrand Johnson and Harry Nyquist. Another type of white noise is the so-called shot noise, which originates in the discrete nature of an electric charge facing an energy barrier. Electric current depends on the number of carriers, which if treated as sum of discrete particles shows Poisson fluctuations. Thus, shot noise requires a current to flow and its noise current follows the PSD with the electric charge q and the current I. S I = 2qI (2.23)

24 Chapter 2. Theory 13 S I [A 2 / Hz] f [Hz] Figure 2.5: White noise is constant in frequency Generation-Recombination Noise and Number Fluctuations The semiconductor and gate oxide crystal structures constituting most parts of MOS devices are not perfect but exhibit crystallographic defects ( traps ) which can trap and release charge carriers (Fig. 2.6). This trapping and the subsequent de-trapping can introduce number fluctuations in a MOS device s current. If the traps energy levels are within a few k B T of the Fermi level these number fluctuations will affect the device s current as noise, which is referred to as generationrecombination (g-r) noise due to the underlying physical principle. In MOS structures the devices part which is most prone to the above-mentioned defects is the channel area where the channel semiconductor crystal is in contact with the gate oxide. A widely accepted model explaining these trapping and de-trapping processes by tunnelling into and out of the traps was established by A. L. McWorther [20]. The corresponding theory is summarised very briefly in the following. Gate oxide Filled trap Empty trap Channel Figure 2.6: Schematic illustration of traps in the gate oxide. Crystallographic defects can trap and release charge carriers, which leads to number fluctuations in the current. White arrows indicate two possible tunnelling paths. The g-r noise S t generated by a single crystallographic defect trapping and releasing charge carriers can be expressed as S t = q2 W 2 L 2 4 N 2 t τ 1 + (2πfτ) 2 (2.24)

25 Chapter 2. Theory 14 with the elementary charge q, the channel width W, the channel length L, the variance in the number of trapped charges N t, the trapping time constant τ and the trapping frequency f. This PSD has a Lorentzian shape (Fig. 2.7). The probability of a trap being occupied or not is given by the Fermi-Dirac distribution F (E) = exp ( E EF k B T ) (2.25) with the energy E and the Fermi energy E F. The variance ( N t ) 2 for the Fermi-Dirac distribution is given by N 2 t = F (E)(1 F (E)). (2.26) In the next step to evaluate Eq a trap density n t (x, y, z, E) in the gate oxide is assumed to take into consideration contributions from more than one trap. With this it is possible to integrate over the whole channel to calculate its total noise PSD S C : q2 S C = 4 W 2 L 2 EC W L tk E V where t k is the high-k material thickness τ n t F (E)(1 F (E)) dxdydzde, (2.27) 1 + (2πfτ) 2 Due to the properties of the Fermi-Dirac distribution, F (E)(1 F (E)) only constitutes a sharp peak around the quasi-fermi level as F (E)(1 F (E)) = k B T df (E)/dE. If additionally n t is assumed to be constant in energy and in space (which will be discussed later on) the above integral simplifies to S C = 4 q2 k B T tk W L n t 0 τ dz. (2.28) 1 + (2πfτ) 2 In Eq dz remains as spatial integrand as τ depends on z (cp. 2.29). An essential part of the McWorther model is the assumption that charge carriers are trapped and released by tunneling. The time constant determining how long carriers remain trapped is given as τ = τ 0 (E)e z/λ, (2.29) where z is the depth into the gate oxide measured from the interface to the channel, τ 0 (E) is often taken as a constant s, and λ is the material dependent tunnelling attenuation length, which is given by the WKB theory: λ = ( 4π ) 1 2m h Φ B. (2.30)

26 Chapter 2. Theory 15 Here, m is the effective electron mass in the gate oxide and Φ B is the barrier height towards the gate oxide. For the given material system consisting of an Al 2 O 3 layer adjacent to an InAs channel (cp. Sec. 3) the values m = 0.23 m 0 with the electron rest mass m 0 and Φ B = 2.3 ev can be taken from [21]. This results in λ = 0.13 nm. With λ known, τ = 1/(2πf) and Eq the depth z of the traps contributing to noise at certain frequencies f can be calculated: ( ) 1 z = λ ln. (2.31) 2πfτ 0 For the frequency range of 10 Hz to 1 khz measured later on this results in values for z between 1.9 nm and 2.5 nm. If the traps are closer to or further away from the interface than this, they respond too quickly or too slowly, respectively, to contribute to g-r noise in the given frequency range. Inserting 2.29 and the values obtained for f, τ and λ into 2.28 the integral can be evaluated as [19] S C = q2 kt λn t fw L. (2.32) Earlier, the trap density n t in the high-k material was assumed to be constant in energy and space. This is usually not the case [22] and will affect 2.32 by changing the 1/f behaviour to a 1/f γ behaviour. It was discovered that γ is smaller than 1 if the trap density increases towards the channel interface and larger than 1 in the opposite case. When using the findings derived above for evaluating measurements later on the relations S I = S Vfb g 2 m and S Vfb = S C /C 2 ox (2.33) are helpful, where S C is the g-r noise power that was derived above. In contrast to the gate oxide noise power S C, S I is the whole device s noise current power. When S C is divided by the gate oxide capacitance C ox squared, this yields the flat-band voltage noise power S Vfb which again yields the noise current power S I if multiplied by the transconductance g m squared: S I = q2 k B T λn t f γ W LCox 2 gm. 2 (2.34) The possible deviation from a 1/f behaviour was taken into account in the last equation. The quantity that will actually be measured in the experimental part later on is the noise current I N. The noise current power S I is this noise current squared. The

27 Chapter 2. Theory 16 term power is used although it is not a real physical power. Conventionally, S I is normalised with the source-drain current I DS squared and S I /IDS 2 is plotted against I DS to compare the measured noise to the transconductance behaviour (g m /I DS ) 2. If both follow a similar behaviour this is an indication for number fluctuations in the measured device. Furthermore, measuring S I and g m allows to extract the trap density n t from Eq. 2.34: n t = f γ W LCoxS 2 I q 2 k B T gm 2. (2.35) Random-Telegraph-Signal Noise A special form of g-r noise is Random-Telegraph-Signal (RTS) noise. It can occur when in g-r processes only a few traps are involved. RTS noise can be observed in the time domain when the current switches between two or more discrete levels. If RTS noise is observed, this often hints to a bottleneck in a device as it is assumed that for RTS noise a single trap governs the flow of a large number of carriers rather than many carriers being involved in trapping and de-trapping. The power spectral density for a current switching between two levels differing by I was found to be S I (f) = 4( I) 2 (τ l + τ h )[( 1 τ l + 1 τ h ) 2 + (2πf) 2 ]. (2.36) τ l and τ h are the Poisson distributed durations in the lower and the higher current state respectively. Similar to g-r noise the RTS noise PSD has a Lorentzian shape in the frequency domain Mobility Fluctuations At the beginning of this chapter the overall current fluctuations were separated into number fluctuations and mobility fluctuations. In contrast to the former a theory of which was treated in chapter there is no widely accepted explanation for the latter. Only an empiric model by F. N. Hooge [23] which is given by S I I 2 DS = α H fn = qα H fw LQ i, (2.37)

28 Chapter 2. Theory 17 is often used to describe noise from mobility fluctuations. In Eq S I is the noise current power, I DS the source-drain current, α H the numerical and material-dependent Hooge parameter, f the frequency, W and L channel width and length, respectively, N the total amount of charge carriers in the channel and Q i the charge in the channel. To obtain an equation valid for all regions of operation and again an expression that will allow to identify mobility fluctuations in the measured data later on a nonuniform charge distribution Q i (x) in the channel has to be assumed. With this and I DS = W µ eff Q i dv/dx, Eq can be expressed as S I I 2 DS = qα H 1 fw L L L 0 dx Q i (x) = qα VDS H W µ eff fw L 2 dv = qα Hµ eff V DS 0 I DS fl 2, (2.38) I DS where µ eff is the effective carrier mobility in the channel and V DS is the source-drain voltage. Above saturation V DS has to be replaced by the saturation voltage V DS, sat. Similar to the expression for number fluctuations (Eq. 2.34) this last expression (Eq. 2.38) is often used to identify mobility fluctuations in measured data by plotting S I /IDS 2 versus the drain current I DS and comparing it to a 1/I DS graph /f Noise The main parts of chapter 2, and 2.3.5, both served as a basis for this thesis main topic: 1/f noise. This type of noise, also called flicker noise or pink noise, occurs in almost all electronic devices. A consequence of the 1/f PSD of this type of noise is that it is mostly visible at lower frequencies. In fact, 1/f noise occurs at all frequencies but the frequency dependence causes the PSD at higher frequencies to be overshadowed by white noise, its PSD being constant over all frequencies. The frequency where the 1/f PSD drops below the white noise PSD is called corner frequency. In MOS devices it is assumed that 1/f noise originates in exactly the two contributions already mentioned in and treated in more detail in and 2.3.5: number fluctuations and mobility fluctuations. Both eqs and 2.38 as the main results of their respective section show the 1/f behaviour. While this twofold composition of number and mobility fluctuations was shown in planar [24] as well as in nanowire MOSFETs [25] only a few noise inspections on TFETs have been carried out so far [17][18]. As mentioned before, from comparison of TFET structures to MOSFET structures, it can be assumed that the contribution of number fluctuations to 1/f noise will also appear in TFET measurements as there is still a channel area similar to that in a MOSFET adjacent to the tunnel junction. For mobility

29 Chapter 2. Theory 18 fluctuations in nanowire TFETs an assumption like this is not so straight forward as there is an ungated part of the nanowire where the electric field is not well-controlled (cp. Sec. 3). This might lead to possible mobility fluctuations being balanced by an adapting electric field in this area / f S I [A 2 / Hz] f [Hz] Figure 2.7: Lorentzian noise PSDs accordings to Eq with different time constants add up to 1/f behaviour Overview As a brief overview the table below summarises the noise characteristics most important for the later measurement evaluations. Noise Characteristic Behaviour Normalised PSD Behaviour at Fixed Frequency White Noise Constant in Frequency 1/IDS 2 RTS Noise Distinct Current Levels in Time Domain G-R Noise Adds up to 1/f Noise (g m /I DS ) 2 Mobility Fluctuations Adds up to 1/f Noise 1/I DS Table 2.1: Overview over different kinds of noise.

30 Chapter 3 TFET Fabrication In this chapter the different steps necessary to fabricate a vertical nanowire TFET are briefly described. As this thesis does not focus on processing, the description will be mostly qualitative. The scanning electron microscope (SEM) images in this section show devices different from those actually used for noise measurements, as the latter had already been fabricated before. The fabrication process is the same, however. It was published in [26]. Nanowire Growth A device can only be as good as the material it is made of. Therefore the growth of the nanowires making up the TFETs later on is essential. The nanowires consist of three parts: A highly n-doped (n D = cm 3 ) InAs stem for the drain side, an intermediate intrinsic (un-doped) InAs part for the gated area and a highly p-doped (n A = cm 3 ) GaSb top part for the source side. For n-doping tetraethyltin (TESn) was used and for p-doping it was diethylzinc (DEZn). The tunnelling governing the transistor s characteristic behaviour is supposed to take place at the junction between GaSb and the intrinsic InAs part. This intrinsic part of the nanowire is required because a high doping throughout the whole nanowire would diminish gate control. Although the gated part of the nanowires is supposed to be intrinsic it was still doped to approximately n D = cm 3 [26] (in contrast to the intrinsic InAs carrier concentration of n i = cm 3 ) as some TESn remains inside the growth chamber after switching off the doping gas. For the growing of InAs nanowires an InAs substrate was required. Instead of using a pure InAs substrate a Si wafer was overgrown with an InAs buffer layer by metalorganic vapour phase epitaxy (MOVPE). In this process metal-organic precursor gases are flooded over the Si substrate. They react in the gas phase as well as on the surface where they finally form a crystalline InAs layer. 19

31 Chapter 3. TFET Fabrication 20 Apart from the InAs buffer layer, Au seed particles are necessary to grow the nanowires. These were distributed over the InAs surface by an electron beam lithography (EBL) defined lift-off process. Heaters Reactor chamber Sample Figure 3.1: Schematic depiction of the growth reactor. Metal-organic precursor gases are run over the gold-particle-covered buffer layer. The nanowires grow under the Au particles pushing them upwards. The actual nanowire growth was carried out by the same process as the buffer layer growth before, only adding another precursor gas (TESn) to add Sn as n-dopant. In and As from the precursor gases diffuse into the gold particles and crystallise below them as InAs once the gold particles are saturated. This pushes the gold particles upwards. After a certain time the doping precursor gas was switched off to obtain the un-doped InAs part in the nanowire. To obtain the p-doped (by the use of DEZn to implant Zn) GaSb part of the nanowires all gases were changed again after some time. A schematic depiction of the growth reactor is shown in Fig As can be seen in Fig. 3.2 the GaSb part of the nanowires has a larger diameter than the InAs part. Incorporating Sb into the Au particle increases the solubility of group III materials in gold. This changes the Au particle composition and with it the nanowire diameter [9]. Digital Etching to Remove Growth Residues Observations have shown that during the growth of the GaSb part there is also an GaInSb shell formed around the InAs part of the nanowires. In the past this diminished the gate control over the transistors once they were completed. Since this problem was identified, the shell is removed by digital etching after the nanowire growth. Furthermore, digital etching can be used to decrease the diameter of the InAs section of the nanowires which enhances the electrostatic gate control [7]. In digital etching the sample surface is first oxidised in a plasma asher and afterwards the oxide layer is removed by an acid. This two-step process is repeated until the intended decrease in nanowire thickness is achieved. Deposition of a High-k Material as Gate Oxide A crucial part for every MOS transistor is the gate oxide. Its permittivity should be as

32 Chapter 3. TFET Fabrication 21 (a) 460 nm 240 nm { { p-gasb i-inas n-inas (b) Figure 3.2: Nanowires grown from an InAs substrate. The GaSb top part has a larger diameter than the InAs part due to the Au particle increasing in diameter in the later growth step. At this process stage the unwanted GaInSb shell around the nanowires was already removed by digital etching. (a) Schematic illustration of the nanowires after growth and digital etching. (b) Nanowire SEM image after growth. high as possible to achieve a gate control over the channel as far as possible. Because of their high permittivity κ the materials used are referred to as high-k materials. Here, an Al 2 O 3 /HfO 2 bilayer was used. Both materials were deposited by atomic layer deposition (ALD). ALD works in a similar way as the buffer layer growth except that the precursor gases are flooded over the sample alternatingly so that the reaction only occurs at the sample and nanowire surface. This forms one closed atomic layer at a time. The thicknesses of the high-k materials were approximately 1 nm Al 2 O 3 followed by 5 nm HfO 2, which corresponds to an effective oxide thickness (EOT) of 1.4 nm [26]. For the most recent samples an additional surface treatment right before the ALD step was introduced. This step is supposed to counteract the degradation of the surface which begins immediately after the growth of the nanowires just because they are subjected to the air in the laboratory. The success of the additional surface treatment became visible both in the TFETs switching behaviour and in the noise measurements. Etching of Mesa Structures to Avoid Current Diffusion So far all the nanowires were connected through the highly n-doped InAs buffer layer. To isolate single transistors later on, mesa structures defined by UV lithography were (a) High-k material Spacer 1 (b) Figure 3.3: Both the high-k material and the spacer between drain and gate were applied. Mesa structures were etched in between these two steps. The resulting trenches were filled by the non-conductive spacer material. (a) Schematic illustration after applying the high-k material and the first spacer. (b) SEM image of nanowires sticking out of the spacer.

33 Chapter 3. TFET Fabrication 22 etched through both the high-k material and the InAs layer (Fig. 3.3). As the Si substrate is not doped it is by far less conductive than the doped InAs buffer layer, so the trenches reaching down to the Si substrate prevent the flowing of currents. DC and noise measurements can be carried out without these mesa structures but for radio frequency (RF) measurements they are indispensable. Definition of Spacers Between Contacts To isolate the transistors drain contact from the gate contact a non-conductive spacer was applied on top of the drain (Fig 3.3). In contrast to the gate oxide, the material used for the spacer layer should have a permittivity as low as possible to keep parasitic capacitances as low as possible. In the current fabrication process an organic UV resist is used. It is one of the main challenges of processing to replace this material as it is not very robust. It absorbs humidity even after the processing of the transistors has been completed and it can trap charges during device operation. Both effects alter the device behaviour and thus constitute a reliability problem. The spacer thickness was defined by simply covering the whole sample with the resist and then slowly etching back until the desired thickness was achieved. This processing step was carried out both before applying the gate metal and afterwards to isolate the drain from the gate and the gate from the source, respectively. Deposition of the Gate Metal After the application of the first spacer the gate metal was sputtered on. In sputtering, a target is bombarded with a sputtering gas inside a vacuum chamber. The sputtering gas physically releases atoms from the target so that these released atoms diffuse towards the sample, and cover its surface with an amorphous metal layer. Here, the whole sample surface as well as the part of the nanowires sticking out of the spacer were covered in tungsten. As it was only supposed to cover the part of the transistor that is to be gated, the tungsten had to be etched from the top of the nanowires. This was achieved in a (b) (a) W gate Figure 3.4: The gate metal W was applied on top of the first spacer. The gate length was defined by applying and then etching a resist. The gate pads were defined by UV lithography. (a) Schematic illustration after definition of the gate length and the pads. (b) SEM image after the definition of the gate length, but before the definiton of the gate pads.

34 Chapter 3. TFET Fabrication 23 similar way as the definition of the spacer thickness before. The metal-covered surface was covered by a resist which was etched back afterwards so that in the end it only covered the part of the nanowire where the tungsten was supposed to remain. The rest of the metal, now sticking out of the resist, was etched away. Besides the gate length also the gate contact pads had to be defined, which was achieved by a UV lithography process (Fig. 3.4). Etching Via Holes to Contact Gate and Drain To be able to access all device contacts, via holes were etched through the spacer layers. The via holes were defined by UV lithography and etched in two similar steps (Fig. 3.5). (a) (b) Figure 3.5: Via holes were etched through the spacer resists to be able to contact drain and gate. To be able to contact the source the high-k material covering the top part of the nanowires was also etched. (a) Schematic illustration after etching via holes to contact drain and gate and after etching the high-k material from the top of the nanowires. (b) SEM image after etching the high-k material from the top of the nanowires but before etching via holes. Removal of the High-k Material From the Drain Area After the previous steps, the top part of the nanowires and the bottom of the via holes were still covered by high-k material which had to be removed before the contacts could be applied. This was again achieved by etching (Fig. 3.5). Special care had to be taken during this step as the etchant currently used also attacks the GaSb underneath the high-k material, so the etching time was crucial. Deposition of Contact Metals In the second but last step all contacts were covered by metal. The contacts consist of three layers: Ni to achieve a good contact to InAs and GaSb followed by W as a diffusion barrier and finally Au to achieve a good contact in a later measurement setup. All metals were applied by sputtering. This process filled up the via holes and covered the whole sample surface. Definition of Contact Pads In the last step the contacts were separated by etching the metal in between the UV

35 Chapter 3. TFET Fabrication (a) 24 (b) Figure 3.6: In the final processing step the contact metals were applied and the contact pads were defined by UV lithography. (a) Schematic illustration of a finished device. (b) Light microscope image of the contact pads after the completed processing. In this image the contact pads show some small cracks, which do not affect the measurement, however. The green rectangle indicates a single transistor. The finger reaching in from the top is the gate contact, the one reaching in from the bottom is the source contact and the large pads on both sides are the drain contacts. Close to where the contact fingers meet, the via holes and the nanowire arrays are visible as framed squares / circles and as a dark square, respectively. lithography defined contact pads. The result can be seen in Fig. 3.6 where a green rectangle in Fig. 3.6(b) indicates a single transistor. On one sample there are approximately 200 TFETs; not all of them are working due to processing-related non-uniformities. Sample Overview Noise and DC measurements were carried out on three different samples. The main differences between the samples were their age which can deteriorate the behaviour of the devices and the additional surface treatment immediately before the ALD step only introduced for the third sample. Table 3.1 below summarises these differences. To make the effect of the additional surface treatment clear, typical subthreshold slopes for the different samples are added in the table. Another effect of the additional surface treatment besides the improved subthreshold slope will become obvious during the analysis of the noise measurements later on (Sec. 5.2). Sample Number Wires Grown on Surface Treatment Before ALD Subthreshold Slope [mv / decade] No No Yes Table 3.1: Overview over measured samples.

36 Chapter 4 Experimental Setup 4.1 General Setup and Measurement Process The aims of this thesis were measuring noise and DC properties of TFETs at different temperatures. As MOSFET noise behaviour is well investigated reference measurements on MOSFETs were carried out to verify if it is possible to use the setup for noise measurements. Concerning the DC properties both the transfer and the output characteristics were measured. For the first one the source current was measured while the gate bias was swept at a constant drain-to-source voltage and for the second one the source current was measured while the drain-to-source voltage was swept for several fixed gate biases. For the DC measurements only the parameter analyser shown in Fig. 4.1 was required as it can act both as a voltage source as well as as a volt- and amperemeter (Fig. 4.2). The measurement data were recorded with a LabView programme controlling the parameter analyser using a General Purpose Interface Bus (GPIB). Parameter analyser Current amplifier Laptop Lock-in amplifier Figure 4.1: Schematic depiction of the measurement setup. 25

37 Chapter 4. Experimental Setup 26 When examining the TFETs noise behaviour two kinds of measurements were carried out as well. In one of them the noise current was measured while logarithmically sweeping the lock-in amplifier frequency from 10 Hz to 1 khz. At each frequency set in this way the device s source current was measured 55 times (set by the measurement programme). The average of these 55 measurements constitutes the data point for the given frequency. This measurement process was repeated for different gate biases. In the second measurement the noise current was measured at a fixed lock-in frequency of 10 Hz to possibly identify noise behaviour following (g m /I DS ) 2 or 1/I DS as explained in secs and 2.3.5, respectively. For these measurements at 10 Hz the 55-fold current measurement explained above was repeated ten times at each gate bias so that the average of these ten measurements constituted one data point. Both kinds of measurements were carried out for several different gate biases from considerably below to considerably above the transistors threshold voltage. In both measurements the complete signal from the device under test (DUT) was amplified by a low-noise current amplifier. To only measure the noise current the DC part of the measured signal was removed by the lock-in amplifier, which selects a very narrow frequency range in any signal. The remaining AC signal was the noise from the device. From the lock-in amplifier the signal was forwarded to a laptop via a GPIB interface where it was recorded by a LabView programme. For a complete measurement (at room temperature) first a transistor s transfer characteristics were measured to see if the device was working. Then the noise measurement was carried out as described above. Afterwards the transfer characteristics were measured again to capture the change in the device behaviour when stressing the transistor during the noise measurement. After this the output characteristics were measured. In the following all measurement instruments used are briefly described including their expected intrinsic noise level to show that it is possible to conduct noise measurements with this setup. To be able to plan the measurement setup the TFETs noise current was roughly estimated to be in the order of 1 % of the device current. This estimation takes MOSFETs noise currents as a basis and results in approximately 1 na for the TFETs. 4.2 Probe Station To bias the transistors they were contacted in a probe station. A Cascade 11000B or a Cascade Microtech / New Wave Research Alessi REL-4800 Micro Probe Station was used. Both are equipped with micro-manipulators to accurately place the contact needles on the transistor pads.

38 Chapter 4. Experimental Setup 27 Both probe stations exhibited contact and wire resistances of a few Ohm which amounts to a white noise contribution far below the expected intrinsic transistor noise level. 4.3 Parameter Analyser The parameter analyser schematically shown in Fig. 4.1 acted as both the contacts voltage sources and as their current monitors in DC measurements. During noise measurements the source current was not measured by the parameter analyser but by the low-noise current amplifier. The two parameter analysers used during this thesis were a Keithley 4200 SCS and an HP4195. Both instruments provide source / monitor units (SMUs) which can be used as depicted in Fig Voltage source - + Amperemeter A The DC accuracy for the Keithley 4200 SCS amounts to ±0.02%rdg µv for the voltage source, ±0.06%rdg fa for the amperemeter for the current range in the transistor s off-state and ±0.04%rdg na for the current range in the transistor s on-state [28]. GND Current source V Voltmeter SMU OUT For the HP4195 the DC voltage accuracy V Nex amounts to ±0.12% + 5 mv [29]. The current measurement accuracy was not to be found Figure 4.2: Simplified circuit diagram showing the different operating possibilities for the parameter analyser [27]. in the instrument manual so it was estimated to be ±5 in the last digit displayed. As the transistors gate contacts are biased by the parameter analyser as DC source its voltage inaccuracy introduces an extrinsic source-drain current noise I Nex transistors transconductances g m : proportional to the I Nex = g m V Nex. (4.1) Calculating this extrinsic noise with the given DC source inaccuracy results in an extrinsic current noise larger than the expected intrinsic transistor noise which would render the HP4195 unusable for noise measurements. However, examining the DC source with an oscilloscope showed that the DC source noise signal has a value of 1.2 mv peakto-peak instead of the maximum inaccuracy given in the instrument manual. Further measuring only the DC source s voltage noise with the lock-in amplifier, calculating the

39 Chapter 4. Experimental Setup 28 resulting extrinsic noise current I Nex according to Eq. 4.1 and comparing it to the transistors measured intrinsic noise showed that the extrinsic noise level is approximately two orders of magnitude smaller than the intrinsic noise level (Fig. 4.3). Thus, the HP4195 can be used as voltage source for noise measurements I N [A / Hz] I N Transistor Parameter analyser V N * g m [V] Figure 4.3: Comparison between intrinsic transistor noise (blue) and extrinsic noise (red) introduced by the voltage source inaccuracy affecting the transistor s gate contact for a TFET. 4.4 Low-Noise Current Amplifier As the currents measured could be very small ( 10 pa 1 µa) a current amplifier was used to facilitate measuring the even smaller noise signal. In this setup an SR570 low-noise current amplifier was used. It can be operated on a battery instead of line voltage which is advantageous for any kind of frequency-dependent measurements as it suppresses voltage spikes at the line voltage frequency and its multiples. Furthermore the amplifier worked as a transimpedance amplifier converting the input current into an output voltage which was then forwarded to the lock-in amplifier. The amplifier s internal noise depends on the sensitivity setting. For the lowest sensitivity (meaning the lowest amplification) that was used (10 6 V/A) the noise level is given as 600 fa for a frequency-independent contribution but can reach up to 800 fa if the intrinsic 1/f-noise is considered [30]. The upper (meaning the highest amplification) limit for the amplifier s sensitivity was not the highest instrument setting but the available bandwidth as it decreases with increasing amplifier sensitivity. In the case of the

40 Chapter 4. Experimental Setup 29 measurements being carried out at a fixed frequency of 10 Hz sometimes also the signal s DC component set a lower limit to the sensitivity as the amplified DC signal could overload the current amplifier s output. Even the highest instrument noise of 800 fa does not reach into the expected intrinsic noise range of the measured devices. 4.5 Lock-In Amplifier In a lock-in amplifier a very narrow band-pass filter is applied to the incoming signal, only measuring the passed AC amplitude. In this way the measured signal s DC component was removed so that only the noise current was measured. The lock-in amplifier used was an SR830 whose internal noise is given as 6 nv / Hz [31]. Compared to the measured noise voltage amplitude of usually at least 10 mv after amplification the lock-in amplifier s internal noise is negligible. 4.6 Cooling System For the low-temperature DC measurements the TFET samples were contacted in a dedicated cryo probe station. The voltages and currents were controlled and measured by the HP4195 parameter analyser described above. The cryo probe station used was a LakeShore CRX-6.5K model with a standard temperature range between < 10 K and 350 K and a vacuum pressure of 10 6 Torr at base temperature. Liquid Helium is used to cool down the system and the probe station is equipped with a sample holder and a radiation shield around the sample holder. The only noise sources from the cryo probe station were the wire and tip resistances which added up to a few Ohm. 4.7 Setup Issues Changing the probe station and the parameter analyser in the course of the measurements involved changing the laboratory. This constituted a major setup challenge for the continuation of the measurements. First, almost all devices on one sample broke in one single incident and later on almost all DUTs individually broke randomly and without apparent reason, usually showing a gate-oxide-breakthrough. For the first issue, where almost a whole sample was destroyed at once it became obvious that switching the probe station s microscope light causes a voltage spike in the sample large enough to

41 Chapter 4. Experimental Setup 30 destroy its devices. This was solved by interrupting the light path instead of switching the light. For the later incidents, where almost during every measurement the DUT was destroyed after some time the problem at least partly originated in the laboratory s grounding: The breaking of devices seemed to be correlated to other laboratory users switching instruments or the light in the laboratory. However, not every switching event in the laboratory causes a voltage spike in the measurement setup as could be observed by examining the lines connecting the voltage source and the probe station with an oscilloscope. A solution which at least reduced the problem was to decouple all instruments involved in the measurements from the laboratory earth with the help of a transformer and to connect their grounds to another earth than that used for the rest of the laboratory. This improved the situation but did not eliminate it completely. As this measure did not completely solve the problem and devices continued to break during measurements though less often the connexions between the parameter analyser and the probe station were examined more closely to possibly identify voltage spikes originating from either one of the measurement instruments or from the changed grounding. Spikes large enough to destroy the measured transistors could not be detected despite monitoring the signal for several hours and randomly switching the light and other instruments in the laboratory. However, not being able to identify any spikes during this observation could have been bad luck as it is possible that just during this time none of the events which could have destroyed a transistor occurred. This issue definitely has to be solved before continuing noise measurements with this setup. 4.8 Setup Overview The table below summarises which instruments and which samples were used for which kind of measurement. Measurement Instruments Used Samples Used (cp. Table 3.1) DC at room temperature Probe Station, Parameter Analyser, Low-Noise Current Amplifier Noise Probe Station, Parameter Analyser, Low-Noise Current Amplifier, Lock-In Temperature-dependent DC Amplifier Cryo Probe Station, Parameter Analyser Table 4.1: Measurement Setup Summary. 1, 2, 3 1, 2, 3 1

42 Chapter 5 Results and Analysis 5.1 Reference Measurements on MOSFETs In publication [25] low-frequency noise in nanowire MOSFETs was studied in detail. There, both number and mobility fluctuations were identified as described in and 2.3.5, respectively. Mobility fluctuations occur below the threshold voltage as the gate electric field confines the conducting electrons to the nanowire core. Above the threshold voltage the gate electric field pulls the electrons close to the nanowire surface instead so that g-r noise becomes dominant due to the high-k material interface and border defects. With the help of the reference measurements it was intended to find out if the results found in [25] can be reproduced with the given setup. If so, this proves that the measurement setup can be used for noise measurements. For the reference measurements MOSFETs fabricated according to the same processing scheme as the MOSFETs examined in [25] were used. The results of the reference measurements showed a behaviour similar to that reported in [25] as can be seen in Fig On first sight, the normalised noise values (I N /I DS ) 2 are much higher for the reference measurements carried out here than they are in [25]. The noise currents without normalisation, however, show the same order of magnitude for both measurement series. The difference in the normalised values is caused by the fact that the MOSFETs used here exhibit lower currents than in [25], mostly due to a smaller diameter (ca. 34 nm as compared to ca. 45 nm). Here, however, this difference in the normalised values is of minor interest as it results from the processing of the devices which is not subject of this thesis. More importantly both measurements showed the same noise behaviour. The g m used for the (g m /I DS ) 2 curves was calculated from DC measurements carried out together with the noise measurements. 31

43 Chapter 5. Results and Analysis 32 (a) (b) 10 2 S Id / I DS ² [1 / Hz] Data 1 / I DS (g m / I DS )² V T I DS [A] Figure 5.1: Comparison between MOSFET noise data measured with a spectrum analyser at KTH and published in [25] and measurements carried out with the setup described in chapter 4. The vertical lines in the graphs labelled with V T indicate the threshold voltages determined from DC measurements. (a) Reference from [25]. Reprinted with the permission of the authors. (b) Measurements carried out to verify the setup. The measurement errors of 20 50% in (b) were left out to increase the comparability with (a) where the measurement errors were not given. Decreasing nanowire diameters also lead to g-r noise becoming the dominating noise process in a device s off-state. This can be seen in Fig. 5.2(a) where the normalised noise current follows (g m /I DS ) 2 also below the threshold voltage. In addition to the characteristic noise behaviour at a fixed frequency (Fig. 5.1) the MOSFET frequency dependence was measured. The results showed a 1/f γ frequency dependence (Fig. 5.2(b)) as described in with γ between 1 and 1.3. γ > 1 indicates that the trap density in the gate oxide decreases towards the interface to the channel. In [25] a 1/f dependence (γ = 1) was observed. The small difference can be attributed to processing variations. (a) (I N / I DS )² [1 / Hz] Data (g m / I DS )² I DS [A] V T (b) (I N / I DS )² [1/Hz] f [Hz] 1 / f 1.2 = 0.5 V = 0.4 V = 0.3 V = 0.2 V = 0.1 V = 0.0 V = 0.1 V = 0.2 V = 0.3 V = 0.4 V = 0.5 V Figure 5.2: Results from the reference measurements carried out to verify the setup. (a) For low nanowire diameters the data points following (g m /I DS ) 2 indicate that g-r noise at the nanowire / high-k material interface becomes dominant also below V T. (b) Noise adding up to a 1/f 1.2 behaviour. The red line is a guide to the eye.