F O U N D R Y L E A D E R S H I P F O R T H E S o C G E N E R A T I O N. Mixed-Signal/RFCMOS
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1 F O U N D R Y L E A D E R S H I P F O R T H E S o C G E N E R A T I O N Mixed-Signal/RFCMOS
2 Solutions for Mixed-Signal/RFCMOS Applications Mixed-Signal and RFCMOS applications have become major requirements for system-on-chip designs. UMC provides a logic compatible process for Mixed-Signal/RF solutions and offers many advanced features to optimize the passive devices such as inductors and capacitors. The frequency range of UMC s scalable models range up to 20GHz. In addition, UMC works very closely with industry leading EDA vendors to deliver seamless design flows to help accelerate time-to-silicon. RF/Wireless Landscape Data rate 10 Gbps PAN LAN WAN ad 1 Gbps 100 Mbps UWB (WiMedia) ac n 5G a/g 4G Mobile TV 10 Mbps b 3G 1 Mbps Bluetooth 2.5G GPS <1m 10m 100m 50km Range PAN: Personal Area Network, LAN: Local Area Network, WAN: Wide Area Network
3 Technology and Performance Technology 250nm 180nm 130/110nm 90nm 65/55nm 40nm 28nm GPS Cell phone Bluetooth ZigBee Mobile TV Wi-Fi - Wi-Fi n - Wi-Fi ac rd Generation partnership project - - 3rd Generation partnership project Long term evolution - - WiMAX - - Key Features High Q inductors on the thicker top copper metal High density MIM capacitors Cost effective Metal Oxide Metal capacitors (MOM) Precision poly resistors Deep Nwell for noise isolation Multiple Vt devices for optimized circuit performance Wide tuning range Varactors Diodes
4 Comprehensive MS/RF Platform UMC s MS/RF technology solutions offer optimum speed and performance. UMC s superior f T and low NF min satisfy most commercial applications. For portable and consumer applications, UMC provides comprehensive processes in accordance with customers particular product requirements. UMC RFCMOS Process Platform RFCMOS Process Baselines Technology HPM HLP LP LL SP GII HS 28nm nm nm nm nm um* um um HPM : High Performance High-K Metal Gate HLP : High Performance Low Power LP : Low Power G : Generic LL : Low Leakage SP : Standard Performance HS : High Speed GII : General Enhance : Ongoing : Available * : UMC's 0.11um AE process with Aluminum BEOL UMC MS/RFCMOS Offerings MOS Native MOS Bipolar MOM Inductor Resistor Diode MIM Transformer Varactor Active Passive UMC MS/RFCMOS Offerings SPICE Models RF Model Monte Carol Model Flicker Noise Model Mismatch Model High Frequency Noise Model FDK Device Symbols Models P Cells VIL/VCL/VTL Rule decks / Tech Files Note: VIL/VCL/VTL is Virtual Inductor/Capacitor/Transformer Library FDK is Foundry Design Kit
5 MS/RF Technology Platform MS/RF Technology Core Devices I/O Devices MS Devices RF Devices LVT 1.8V I/O* Native Diode RVT 2.5V I/O* Bipolar Resistor HVT 3.3V I/O* Diode Varactor 2.5_OD3.3V I/O Resistors (5 Types) MIM MIM MOM : RF Model Support MOM * : Please Contact Account Managers for I/O Options of Each Node Inductor Transformer Active and Passive Devices Active Devices L130E L110AE 90LL 90SP L65LL L65/55LP L65/55SP 40LP 28HLP MOS (Core N,P) MOS (I/O, N,P) Native NMOS BJTs Passive Devices L130E L110AE 90LL/SP 90SP L65LL L65/55LP L65/55SP 40LP 28HLP MOS Varactor Resistors Diodes MIM Capacitor MOM Capacitor Inductors Active Devices L130E L110AE 90LL 90SP L65LL L65/55LP L65/55SP 40LP 28HLP Mismatch Report Characterization Report Noise Report Available
6 Foundry s First Virtual Inductor/Transformer/Capacitor Libraries UMC works with its EDA tool partners to deliver the industry's first parameterized design kits. Full wave simulation has been performed on all kits within the Virtual Inductor / Transformer / Capacitor Libraries. The virtual libraries enable RFCMOS designers to create and simulate custom inductor geometries that are based on UMC's processes. These libraries are built upon UMC's Electromagnetic Design Methodology (EMDM), which allows engineers to easily and accurately create any RF structure. EMDM gives designers the flexibility to innovate new geometries simply by editing parameters such as diameter, number of turns or width. Foundry s First Virtual Library VIL Spiral Differential w/o center tap Differential with center tap Stack Input: single/differential end VTL Output: single/differential end Turn Ratio: 1:n, n:2n, n:n W/O center tap CT on primary coil CT on secondary CT on both coils Octagon VCL Symmetry Asymmetry Note : The Virtual library can be used to simulate all types of RF inductors and capacitors. CT: Center Tap MS/RF Design Flow and FDK The FDK (Foundry Design Kit) provides IC designers with an automatic design environment. The methodology provides access to circuit-level design and simulation, circuit layout, and layout verification using RF device models. In the front-end, fundamental components of UMC s MS/RF process are implemented in common design environments and simulation tools. The back-end includes parameterized cells (P Cell), which includes a schematic driven layout to provide an automatic and complete design flow. Callback functions are also provided in the design flow to minimize data entry. EDA tools for MS/RF designs are also supported. Schematic (Composer) (Symbols & CDF) Schematic Driven Layout Circuit Layout Virtuoso(P-cell) Verification&Extraction (DRC/LVS/LPE) Calibre/XRC Assura Tape Out Inductor spec. Virtual Inductor/ Capacitor Transformer Library Virtual Inductor/ Capacitor/ Transformer Library Spectre/Spectre RF Eldo/EldoRF Hspice ADS Simulator with Verified RF/Mixed Signal Models
7 Optimum Inductor/Capacitor/Transformer Finder (OIF/OCF/OTF) UMC offers the Optimum Inductor Finder (OIF) in the FDK package. The OIF gives designers the ability to quickly access a large library of inductors accurately calibrated to UMC's silicon. It also allows users to perform inductor optimization through just a few simple steps using the user-friendly interface. For instance, customers can define a desired inductor and make trade-offs between Q-factor and area. The OIF will select a design that best fits the specifications in a matter of seconds. In addition, UMC offers the Optimum Capacitor Finder (OCF) in the FDK package. The OCF gives designers the ability to quickly access a large library of capacitors accurately calibrated to UMC's silicon. It also allows users to perform capacitor optimization through just a few simple steps using the user-friendly interface. For instance, customers can define a desired capacitor and make trade-offs between Q-factor and area. The OCF will select a design that best fits the specifications in a matter of seconds. UMC also offers the Optimum Transformer Finder (OTF) in the FDK package. The OTF gives designers the ability to quickly access a large library of transformers accurately calibrated to UMC's silicon. It also allows users to perform transformer optimization through just a few simple steps using the user-friendly interface. For instance, customers can define a desired transformer and make trade-offs between impedance and area. The OTF will select a design that best fits the specifications in a matter of seconds. FDK EDA Supported Tools FDK EDA Supported Tools MS/RF Design Flow Cadence Mentor ADS Synopsys Schematic Entry Composer DA-IC ADS* Laker ADP* Pre-simulation Hspice/Spectre Models Spectre SpectreRF GoldenGate* HSPICE Physical Design Virtuoso XL Laker L3* Physical Verification (DRC/LVS/RCX) Assura QRC Calibre Calibre XRC Hercules Star RCXT Note: *is available by request
8 F O U N D R Y L E A D E R S H I P F O R T H E S o C G E N E R A T I O N North America: UMC USA 488 De Guigne Drive, Sunnyvale, CA 94085, USA Tel: Fax: Asia: UMC No. 3, Li-Hsin 2nd Road, Hsinchu Science Park, Hsinchu, Taiwan Tel: Fax: Europe: UMC Europe BV De entree BH Amsterdam Zuidoost The Netherlands Tel: 31-(0) Fax: 31-(0) Japan: UMC Japan 15F Akihabara Centerplace Bldg., 1 Kanda Aioi-Cho Chiyoda-Ku Tokyo Japan Tel : Fax: Singapore: UMC-SG No. 3, Pasir Ris Drive 12, Singapore Tel: Fax: Korea: UMC Korea Tel: (TWN) Fax: (TWN) For more information: visit or sales@umc.com 1308
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