Low Noise, High Speed Amplifier for 16-Bit Systems AD8021

Size: px

Start display at page:

Download "Low Noise, High Speed Amplifier for 16-Bit Systems AD8021"

Georgiana Anthony
5 years ago
Views:

1 Low Noise, High Speed Amplifier for -Bit Systems AD FEATURES Low noise. nv/ Hz input voltage noise. pa/ Hz input current noise Custom compensation Constant bandwidth from G = to G = High speed MHz (G = ) 9 MHz (G = ) Low power 4 mw or.7 ma typical for V supply Output disable feature,. ma Low distortion 9 dbc second harmonic, fc = MHz dbc third harmonic, fc = MHz DC precision mv maximum input offset voltage. μv/ C input offset voltage drift Wide supply range, V to 4 V Low price Small packaging Available in SOIC- and MSOP- APPLICATIONS ADC preamps and drivers Instrumentation preamps Active filters Portable instrumentation Line receivers Precision instruments Ultrasound signal processing High gain circuits GENERAL DESCRIPTION The AD is an exceptionally high performance, high speed voltage feedback amplifier that can be used in -bit resolution systems. It is designed to have both low voltage and low current noise (. nv/ Hz typical and. pa/ Hz typical) while operating at the lowest quiescent supply current (7 ± V) among today s high speed, low noise op amps. The AD operates over a wide range of supply voltages from ±. V to ± V, as well as from single V supplies, making it ideal for high speed, low power instruments. An output disable pin allows further reduction of the quiescent supply current to. ma. CONNECTION DIAGRAM LOGIC REFERENCE IN +IN 4 AD 7 DISABLE V OUT C COMP Figure. SOIC- (R-) and MSOP- (RM-) The AD allows the user to choose the gain bandwidth product that best suits the application. With a single capacitor, the user can compensate the AD for the desired gain with little trade-off in bandwidth. The AD is a well-behaved amplifier that settles to.% in ns for a V step. It has a fast overload recovery of ns. The AD is stable over temperature with low input offset voltage drift and input bias current drift,. μv/ C and na/ C, respectively. The AD is also capable of driving a 7 Ω line with ± V video signals. The AD is both technically superior and priced considerably less than comparable amps drawing much higher quiescent current. The AD is a high speed, general-purpose amplifier, ideal for a wide variety of gain configurations and can be used throughout a signal processing chain and in control loops. The AD is available in both standard -lead SOIC and MSOP packages in the industrial temperature range of 4 C to + C. CLOSED-LOOP GAIN (db) 4 9 V OUT = mv p-p G =, R F = kω, R G = Ω, R IN = Ω, C C = pf G =, R F = kω, R G = Ω, R IN =.Ω, C C =.pf G =, R F =, R G = 49Ω, R IN =.4Ω, C C = 4pF G =, R F =, R G =, R IN =.Ω, C C = 7pF.M M M M G Figure. Small Signal Frequency Response - - Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Fax: 7.4. Analog Devices, Inc. All rights reserved.

2 AD* PRODUCT PAGE QUICK LINKS Last Content Update: //7 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS Universal Evaluation Board for Single High Speed Operational Amplifiers DOCUMENTATION Application Notes AN-: An IC Amplifier User s Guide to Decoupling, Grounding, and Making Things Go Right for a Change AN-: Find Op Amp Noise with Spreadsheet AN-7: Careful Design Tames High Speed Op Amps AN-: User's Guide to Applying and Measuring Operational Amplifier Specifications AN-7: Operational Integrators AN-: Noise and Operational Amplifier Circuits AN-4: Replacing Output Clamping Op Amps with Input Clamping Amps AN-47: Fast Rail-to-Rail Operational Amplifiers Ease Design Constraints in Low Voltage High Speed Systems AN-: Biasing and Decoupling Op Amps in Single Supply Applications AN-49: Using the Analog Devices Active Filter Design Tool Data Sheet AD: Low Noise, High Speed Amplifier for -Bit Systems Data Sheet User Guides UG-: Evaluation Board for Single, High Speed Operational Amplifiers (-Lead SOIC and Exposed Paddle) TOOLS AND SIMULATIONS Analog Filter Wizard Analog Photodiode Wizard OpAmp Error Budget Calculator Power Dissipation vs Die Temp VRMS/dBm/dBu/dBV calculators AD SPICE Macro-Model REFERENCE DESIGNS CN4 CN REFERENCE MATERIALS Product Selection Guide High Speed Amplifiers Selection Table SAR ADC & Driver Quick-Match Guide Tutorials MT-: Ideal Voltage Feedback (VFB) Op Amp MT-: Voltage Feedback Op Amp Gain and Bandwidth MT-47: Op Amp Noise MT-4: Op Amp Noise Relationships: /f Noise, RMS Noise, and Equivalent Noise Bandwidth MT-49: Op Amp Total Output Noise Calculations for Single-Pole System MT-: Op Amp Total Output Noise Calculations for Second-Order System MT-: Op Amp Noise Figure: Don't Be Misled MT-: Op Amp Distortion: HD, THD, THD + N, IMD, SFDR, MTPR MT-: High Speed Voltage Feedback Op Amps MT-: Effects of Feedback Capacitance on VFB and CFB Op Amps MT-9: Compensating for the Effects of Input Capacitance on VFB and CFB Op Amps Used in Current-to- Voltage Converters MT-: Choosing Between Voltage Feedback and Current Feedback Op Amps DESIGN RESOURCES AD Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints DISCUSSIONS View all AD EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options.

3 TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

4 AD TABLE OF CONTENTS Features... Applications... General Description... Connection Diagram... Revision History... Specifications... Absolute Maximum Ratings... 7 Maximum Power Dissipation... 7 ESD Caution... 7 Pin Configuration and Function Descriptions... Applications... 9 Using the Disable Feature... Theory of Operation... PCB Layout Considerations... Driving -Bit ADCs... Differential Driver... Using the AD in Active Filters... Driving Capacitive Loads... Outline Dimensions... Ordering Guide... Typical Performance Characteristics... 9 Test Circuits... 7 REVISION HISTORY / Rev. E to Rev. F Updated Format...Universal Changes to General Description... Changes to Figure... 7 Changes to Figure... 9 Changes to Table 9... / Rev. D to Rev. E Updated Format...Universal Change to Figure 9... Change to Figure... Change to Table 7 and Table... Change to Driving -Bit ADCs Section... 7/ Rev. B to Rev. C Deleted All References to Evaluation Board...Universal Replaced Figure... Updated Outline Dimensions... / Rev. A to Rev. B Edits to Evaluation Board Applications... Edits to Figure 7... / Rev. to Rev. A Edits to Specifications... / Rev. C to Rev. D Updated Format...Universal Rev. F Page of

5 AD SPECIFICATIONS VS = ± TA = C, RL = kω, gain = +, unless otherwise noted. Table. ADAR/ADARM Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Small Signal Bandwidth G = +, CC = pf, VO =. V p-p 49 MHz G = +, CC = 7 pf, VO =. V p-p MHz G = +, CC = pf, VO =. V p-p MHz G = +, CC = pf, VO =. V p-p MHz Slew Rate, V Step G = +, CC = pf 9 V/μs G = +, CC = 7 pf V/μs G = +, CC = pf V/μs G = +, CC = pf 4 V/μs Settling Time to.% VO = V step, RL = Ω ns Overload Recovery (%) ±. V input step, G = + ns DISTORTION/NOISE PERFORMANCE f = MHz HD VO = V p-p 9 dbc HD VO = V p-p dbc f = MHz HD VO = V p-p 7 dbc HD VO = V p-p dbc Input Voltage Noise f = khz.. nv/ Hz Input Current Noise f = khz. pa/ Hz Differential Gain Error NTSC, RL = Ω. % Differential Phase Error NTSC, RL = Ω.4 Degrees DC PERFORMANCE Input Offset Voltage.4. mv Input Offset Voltage Drift TMIN to TMAX. μv/ C Input Bias Current +Input or input 7.. μa Input Bias Current Drift na/ C Input Offset Current.. ±μa Open-Loop Gain db INPUT CHARACTERISTICS Input Resistance MΩ Common-Mode Input Capacitance pf Input Common-Mode Voltage Range 4. to +4. V Common-Mode Rejection Ratio VCM = ±4 V 9 db OUTPUT CHARACTERISTICS Output Voltage Swing. to +.. to +.4 V Linear Output Current ma Short-Circuit Current 7 ma Capacitive Load Drive for % Overshoot VO = mv p-p/ V p-p / pf DISABLE CHARACTERISTICS Off Isolation f = MHz 4 db Turn-On Time VO = V to V, % logic to % output 4 ns Turn-Off Time VO = V to V, % logic to % output ns DISABLE Voltage Off/On VDISABLE VLOGIC REFERENCE.7/.9 V Enabled Leakage Current LOGIC REFERENCE =.4 V 7 μa DISABLE = 4. V μa Rev. F Page of

6 AD ADAR/ADARM Parameter Conditions Min Typ Max Unit Disabled Leakage Current LOGIC REFERENCE =.4 V μa DISABLE =.4 V μa POWER SUPPLY Operating Range ±. ± ±. V Quiescent Current Output enabled ma Output disabled.. ma +Power Supply Rejection Ratio VCC = 4 V to V, VEE = V 9 db Power Supply Rejection Ratio VCC = V, VEE = V to 4 V 9 db VS = ± TA = C, RL = kω, gain = +, unless otherwise noted. Table. ADAR/ADARM Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Small Signal Bandwidth G = +, CC = pf, VO =. V p-p MHz G = +, CC = 7 pf, VO =. V p-p 7 MHz G = +, CC = pf, VO =. V p-p 7 MHz G = +, CC = pf, VO =. V p-p MHz Slew Rate, V Step G = +, CC = pf V/μs G = +, CC = 7 pf 4 7 V/μs G = +, CC = pf 4 V/μs G = +, CC = pf 4 4 V/μs Settling Time to.% VO = V step, RL = Ω ns Overload Recovery (%) ± V input step, G = + 9 ns DISTORTION/NOISE PERFORMANCE f = MHz HD VO = V p-p 9 dbc HD VO = V p-p dbc f = MHz HD VO = V p-p 7 dbc HD VO = V p-p dbc Input Voltage Noise f = khz.. nv/ Hz Input Current Noise f = khz. pa/ Hz Differential Gain Error NTSC, RL = Ω. % Differential Phase Error NTSC, RL = Ω.4 Degrees DC PERFORMANCE Input Offset Voltage.4. mv Input Offset Voltage Drift TMIN to TMAX. μv/ C Input Bias Current +Input or input. μa Input Bias Current Drift na/ C Input Offset Current.. ±μa Open-Loop Gain 4 db INPUT CHARACTERISTICS Input Resistance MΩ Common-Mode Input Capacitance pf Input Common-Mode Voltage Range. to +. V Common-Mode Rejection Ratio VCM = ± V 9 db Rev. F Page 4 of

7 AD ADAR/ADARM Parameter Conditions Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage Swing. to +9.. to +. V Linear Output Current 7 ma Short-Circuit Current ma Capacitive Load Drive for % Overshoot VO = mv p-p/ V p-p / pf DISABLE CHARACTERISTICS Off Isolation f = MHz 4 db Turn-On Time VO = V to V, % logic to % output 4 ns Turn-Off Time VO = V to V, % logic to % output ns DISABLE Voltage Off/On VDISABLE VLOGIC REFERENCE./.9 V Enabled Leakage Current LOGIC REFERENCE =.4 V 7 μa DISABLE = 4. V μa Disabled Leakage Current LOGIC REFERENCE =.4 V μa DISABLE =.4 V μa POWER SUPPLY Operating Range ±. ± ±. V Quiescent Current Output enabled 7.. ma Output disabled.7. ma +Power Supply Rejection Ratio VCC = V to V, VEE = V 9 db Power Supply Rejection Ratio VCC = V, VEE = V to V db VS = TA = C, RL = kω, gain = +, unless otherwise noted. Table. ADAR/ADARM Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Small Signal Bandwidth G = +, CC = pf, VO =. V p-p 7 MHz G = +, CC = 7 pf, VO =. V p-p 9 MHz G = +, CC = pf, VO =. V p-p MHz G = +, CC = pf, VO =. V p-p 9 MHz Slew Rate, V Step G = +, CC = pf V/μs G = +, CC = 7 pf 4 V/μs G = +, CC = pf V/μs G = +, CC = pf 9 9 V/μs Settling Time to.% VO = V step, RL = Ω ns Overload Recovery (%) V to. V input step, G = + 4 ns DISTORTION/NOISE PERFORMANCE f = MHz HD VO = V p-p 4 dbc HD VO = V p-p 9 dbc f = MHz HD VO = V p-p dbc HD VO = V p-p dbc Input Voltage Noise f = khz.. nv/ Hz Input Current Noise f = khz. pa/ Hz Rev. F Page of

8 AD ADAR/ADARM Parameter Conditions Min Typ Max Unit DC PERFORMANCE Input Offset Voltage.4. mv Input Offset Voltage Drift TMIN to TMAX. μv/ C Input Bias Current +Input or input 7.. μa Input Bias Current Drift na/ C Input Offset Current.. ±μa Open-Loop Gain 7 7 db INPUT CHARACTERISTICS Input Resistance MΩ Common-Mode Input Capacitance pf Input Common-Mode Voltage Range.9 to 4. V Common-Mode Rejection Ratio. V to. V 4 9 db OUTPUT CHARACTERISTICS Output Voltage Swing. to.. to. V Linear Output Current ma Short-Circuit Current ma Capacitive Load Drive for % Overshoot VO = mv p-p/ V p-p / pf DISABLE CHARACTERISTICS Off Isolation f = MHz 4 db Turn-On Time VO = V to V, % logic to % output 4 ns Turn-Off Time VO = V to V, % logic to % output ns DISABLE Voltage Off/On VDISABLE VLOGIC REFERENCE./.7 V Enabled Leakage Current LOGIC REFERENCE =.4 V 7 μa DISABLE = 4. V μa Disabled Leakage Current LOGIC REFERENCE =.4 V μa DISABLE =.4 V μa POWER SUPPLY Operating Range ±. ± ±. V Quiescent Current Output enabled.7 7. ma Output disabled.. ma +Power Supply Rejection Ratio VCC = 4. V to. V, VEE = V 74 db Power Supply Rejection Ratio VCC = V, VEE =. V to +. V 7 4 db Rev. F Page of

9 AD ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating Supply Voltage.4 V Power Dissipation Observed power derating curves Input Voltage (Common Mode) ±VS ± V Differential Input Voltage ±. V Differential Input Current ± ma Output Short-Circuit Duration Observed power derating curves Storage Temperature Range C to + C Operating Temperature Range 4 C to + C Lead Temperature (Soldering, sec) C The AD inputs are protected by diodes. Current-limiting resistors are not used to preserve the low noise. If a differential input exceeds ±. V, the input current should be limited to ± ma. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately C. Temporarily exceeding this limit can cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 7 C for an extended period can result in device failure. While the AD is internally short-circuit protected, this can not be sufficient to guarantee that the maximum junction temperature ( C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. MAXIMUM POWER DISSIPATION (W).... -LEAD MSOP -LEAD SOIC AMBIENT TEMPERATURE ( C) Figure. Maximum Power Dissipation vs. Temperature -4 Specification is for device in free air: -lead SOIC: θja = C/W; -lead MSOP: θja = 4 C/W. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. F Page 7 of

10 AD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS LOGIC REFERENCE AD DISABLE IN 7 +IN V OUT 4 C COMP Figure 4. Pin Configuration - Table. Pin Function Descriptions Pin No. Mnemonic Description LOGIC REFERENCE Reference for Pin Voltage Level. Connect to logic low supply. IN Inverting Input. +IN Noninverting Input. 4 VS Negative Supply Voltage. CCOMP Compensation Capacitor. Tie to VS. (See the Applications section for value.) VOUT Output. 7 +VS Positive Supply Voltage. DISABLE Disable, Active Low. When Pin (DISABLE) is higher than Pin (LOGIC REFERENCE) by approximately V or more, the part is enabled. When Pin is brought down to within about. V of Pin, the part is disabled. (See the Specifications tables for exact disable and enable voltage levels.) If the disable feature is not going to be used, Pin can be tied to +VS or a logic high source, and Pin can be tied to ground or logic low. Alternatively, if Pin and Pin are not connected, the part is in an enabled state. Rev. F Page of

11 TYPICAL PERFORMANCE CHARACTERISTICS AD TA = C, VS = ± V, RL = kω, G = +, RF = RG = 499 Ω, RS = 49.9 Ω, RO = 97 Ω, RD =. Ω, CC = 7 pf, CL =, CF =, VOUT = V p-p, frequency = MHz, unless otherwise noted. 4 G = +, R F = kω, R G = Ω, C C = pf 9 G = + V S = ±.V V S = ±V 7 CLOSED-LOOP GAIN (db) 9 G = +, R F = kω, R G = 49Ω, C C = pf G = +, R F = R G =, C C = 7pF G = +, R F = 7Ω, C C = pf GAIN (db) 4 V S = ±.V V S = ±V.M M M M G - M M M G - Figure. Small Signal Frequency Response vs. Frequency and Gain, VOUT = mv p-p, Noninverting (See Figure 4) Figure. Small Signal Frequency Response vs. Frequency and Supply, VOUT = mv p-p, Noninverting (See Figure 4) 4 G =, R F = kω, R G = Ω, R IN = Ω, C C = pf G = V S = ±.V V S = ±V GAIN (db) 9 G =, R F = kω, R G = Ω, R IN =.Ω, C C =.pf G =, R F =, R G = 49Ω, R IN =.4Ω, C C = 4pF GAIN (db) 4 V S = ±V G =, R F =, R G =, R IN =.Ω, C C = 7pF.M M M M G - 7 M V S = ±.V M M G -9 Figure. Small Signal Frequency Response vs. Frequency and Gain, VOUT = mv p-p Inverting (See Figure 4) Figure 9. Small Signal Frequency Response vs. Frequency and Supply, VOUT = mv p-p, Inverting (See Figure ) 9 G = + C C = pf 9 G = + 7 C C = 7pF 7 V OUT =.V AND mv p-p GAIN (db) 4 C C = 9pF GAIN (db) 4 V OUT = 4V p-p C C = 7pF V OUT = V p-p C C = 9pF.M M M M G Figure 7. Small Signal Frequency Response vs. Frequency and Compensation Capacitor, VOUT = mv p-p (See Figure 4) -7 M M M G Figure. Frequency Response vs. Frequency and VOUT, Noninverting (See Figure 4) - Rev. F Page 9 of

12 AD 9 G = + 9 G = + R F = R G R F = R F = kω GAIN (db) 7 4 R L = kω GAIN (db) 7 4 R F = Ω R F = Ω R L = Ω R F = 7Ω.M M M M G - R F = kω AND C F =.pf.m M M M G -4 Figure. Large Signal Frequency Response vs. Frequency and Load, Noninverting (See Figure 49) Figure 4. Small Signal Frequency Response vs. Frequency and RF, Noninverting, VOUT = mv p-p (See Figure 4) 9 7 G = + + C + C 9 G = + GAIN (db) 4 + C V OUT = V p-p 4 C V OUT = mv p-p GAIN (db) R S = 49.9Ω R S = Ω M + C 4 C M M G - 9 R S = 49Ω.M M M M G - Figure. Frequency Response vs. Frequency, Temperature, and VOUT, Noninverting (See Figure 4) Figure. Small Signal Frequency Response vs. Frequency and RS, Noninverting, VOUT = mv p-p (See Figure 4) G = + pf pf 9 GAIN (db) 9 pf pf pf OPEN-LOOP GAIN (db) PHASE (Degrees) 4 9 M M M G - k k M M M 9 G - Figure. Small Signal Frequency Response vs. Frequency and Capacitive Load, Noninverting, VOUT = mv p-p (See Figure 49 and Figure 7) Figure. Open-Loop Gain and Phase vs. Frequency, RG = Ω, RF = kω, RO = 97 Ω, RD =. Ω, CC = pf (See Figure ) Rev. F Page of

13 AD.4 G = +. V S = ±.V 4 GAIN (db).. V S = ±V V S = ±V P OUT (dbm) 7 Δf =.MHz f f 97Ω P OUT.Ω Ω 9..4 M M -7 M FREQUENCY (MHz) -. Figure 7.. db Flatness vs. Frequency and Supply, VOUT = V p-p, RL = Ω, Noninverting (See Figure 49) Figure. Intermodulation Distortion vs. Frequency DISTORTION (dbc) R L = Ω R L = kω SECOND THIRD-ORDER INTERCEPT (dbm) 4 4 V S = ±.V V S = ±V.M THIRD M M - M FREQUENCY (MHz) - Figure. Second and Third Harmonic Distortion vs. Frequency and RL Figure. Third-Order Intercept vs. Frequency and Supply Voltage 4 DISTORTION (dbc) 7 THIRD SECOND V S = ±.V 9 SECOND V S = ±V THIRD SECOND k M V S = ±V M -9 M DISTORTION (dbc) 7 9 SECOND R L = Ω THIRD SECOND R L = kω THIRD 4 V OUT (V p-p) - Figure 9. Second and Third Harmonic Distortion vs. Frequency and VS Figure. Second and Third Harmonic Distortion vs. VOUT and RL Rev. F Page of

14 AD.. DISTORTION (dbc) 7 9 THIRD SECOND f C = MHz SECOND f C = MHz THIRD 4 V OUT (V p-p) - POSITIVE OUTPUT VOLTAGE (V) POSITIVE OUTPUT NEGATIVE OUTPUT LOAD (Ω) NEGATIVE OUTPUT VOLTAGE (V) - Figure. Second and Third Harmonic Distortion vs. VOUT and Fundamental Frequency (fc), G = + Figure. DC Output Voltages vs. Load (See Figure 4) 4 DISTORTION (dbc) 7 9 SECOND THIRD SECOND THIRD f C = MHz f C = MHz 4 V OUT (V p-p) -4 SHORT-CIRCUIT CURRENT (ma) 4 V S = ±V V S = ±.V V S = ±.V 7 9 TEMPERATURE ( C) -7 Figure 4. Second and Third Harmonic Distortion vs. VOUT and Fundamental Frequency (fc), G = + Figure 7. Short-Circuit Current to Ground vs. Temperature 7 f C = MHz R L = kω R F = R G G = + 4 G = R L = kω, Ω DISTORTION (dbc) 9 SECOND THIRD V OUT (mv) 4 FEEDBACK RESISTANCE (Ω) TIME (ns) - Figure. Second and Third Harmonic Distortion vs. Feedback Resistor (RF) Figure. Small Signal Transient Response vs. RL, VO = mv p-p, Noninverting (See Figure 49) Rev. F Page of

15 AD. V O = 4V p-p G =. V O = V p-p G =. R L = kω. V OUT (V) R L = Ω V OUT (V) V S = ±.V.. V S = ±V. 4 TIME (ns) Figure 9. Large Signal Transient Response vs. RL, Noninverting (See Figure 49) TIME (ns) Figure. Large Signal Transient Response vs. VS (See Figure 4) - 4 V O = 4V p-p G = V IN = ±V G = + V IN = V/DIV V OUT = V/DIV V OUT, R L = kω V IN R L = Ω VOLTS V OUT 4 TIME (ns) - V IN 4 TIME (ns) - Figure. Large Signal Transient Response, Inverting (See Figure ) Figure. Overdrive Recovery vs. RL (See Figure 49). C L = pf G = V O = 4V p-p G = V OUT (V).. C L = pf, pf OUTPUT SETTLING +.%.% ns. - VERT =.mv/div HOR = ns/div -4 4 TIME (ns) Figure. Large Signal Transient Response vs. CL (See Figure 4) Figure 4..% Settling Time, V Step Rev. F Page of

16 AD SETTLING (µv) 4 4 V PULSE WIDTH = ns PULSE WIDTH = µs INPUT CURRENT NOISE (pa/ Hz) V t 4 4 TIME (µs) Figure. Long-Term Settling, V to V, VS = ± V, G = + - k k k M M Figure. Input Current Noise vs. Frequency - 4 G = V OUT (mv) VOLTAGE OFFSET (mv) TIME (ns) TEMPERATURE ( C) -9 Figure. Small Signal Transient Response, VO = mv p-p, G = + (See Figure 4) Figure 9. VOS vs. Temperature.4. VOLTAGE NOISE (nv/ Hz).nV/ Hz INPUT BIAS CURRENT (μa) k k k M -7 M. 7 TEMPERATURE ( C) -4 Figure 7. Input Voltage Noise vs. Frequency Figure 4. Input Bias Current vs. Temperature Rev. F Page 4 of

17 AD 4 CMRR (db) 7 9 DISABLED ISOLATION (db) 4 7 k k M M M -4 9.M M M M G -44 Figure 4. CMRR vs. Frequency (See Figure ) Figure 44. Input-to-Output Isolation, Chip Disabled (See Figure 4) k k k OUTPUT IMPEDANCE (Ω).. OUTPUT IMPEDANCE (Ω) k k k... k k M M M G Figure 4. Output Impedance vs. Frequency, Chip Enabled (See Figure ) -4 k k M M M G Figure 4. Output Impedance vs. Frequency, Chip Disabled (See Figure ) -4 4V DISABLE V PSRR V V t EN = 4ns V OUTPUT t DIS = ns PSRR (db) 4 7 V S = ±.V +PSRR V S = ±V V S = ±V 4 TIME (ns) Figure 4. Enable (ten)/disable (tdis) Time vs. VOUT (See Figure ) -4 9 k k M M M Figure 4. PSRR vs. Frequency and Supply Voltage (See Figure and Figure 7) -4 M Rev. F Page of

18 AD.. SUPPLY CURRENT (ma) TEMPERATURE ( C) Figure 47. Quiescent Supply Current vs. Temperature -47 Rev. F Page of

19 AD TEST CIRCUITS Ω Ω CABLE R IN 49.9Ω R S C C R O R D Ω CABLE Ω AD C C Ω HP7D NETWORK ANALYZER R G R F C F -4 R G 7pF R F - Figure 4. Noninverting Gain Figure. Output Impedance, Chip Enabled Ω CABLE R S FET PROBE 49.9Ω AD Ω R IN 49.9Ω C C C L R L.V 4V 49.9Ω 49.9Ω LOGIC REF DISABLE C C 97Ω.Ω R G R F 7pF C F Figure 49. Noninverting Gain and FET Probe Figure. Enable/Disable 49.9Ω R O Ω CABLE HP7D NETWORK ANALYZER Ω Ω CABLE RIN 49.9Ω R G C C R F Figure. Inverting Gain R D - Ω 49.9Ω 49.9Ω Ω LOGIC REF DISABLE AD Ω CABLE FET PROBE kω Ω HP7D NETWORK ANALYZER Ω C C 7pF Figure 4. Input-to-Output Isolation, Chip Disabled -4.Ω AD +V S C C 7pF Figure. CMRR 49.9Ω - Ω AD C C 7pF Ω HP7D NETWORK ANALYZER Figure. Output Impedance, Chip Disabled - Rev. F Page 7 of

20 AD BIAS BNC Ω HP7D NETWORK ANALYZER Ω BIAS BNC Ω HP7D NETWORK ANALYZER Ω Ω CABLE Ω CABLE 49Ω C C 7pF 49.9Ω, W 97Ω.Ω 49Ω 49.9Ω W C C 7pF 97Ω.Ω - -7 Figure. Positive PSRR Figure 7. Negative PSRR Rev. F Page of

21 AD APPLICATIONS The typical voltage feedback op amp is frequency stabilized with a fixed internal capacitor, CINTERNAL, using dominant pole compensation. To a first-order approximation, voltage feedback op amps have a fixed gain bandwidth product. For example, if its db bandwidth is MHz for a gain of G = +; at a gain of G = +, its bandwidth is only about MHz. The AD is a voltage feedback op amp with a minimal CINTERNAL of about. pf. By adding an external compensation capacitor, CC, the user can circumvent the fixed gain bandwidth limitation of other voltage feedback op amps. Unlike the typical op amp with fixed compensation, the AD allows the user to: Maximize the amplifier bandwidth for closed-loop gains between and, avoiding the usual loss of bandwidth and slew rate. Optimize the trade-off between bandwidth and phase margin for a particular application. Match bandwidth in gain blocks with different noise gains, such as when designing differential amplifiers (as shown in Figure ). OPEN-LOOP GAIN (db) C C = pf C C = pf (B) (A) k k k M M M G G (B) (A) (C) (C) Figure. Simplified Diagram of Open-Loop Gain and Phase Response Figure is the AD gain and phase plot that has been simplified for instructional purposes. Arrow A in Figure shows a bandwidth of about MHz and a phase margin at about when the desired closed-loop gain is G = + and the value chosen for the external compensation capacitor is CC = pf. If the gain is changed to G = + and CC is fixed at pf, then (as expected for a typical op amp) the bandwidth is 9 4 PHASE (Degrees) - degraded to about MHz and the phase margin increases to 9 (Arrow B). However, by reducing CC to pf, the bandwidth and phase margin return to about MHz and (Arrow C), respectively. In addition, the slew rate is dramatically increased, as it roughly varies with the inverse of CC. COMPENSATION CAPACITANCE (pf) NOISE GAIN (V/V) Figure 9. Suggested Compensation Capacitance vs. Gain for Maintaining db Peaking Table and Figure 9 provide recommended values of compensation capacitance at various gains and the corresponding slew rate, bandwidth, and noise. Note that the value of the compensation capacitor depends on the circuit noise gain, not the voltage gain. As shown in Figure, the noise gain, GN, of an op amp gain block is equal to its noninverting voltage gain, regardless of whether it is actually used for inverting or noninverting gain. Thus, Noninverting GN = RF/RG + Inverting GN = RF/RG + R S + AD C COMP G = G N = + R F kω R G 49Ω R G 49Ω NONINVERTING INVERTING Figure. The Noise Gain of Both is R F kω AD + G = 4 G N = + C COMP -9 - Rev. F Page 9 of

22 AD CF = CL =, RL = kω, RIN = 49.9 Ω (see Figure 49). Table. Recommended Component Values Noise Gain (Noninverting Gain) RS (Ω) RF (Ω) RG (Ω) CCOMP (pf) Slew Rate (V/μs) db SS BW (MHz) Output Noise (AD Only) (nv/ Hz) 7 7 NA k k k k Output Noise (AD with Resistors) (nv/ Hz) With the AD, a variety of trade-offs can be made to finetune its dynamic performance. Sometimes more bandwidth or slew rate is needed at a particular gain. Reducing the compensation capacitance, as illustrated in Figure 7, increases the bandwidth and peaking due to a decrease in phase margin. On the other hand, if more stability is needed, increasing the compensation capacitor decreases the bandwidth while increasing the phase margin. As with all high speed amplifiers, parasitic capacitance and inductance around the amplifier can affect its dynamic response. Often, the input capacitance (due to the op amp itself, as well as the PC board) has a significant effect. The feedback resistance, together with the input capacitance, can contribute to a loss of phase margin, thereby affecting the high frequency response, as shown in Figure 4. A capacitor (CF) in parallel with the feedback resistor can compensate for this phase loss. Additionally, any resistance in series with the source creates a pole with the input capacitance (as well as dampen high frequency resonance due to package and board inductance and capacitance), the effect of which is shown in Figure. It must also be noted that increasing resistor values increases the overall noise of the amplifier and that reducing the feedback resistor value increases the load on the output stage, thus increasing distortion (see Figure ). USING THE DISABLE FEATURE When Pin (DISABLE) is higher than Pin (LOGIC REFERENCE) by approximately V or more, the part is enabled. When Pin is brought down to within about. V of Pin, the part is disabled. See Table for exact disable and enable voltage levels. If the disable feature is not used, Pin can be tied to VS or a logic high source, and Pin can be tied to ground or logic low. Alternatively, if Pin and Pin are not connected, the part is in an enabled state. Rev. F Page of

23 AD THEORY OF OPERATION The AD is fabricated on the second generation of Analog Devices proprietary High Voltage extra-fast Complementary Bipolar (XFCB) process, which enables the construction of PNP and NPN transistors with similar fts in the GHz region. The transistors are dielectrically isolated from the substrate (and each other), eliminating the parasitic and latch-up problems caused by junction isolation. It also reduces nonlinear capacitance (a source of distortion) and allows a higher transistor, ft, for a given quiescent current. The supply current is trimmed, which results in less part-to-part variation of bandwidth, slew rate, distortion, and settling time. As shown in Figure, the AD input stage consists of an NPN differential pair in which each transistor operates at a. ma collector current. This allows the input devices a high transconductance; thus, the AD has a low input noise of. nv/ khz. The input stage drives a folded cascode that consists of a pair of PNP transistors. The folded cascode and current mirror provide a differential-to-single-ended conversion of signal current. This current then drives the high impedance node (Pin ), where the CC external capacitor is connected. The output stage preserves this high impedance with a current gain of, so that the AD can maintain a high open-loop gain even when driving heavy loads. Two internal diode clamps across the inputs (Pin and Pin ) protect the input transistors from large voltages that could otherwise cause emitter-base breakdown, which would result in degradation of offset voltage and input bias current. +IN IN C INTERNAL.pF OUTPUT PCB LAYOUT CONSIDERATIONS As with all high speed op amps, achieving optimum performance from the AD requires careful attention to PC board layout. Particular care must be exercised to minimize lead lengths between the ground leads of the bypass capacitors and between the compensation capacitor and the negative supply. Otherwise, lead inductance can influence the frequency response and even cause high frequency oscillations. Use of a multilayer printed circuit board, with an internal ground plane, reduces ground noise and enables a compact component arrangement. Due to the relatively high impedance of Pin and low values of the compensation capacitor, a guard ring is recommended. The guard ring is simply a PC trace that encircles Pin and is connected to the output, Pin, which is at the same potential as Pin. This serves two functions. It shields Pin from any local circuit noise generated by surrounding circuitry. It also minimizes stray capacitance, which would tend to otherwise reduce the bandwidth. An example of a guard ring layout is shown in Figure. Also shown in Figure, the compensation capacitor is located immediately adjacent to the edge of the AD package, spanning Pin 4 and Pin. This capacitor must be a high quality surfacemount COG or NPO ceramic. The use of leaded capacitors is not recommended. The high frequency bypass capacitor(s) should be located immediately adjacent to the supplies, Pin 4 and Pin 7. To achieve the shortest possible lead length at the inverting input, the feedback resistor RF is located beneath the board and spans the distance from the output, Pin, to inverting input Pin. The return node of Resistor RG should be situated as close as possible to the return node of the negative supply bypass capacitor connected to Pin 4. LOGIC REFERENCE IN (TOP VIEW) 7 DISABLE BYPASS CAPACITOR C COMP CC - +IN 4 C COMP V OUT GROUND PLANE Figure. Simplified Schematic METAL BYPASS CAPACITOR GROUND PLANE COMPENSATION CAPACITOR - Figure. Recommended Location of Critical Components and Guard Ring Rev. F Page of

24 AD DRIVING -BIT ADCs Low noise and adjustable compensation make the AD especially suitable as a buffer/driver for high resolution ADCs. As seen in Figure 9, the harmonic distortion is better than 9 dbc at frequencies between khz and MHz. This is an advantage for complex waveforms that contain high frequency information, because the phase and gain integrity of the sampled waveform can be preserved throughout the conversion process. The increase in loop gain results in improved output regulation and lower noise when the converter input changes state during a sample. This advantage is particularly apparent when using -bit high resolution ADCs with high sampling rates. Figure shows a typical ADC driver configuration. The AD is in an inverting gain of 7., fc is khz, and its output voltage is V p-p. The results are listed in Table 7. Ω 9Ω R G Ω +V + AD C C pf V pf R F.kΩ IN HI IN HI +V AD7 7kSPS Figure. Inverting ADC Driver, Gain = 7., fc = khz Table 7. Summary of ADC Driver Performance (fc = khz, VOUT = V p-p) Parameter Measurement Unit Second Harmonic Distortion. dbc Third Harmonic Distortion 9. dbc THD. dbc SFDR +. dbc Figure 4 shows another ADC driver connection. The circuit was tested with a noninverting gain of. and an output voltage of approximately V p-p for optimum resolution and noise performance. No filtering was used. An FFT was performed using Analog Devices evaluation software for the AD7 -bit converter. The results are listed in Table. Ω +V Ω + Ω AD C C IN HI BITS +V - Table. Summary of ADC Driver Performance (fc = khz, VOUT = V p-p) Parameter Measurement Unit Second Harmonic Distortion 9. dbc Third Harmonic Distortion.4 dbc THD 4.4 dbc SFDR +.4 dbc DIFFERENTIAL DRIVER The AD is uniquely suited as a low noise differential driver for many ADCs, balanced lines, and other applications requiring differential drive. If pairs of internally compensated op amps are configured as inverter and follower, the noise gain of the inverter is higher than that of the follower section, resulting in an imbalance in the frequency response (see Figure ). A better solution takes advantage of the external compensation feature of the AD. By reducing the CCOMP value of the inverter, its bandwidth can be increased to match that of the follower, avoiding compromises in gain bandwidth and phase delay. The inverting and noninverting bandwidths can be closely matched using the compensation feature, thus minimizing distortion. Figure illustrates an inverter-follower driver circuit operating at a gain of, using individually compensated ADs. The values of feedback and load resistors were selected to provide a total load of less than kω, and the equivalent resistances seen at each op amp s inputs were matched to minimize offset voltage and drift. Figure 7 is a plot of the resulting ac responses of driver halves. V IN 49.9Ω 49Ω G = + + AD 7pF Ω G = + Ω AD pf 4Ω kω kω Figure. Differential Amplifier V OUT V OUT - R G.Ω V R F 7Ω OPTIONAL C F IN LO AD7 7kSPS ADC Figure 4. Noninverting ADC Driver, Gain =, fc = khz BITS -4 Rev. F Page of

25 B B + are AD C 9 V IN R R C AD V OUT GAIN (db) 9 G = G = + k M M M G Figure. AC Response of Two Identically Compensated High Speed Op Amps Configured for a Gain of + and a Gain of GAIN (db) 9 9 G = ± k M M M G Figure 7. AC Response of Two Dissimilarly Compensated AD Op Amps (Figure ) Configured for a Gain of + and a Gain of, (Note the Close Gain Match) USING THE AD IN ACTIVE FILTERS The low noise and high gain bandwidth of the AD make it an excellent choice in active filter circuits. Most active filter literature provides resistor and capacitor values for various filters but neglects the effect of the op amp s finite bandwidth on filter performance; ideal filter response with infinite loop gain is implied. Unfortunately, real filters do not behave in this manner. Instead, they exhibit finite limits of attenuation, depending on the gain bandwidth of the active device. Good low-pass filter performance requires an op amp with high gain bandwidth for attenuation at high frequencies, and low noise and high dc gain for low frequency, pass-band performance. Figure shows the schematic of a -pole, low-pass active filter and lists typical component values for filters having a Besseltype response with a gain of and a gain of. Figure 9 is a network analyzer plot of this filter s performance R G C C R F Figure. Schematic of a Second-Order, Low-Pass Active Filter Table 9. Typical Component Values for Second-Order, Low- Pass Active Filter of Figure Gain R (Ω) R (Ω) RF (Ω) RG (Ω) C (nf) C (nf) CC (pf) GAIN (db) 4 4 G = G = k k k M M Figure 9. Frequency Response of the Filter Circuit of Figure for Two Different Gains DRIVING CAPACITIVE LOADS When the AD drives a capacitive load, the high frequency response can show excessive peaking before it rolls off. Two techniques can be used to improve stability at high frequency and reduce peaking. The first technique is to increase the compensation capacitor, CC, which reduces the peaking while maintaining gain flatness at low frequencies. The second technique is to add a resistor, RSNUB, in series between the output pin of the AD and the capacitive load, CL. Figure 7 shows the response of the AD when both CC and RSNU B used to reduce peaking. For a given CL, Figure 7 can be used to determine the value of RSNUB that maintains db of peaking in the frequency response. Note, however, that using RSNUB attenuates the low frequency output by a factor of RLOAD/(RSNU B - RLOAD). -9 Rev. F Page of

26 AD GAIN (db) Ω 49.9Ω FET PROBE R SNUB pf C C R L kω C C = 7pF; R SNUB = Ω C C = pf; R SNUB = Ω R SNUB (Ω) 4 4 C C = pf; R SNUB = 7.4Ω.. FREQUENCY (MHz) Figure 7. Peaking vs. RSNUB and CC for CL = pf CAPACITIVE LOAD (pf) Figure 7. Relationship of RSNUB B vs. CL for db Peaking at a Gain of + -7 Rev. F Page 4 of

27 AD OUTLINE DIMENSIONS. (.9) 4. (.9) 4. (.74). (.497) 4. (.44). (.4). (.9). (.4) COPLANARITY..7 (.) BSC SEATING PLANE.7 (.). (.). (.). (.). (.9).7 (.7). (.9). (.99) 4.7 (.).4 (.7) COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 7. -Lead Standard Small Outline Package [SOIC] Narrow Body (R-) Dimensions shown in millimeters and (inches) PIN. BSC.. COPLANARITY.. MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-7-AA Figure 7. -Lead Mini Small Outline Package [MSOP] (RM-) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding ADAR 4 C to + C -Lead SOIC R- ADAR-REEL 4 C to + C -Lead SOIC R- ADAR-REEL7 4 C to + C -Lead SOIC R- ADARZ 4 C to + C -Lead SOIC R- ADARZ-REEL 4 C to + C -Lead SOIC R- ADARZ-REEL7 4 C to + C -Lead SOIC R- ADARM 4 C to + C -Lead MSOP RM- HNA ADARM-REEL 4 C to + C -Lead MSOP RM- HNA ADARM-REEL7 4 C to + C -Lead MSOP RM- HNA ADARMZ 4 C to + C -Lead MSOP RM- HNA# ADARMZ-REEL 4 C to + C -Lead MSOP RM- HNA# ADARMZ-REEL7 4 C to + C -Lead MSOP RM- HNA# Z = Pb-free part, # denotes lead-free product may be top or bottom marked. Rev. F Page of

28 AD NOTES Rev. F Page of

29 AD NOTES Rev. F Page 7 of

Low Noise, High Speed Amplifier for 16-Bit Systems AD8021

Low Noise, High Speed Amplifier for -Bit Systems AD FEATURES Low noise. nv/ Hz input voltage noise. pa/ Hz input current noise Custom compensation Constant bandwidth from G = to G = High speed MHz (G =