DPDT. How many SPDTs and how many DPDTs you think you need to control one light-bulb common to a 10-floor staircase. Total 11 switches.

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1 Exercise for fun: Explain how the two-way stair-case light control circuit works. 110V 2nd Floor Now complete the three-way stair-case light control circuit below. 1st Floor 110V PT 1st Floor 2nd Floor 3rd Floor PT Hint: Wire-up the PT so as to make a Straight/ross connection: Straight ross How many s and how many PTs you think you need to control one light-bulb common to a 10-floor staircase. Total 11 switches. 3 LEs (Light-Emitting iodes) LE is a non-linear device (see the V-I I 1.6V 10m RE characteristic). Since current increases steeply LE athode (-) node (+) once you cross the threshold voltage, we need a V current limiting resistance (example: 330 ohms resistance) wired in series with the LE. Sourcing method to drive an LE is not desirable. 74LS08 Voh (typ) = 3.4V 3.4V 1.9V urrent = = 4.5m 330Ω 4.5m exceeds I OHmax of 0.4m. Sinking method to drive an LE is preferred. 74LS Ω 330 Ω Typical V OL = 0.25V +5V 5.0V 1.9V 0.25V urrent = = 8.6m 330Ω 8.6m is not too far from I OLmax of 8.0m. 1/30/07 EE201L lass Notes - hapter #2 Page 32 / 40

2 Is a buffer better than an ordinary gate in driving an LE? (es/no). 74LS00 Ordinary Gate I OH max = -0.4m I OL max = 8.0m 74LS37 uffer Gate I OH max = -1.2m I OL max = 24.0m The buffer has (1/2/3) times drive capability compared to an ordinary gate. The buffer (also finds it difficult to / can easily) drive an LE in sourcing mode. So the best method to drive an LE is to use choice #. hoice #1:Use an ordinary gate s sourcing capability. hoice #2:Use an ordinary gate s sinking capability. hoice #3:Use a buffer gate s sourcing capability. hoice #4:Use a buffer gate s sinking capability. 4 Totem-pole output stage of a gate "TRNSISTOR" is the most basic element of all electronic circuitry. It has three legs: SE, OLLETOR and EMITTER. Shown on the side is a npn bipolar transistor. transistor acts like a switch in a digital circuit. It either conducts or does not conduct. If the SE is held at HIGH voltage, it conducts from collector to the emitter. ollector ase H Emitter S kω 900 Ω 50 Ω V 50 Ω V V (=5V) 50Ω V 3.5 kω 500 Ω 250 Ω Source Transistor Sink Transistor Source Sink =? =? 74S00 2-input NN from TI merican Indian Totempole Totem-pole output stage 1/30/07 EE201L lass Notes - hapter #2 Page 33 / 40

3 5 Open-collector output stage: Suppose you want to generate =. We know we can do like this. What happened if we do like this?? an we connect outputs of two gates together as shown? es / No 50 Ω V Source ON Sink OFF 50 Ω V Source OFF Sink ON Short ircuit??? 1/30/07 EE201L lass Notes - hapter #2 Page 34 / 40

4 To avoid conflict between the blowers and the vacuum pumps, let us remove the blowers! Well, the blowers are there originally for a reason. If we remove the blowers, who will create high pressure? Let us install a small (weak) blower on the common line. This blower is ON all the time. lso assume that it is specially designed so that it does not get overloaded. If any of the vacuum pumps is on, because the vacuum pump is much stronger than the small (weak) blower, the output pressure will be low. ut if both vacuum pumps are off, the small external blower will build-up the output pressure slowly to high pressure. y analogy, we remove the source transistors in the totem-pole output stage of the NN gates. The role of the external blower is held by the external pull-up resistance (usually 10Kohms) here. Such gates without source transistor are called "open-collector output gates" because the collector leg of the sink transistor is left "open" in the output-stage. V = 5V 10KΩ The wire-interconnection of the outputs of the open-collector gates is called WIRE-Ning, as it forms an imaginary N operation of the outputs it connects. Imaginary N gate formed by the wire-interconnection WIRE-Ning 1/30/07 EE201L lass Notes - hapter #2 Page 35 / 40

5 6 Exercise using the open-collector gates: 6.1 raw gate-level logic to produce G = ( + ) ( ) (E F) using as few gates as possible, using (a) Totem-pole output gates (b) Open-collector output gates Open-ollector 74LS01 74LS03 74LS05 74LS09 74LS12 74LS22 74LS33 Totem-pole 74LS00 74LS00 74LS04 74LS08 74LS10 74LS20 74LS02 74LS03 is pin-for-pin compatible with 74LS Find the logic function produced by the following logic. Point-out any errors. LS00 LS03 LS03 LS09 F 1 LS05 F 2 E 6.3 The following logic is built using totem-pole output gates. an you take advantage of WIRE- Ning in open-collector output gates and reduce the gate count (and there by cost)? LS00 LS08 LS11 F 3 E F G H LS02 LS00 LS08 F 4 1/30/07 EE201L lass Notes - hapter #2 Page 36 / 40

6 7 very common and useful application of open-collector gates in the design of systems with multiple add-on cards: 1/30/07 EE201L lass Notes - hapter #2 Page 37 / 40

7 8 Gates with Tristate outputs, Forming Tri-state buses: 1/30/07 EE201L lass Notes - hapter #2 Page 38 / 40

8 1/30/07 EE201L lass Notes - hapter #2 Page 39 / 40