High-Speed/Logic Gate Optocoupler (SFH67XX Series)

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1 Application Note High-Speed/Logic Gate Optocoupler (SFHXX Series) TRODUCTION The new SFHXX series of high-speed optocouplers is capable of transmitting data rates up to Mb/s typical and. Mb/s over the full specified operating temperature range. The combination of low input current (. ma) and active logic-level output is a fit for nearly all logic applications where a galvanic insulation is necessary. The SFHXX series features positive logic with TTL output levels. For improved noise immunity the detector incorporates a schmitt-trigger stage. The SFH00/9 provides an enable input, which allows switching the output into the high ohmic state for bus applications. For applications which need an open collector output, the SFH0 is offered.the SFH and SFH are the dual versions. The two channels are free of crosstalk and interference. To ensure a high common mode transient immunity of guaranteed. k/µs at 00, the SFHX/ series features an internal shield which consists of an additional ITO layer. The ITO (indium tin oxide) layer is an optically transparent but electrically conductive layer on top of the detector. The standard SFH0X series withstands.0 k/µs at CM = 0. The SFHXX series is also available in an SMD version (option and 9 with > mm creepage and clearance distance). SFH00/9 SFH0/ SFH0/ Three-State-put Totem-Pole-put Totem-Pole-put SFH0 SFH/ 0 Open-Collector-put Dual/Totem-Pole-put Fig. - ariations in the SFHXX Family TABLE LED ENABLE OUTPUT SFH00/9 On L H Off L L On H Z Off H Z SFH0/0/0//// On H Off L Truth table (positive logic) H = logic high level, L = logic low level, Z = high ohmic state DESIGN CONSIDERATIONS The circuits shown below are intended to give the design engineer a guideline for logic family interconnection. Input Circuitry Below are stated the most common interface circuits which work for this coupler series. Totem Pole Drive Circuits Figures and are two of the most commonly used circuits. The designer chooses R according to the equation: R OH F = I F (valid for Figure ) () For technical questions, please contact: optocoupler.answers@vishay.com Document Number: 0 0 Rev.., -Apr-0

2 High-Speed/Logic Gate Optocoupler (SFHXX Series) Application Note R DD OL F = I F (valid for Figure ) () SFH00/9 Due to the coupler s typically low input current threshold of 0.0 ma and the negative temperature gradient of the input current threshold (see figure ), the output leakage current of the driver element at high temperatures may become an issue in certain applications where the circuit is operated at the upper temperature range. For critical applications, where a high leakage current is expected, a shunt LED circuit, as shown in figure, is a good solution. LS TTL R Fig. - Series LED Drive SFH00/ T A - Temperature ( C) Normalized Input Current Threshold (%) R Fig. - Typical Input Current Threshold (Normalized) vs. Temperature Fig. - Series LED Drive A good compromise between low power dissipation and symmetrical propagation delays with respect to some guard band is I F = ma. In some applications a speed-up capacitor (typically around 00 pf) across R may be used to achieve faster switching times (please refer to the end of this section for details). R R SFH00/9 Fig. - Shunt LED Drive Circuit with Leakage Current Protection TABLE FIGURE GATE (E.G.) R ALUE LS0 0 Ω LS0 HCT0 Typical values for R at =.0 kω.0 kω Both circuits are simple and feature a minimal component count with low power dissipation. A logic source drive, as shown in figure, is not recommended due to speed and current limitations (especially in the logic family), and lower common mode transient immunity. The resistor R determines the forward LED current, and R shunts the LED. The choice of R depends on power dissipation considerations and the expected leakage current. The following equations can help designers determine the appropriate resistor values: R = Fmax(LEDoff) I Leak at Temp I Leakage F OL R = R F + I F R () () Document Number: 0 For technical questions, please contact: optocoupler.answers@vishay.com Rev.., -Apr-0 0

3 Application Note High-Speed/Logic Gate Optocoupler (SFHXX Series) TABLE I F R ALUE R ALUE ma.0 kω. kω Typical input circuit values to shunt around 0 µa away from the LED (according to figure ) A better way to handle leakage current is presented in figure. This circuit provides excellent speed properties and leakage current protection. The silicon diode D ensures that the current is only sourced by and is therefore not required for units driven by an open collector or open drain. The low forward voltage of D ensures that the LED stays off at logic low. The equation to choose R is: R DD F = I F R D Fig. - Logic Gate Shunt Drive Circuit Open Collector Drive Circuits A simple circuit, which also works for open collector drive circuits, has been presented in figures and. In figure, the resistor R represents a leakage current protection path. A more efficient but more power-dissipating solution is presented in figure. This drive circuit provides good speed and protection against leakage currents. The resistor R is chosen in accordance with SFH00/9 () Fig. - Open Collector/Drain Shunt Drive Circuit TABLE R I F R ALUE ma.0 kω 0 ma.0 kω ma. kω Typical input circuit values for a circuit according to figure Input Circuitry for Improved Switching Speeds If switching speed is a concern, the use of a speed-up capacitor is a good solution. The resistor R limits the peak transient current I Fpeak, whereas R and R determine the current at steady-state operation. The equations and reasonable resistor values are printed below. A reasonable value for the speed-up capacitor C S is 00 pf. Open Collector Drain C S R R Fig. - Series LED Drive with Speed-up Capacitor The equations for the resistor values are: SFH00/9 SFH00/9 R DD F = I F () R DD OL F = I Fpeak () Refer to table for some typical resistor values. Note that leakage protection generally might only be an issue in some special applications. R DD OL F = R I F The maximum I Fpeak for this transient is 0 ma for the SFHXX series. () For technical questions, please contact: optocoupler.answers@vishay.com Document Number: 0 0 Rev.., -Apr-0

4 High-Speed/Logic Gate Optocoupler (SFHXX Series) Application Note TABLE C S ALUE R ALUE R ALUE 00 pf.0 kω Ω Typical input circuit values for a circuit according to figure put Circuitry One advantage of the SFHXX series is its easy connection to any logic system, because of the active output stage (totem pole/three state output). Either directly or via a pull-up resistor, all couplers can drive up to LS TTL loads ( TTL loads) easily. In general, a 0. µf bypass capacitor is strongly recommended for proper operation. The SFH00/9 with its three-state output fits best in bus applications because of the possibility to switch the couplers output into the high ohmic state (for a typical setup please refer to figure ). Drive Circuits for the Dual-Channel Devices The SFH/ can be driven as simply as the single channel devices. All the above drive circuits and equations () to () can be adapted to drive the dual-channel devices. (The use of the dual-channel devices reduces the number of parts and the required board space.) Interfacing to TTL-Compatible Logic Interfacing the SFHXX coupler to LS TTL or any other compatible logic is quite simple. The active output of this coupler eliminates the need for an external pull up resistor, and minimizes parts count and board space requirements. The typical connection is seen in figure 9. Even HCT logic can be interfaced this way. 0 SFH0/ 0. µf LS TTL PUT Fig. 9 - Interfacing the Coupler to TTL, LSTTL or Compatible Logic Interfacing to Logic To ensure reliable logic switching, a pull-up resistor between the output and is recommended (see Figures and ). For the HCT logic family, this pull-up resistor may be omitted, due to the matching switching level of the coupler s output and the HCT input. There are three simple ways to connect logic to the SFHXX coupler family: Using SFHXX (totem pole) and a pull-up resistor (see figure ) Using SFH0 (open collector) and a pull-up resistor (see figure ) Using an HCT logic device (see figure 0) Using an HCT device is the simplest and most convenient solution to eliminate the external pull-up resistor (see figure 0). The designer doesn t have to worry about power consumption, rise times, or system speed. Fig. 0 - Interfacing to Logic Level via a HCT Device Using the open collector device, as in figure, requires an external pull-up resistor R P. To determine the correct value of this pull-up resistor, use following equations: where n I IL represents the total load current at low level OL. (To ensure OLmax < 0. over temperature I OLmax should be set not higher than. ma). The maximum R P value can be determined by: (9) (0) In applications however, where I IH is in the µa region, the limiting factor can also be determined by the maximum allowable rise time t r (00 ns for HC logic). The equation leads to SFH0/ R CCmax OLmin Pmin = I OLmax + n I IL R CCmin IHmin Pmin = I OHmax + n I IH t R P C L H = CC e 0. µf t R r Pmax = C L n IHmin CCmin HCT Input at Logic Level () () Document Number: 0 For technical questions, please contact: optocoupler.answers@vishay.com Rev.., -Apr-0 09

5 Application Note High-Speed/Logic Gate Optocoupler (SFHXX Series) in which C L represents the total capacitance of the load, including the coupler (which is around pf). The resistor value is a compromise between the requirement of power dissipation and switching speed. A low R P produces symmetrical and fast switching times but results in a higher power dissipation. Reasonable values are shown in table. Details of the relationship between the rise time t r and the pull-up resistor R P /load capacitance C L are shown in figure. SFH0 the delay time t d, but it strongly determines the rise time, especially for the open collector type. Interfacing to. Level Interfacing to the. logic families (e.g. AC, AHC, or HC) is quite easy, and presented in figure. If the totem pole/three-state coupler is operated with =, then the output high level of the coupler, which is then typically., matches perfectly with the. logic input levels. In general, the output high voltage can be determined by OH -.. (Even with =.0 ± 0 %, the output voltage is within the limits, and is guaranteed to be higher than. over temperature to fulfill the logic requirement). 0. µf Rp Input SFH0/.0.. Logic 9 Fig. - Interfacing SFH0 (Open Collector put) to Logic By using a totem pole device, the equations (9) and (0) are also valid, but the pull-up resistor has only to bring up the voltage difference between OH ( -. ) and the input switching limit, e.g.. for HC logic, which makes a Δ of 0.. This allows the use of a higher R P which results in lower power consumption. 0 SFH0/ 0. µf Input Fig. - Interfacing SFHXX (Totem Pole put) to Logic R P 0. µf Fig. - Interfacing to. Logic with = Interfacing to other Levels If shifting to any other level is intended (e.g.. logic, like the ALC or ALT series), the SFH0 with its open collector output is qualified. R P works as a pull-up resistor to ensure the proper logic high level. The basic principles are the same as described in the section interfacing to logic in equations (9) to (). Pull-Up Resistor Considerations for the Open Collector Type SFH0 As previously mentioned above, the pull-up resistor has to be chosen in accordance with the equations (9), (0), and (). Figure plots the expected rise time t r versus the time constant τ = R P x C L. Unlike the rise time t r, the fall time t f is mostly independent of R P and around ns. TABLE R P (OPEN COLLECTOR) R P (TOTEM POLE) 0 Ω.0 kω Typical values for R p by connecting to logic (according to figures and ). Note that generally the R P value has a negligible influence on For technical questions, please contact: optocoupler.answers@vishay.com Document Number: 0 00 Rev.., -Apr-0

6 High-Speed/Logic Gate Optocoupler (SFHXX Series) Application Note Rise Time, t r (ns) RC Time Constant (ns) Fig. - Typical Rise Time vs. Load for = (Test Circuit See Figure ) SFH9 (top layer) 0. µf (bottom layer) Fig. - Principle Board Layout for Enhanced CMTI (Fits to Schematic in Figure ) SFH0 0. µf R P = A circuit which enhances CMTI safety is shown in figure. The diode D is intended to sink parasitic current, which is caused by stray capacitance, away from the LED to prevent a false turn-on. Fig. - Test Circuit for Rise Time t r vs. Time Constant COMMON-MODE TRANSIENT IMMUNITY (CMTI) The SFH//9 feature a guaranteed common mode transient immunity (CMTI) of. k/µs at 00. This is achieved by using a faraday shield which is transparent to infrared light, but electrically conducting. This shield prevents the photodiode from being turned on by common-mode transients. In general there are some design rules to achieve a high CMTI. These recommendations are especially important for low LED drive current devices, like the SFHXX series: Connect the unused pins and to the virtually grounded input potential (either or ). Minimize stray capacitance. Avoid long distances between LED input circuit and coupler. Choose an appropriate high LED forward current to improve CM H (common mode transient immunity at logic high level). A layout which implements these hints is seen in figure. Note that this layout reduces creepage and clearance distance as well. CL I F tr Time D* R Fig. - Input Circuitry for Improved CMTI * Diode D : Any signaling diode Another input circuit for high CMTI is shown in figure. The transistor shunts the LED in the off-state and prevents a false turn on. This circuit tolerates very high common mode transients in the LED off-state. An improvement in the LED on-state can be reached by choosing a high I F current. For =, R is typically around. kω. SFH9 Document Number: 0 For technical questions, please contact: optocoupler.answers@vishay.com Rev.., -Apr-0 0

7 Application Note High-Speed/Logic Gate Optocoupler (SFHXX Series) RS R Q* * Transistor Q: Any switching transistor (e.g. N) Fig. - Input Circuitry for High CMTI A common way to achieve ultra-high CMTI is presented in figure 9. The balanced input impedance principle works with four resistors, R = R and R = R. R and R are used to minimize any noticeable LED current when the transistor is on. To achieve maximum performance, the stray capacitance from anode or cathode to the output side of the coupler has to be kept as low as possible. Reasonable values with Q = N are R = R = 0 Ω and R = R omitted. Note that R and R can be omitted, depending on the CE of the transistor Q. R* Q** Signal R* R* R* Fig. 9 - Balanced Input Impedance Circuitry * Resistor R = R and R = R : To achieve a balanced input impedance ** Transistor Q : Any switching transistor DYNAMIC OPERATION The SFHXX series of active pull-up outputs offer a guaranteed maximum propagation delay time of 00 ns over temperature and as well as a guaranteed. Mb/s data rate over temperature. Pulse Width Distortion Pulse width distortion (PWD) is defined as the difference between t PHL and t PLH (PWD = t PHL t PLH ). This value is important in applications where symmetrical switching times SFH9 SFH9 are required, e.g. in systems which are based on pulse width modulation. In transmission systems, the PWD should not exceed 0 % of the minimum propagation delay time. At I F =.0 ma LED forward current, the SFHxx has a typical PWD of around 0 ns over temperature, which corresponds to a maximum PWD of 0 %. Note that the use of a speed up capacitor decreases t PLH but might increase the PWD. Pulse Width Distor tion, PWD (ns) Temperature, T A ( C) Fig. 0 - Typical Pulse Width Distortion over Temperature at I F = ma (Test Circuit See Figure ) Propagation Delay Skew Propagation delay skew (t PSK ) is the difference between the minimum propagation delay, either t PHL or t PLH, and the maximum propagation delay, either t PLH or t PHL, between any SFHXX coupler under the same operation conditions. Propagation delay skew is therefore an important value for parallel data transmission, where synchronized data is needed. Propagation Delay Skew, t PSK (ns) T A - Temperature ( C) Fig. - Typical Propagation delay Skew over Temperature at I F = ma (Test Circuit See Figure ) In logic circuits, the overall PWD and t PSK are determined by all input and output logic gates in the signal path. To minimize the overall PWD, two identical couplers may be used as shown in figure. But the minimum PWD is achieved at the cost of a higher overall propagation delay. For technical questions, please contact: optocoupler.answers@vishay.com Document Number: 0 0 Rev.., -Apr-0

8 High-Speed/Logic Gate Optocoupler (SFHXX Series) Application Note SFH0/. kω k LS0 9. kω SFH0/ 0. µf Fig. Eye Pattern Diagram A typical eye pattern diagram for Mb/s data transmission is presented in figure. The eye pattern testing was done with a pseudo random data sequence (NRZ coding). 0. µf LS0 DESIGN IDEAS Optocouplers are commonly used as an interface between two circuits, where galvanic insulation is required, either to protect humans or sensitive electronic equipment. Based on this requirement, some designs are presented below, which use the SFHXX series. IGBT/IPM Driver The SFHXX series can be used as a fast driver for intelligent power modules (IPMs) using IGBT or MOSFET technology. The SFHXX optocoupler series provide level shifting and galvanic insulation and is therefore the ideal interface to the control logic. With its guaranteed minimum. k/µs at 00 common mode transient immunity, the SFHX also fulfills enhanced switching requirements. Switching Loads The SFHXX series can easily handle currents up to ma DC and voltages up to. Figures and show how it can handle loads which are beyond these limits. In figure, R is used as a pull-up resistor and the load current is handled and limited by the external transistor Q. Unlike figure, the schematic in figure is qualified to support both high voltages and currents. The power supply might be raised up to to achieve a proper GS voltage to turn the transistor fully on. The combination of the SFHXX series with logic level power transistors provides a fast-switching solution that helps to reduce parts count. 0 Fig. SFH0/ put Monitoring. k LS0 LS0 0. µf Input Monitoring Fig. Document Number: 0 For technical questions, please contact: optocoupler.answers@vishay.com Rev.., -Apr-0 0

9 Application Note High-Speed/Logic Gate Optocoupler (SFHXX Series) BAR Galvanic Insulation + + S IPM - Intelligent Power + H Module SFH IGBT/MOSFET Driver IGBT Module. kω HCT0 0. µf Protection/ Suppression Unit Fig. SFH SS Fig. * Transistor Q : Any n-channel enhancement-mode transistor ** Resistor R : R might be omitted, depending on the necessary GS of Q to turn Q fully on SFH 0.µF R** kω Q* LOAD BSP9 BUZ0SL BUZL SS Time Multiplexed Bus Line Access with Optical Insulation Barrier The schematic in figure shows the use of a common data bus line with independent data lines in time multiplexing mode. The -line to -line address decoder selects one of the data lines by enabling the output, whereas all the other outputs remain in the high ohmic state. Opto-Insulated DAC Interface When galvanic insulation in digital-to-analog-conversion or analog-to-digital-conversion systems is required, the SFHXX series is a good choice for an interface. Setups like the one in figure 9 provide a fast and part saving insulation barrier. The low propagation delay skew of the SFHXX devices makes them ideal for use in parallel data transfer. The SFHXX series provide an optimal interface solution for the SAB 0 C/C micro-controllers by supporting the Mb/s data rate at a 0 MHz CPU clock. kω Q* SP00T 0.µF LOAD Fig. * Transistor Q : Any p-channel enhancement-mode transistor For technical questions, please contact: optocoupler.answers@vishay.com Document Number: 0 0 Rev.., -Apr-0

10 High-Speed/Logic Gate Optocoupler (SFHXX Series) Application Note Galvanic Insulation Barrier SFH00/9 Common Bus. kω 0. µf Line HCT0 SFH00/9. kω 0. µf Line HCT0. kω SFH00/9 0. µf Y0 Y Y Y A B HCT9 -Line to -Line Decoder G Select Inputs Enable Line HCT0 Truth Table G B A Active on Bus Line H X X None (all high ohmic) L L L Line SFH00/9 L L H Line L H L Line. kω 0. µf L H H Line Line HCT0 Common Bus Fig. - Typical Setup for a Common Bus Line with Different Lines in Time Multiplex Mode Document Number: 0 For technical questions, please contact: optocoupler.answers@vishay.com Rev.., -Apr-0 0

11 Application Note High-Speed/Logic Gate Optocoupler (SFHXX Series) 0. µf SAB 0C Microcontroller** Synchronous Serial Channel (SSC)/SPI P./SCLK CLK P.9/MTSR FS D MAX Transformer Driver SD D HCT0* HCT0*. kω. kω Galvanic Insulation Barrier HALO TGM-00P Transformer SFH/ SFH0/ 0. µf xbaw Diodes 0. µf L0 +. µf CL SCLK D MAX Digital-to-Analog Converter 0. µf REFAB REFCD FBA OUTA FBB OUTB MAX FBC 0. µf. 0 kω 0 kω 0 kω 0 kω 0 kω Channel A 0... Channel B 0... PX.Y CS HCT0*. kω 0. µf CS DOUT UPO PDL D OUTC FBD OUTD A 0 kω 0 kω 0 kω Channel C 0... Channel D 0... Fig. 9 - Fully Galvanic Insulated Digital-to-Analog-Conversion System ( Channel DAC) * Inverter HCT0 is used to allow ma LED current ** Any CX micro-controller can be used For technical questions, please contact: optocoupler.answers@vishay.com Document Number: 0 0 Rev.., -Apr-0

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