SEMICONDUCTOR TECHNICAL DATA

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1 SEMIONDUTOR TEHNIL DT The programmable timer is a 4 stage binary ripple counter with 6 stages selectable by a binary code. Provisions for an on chip R oscillator or an external clock are provided. n on chip monostable circuit incorporating a pulse type output has been included. y selecting the appropriate counter stage in conjunction with the appropriate input clock frequency, a variety of timing can be achieved. 4 Flip Flop Stages Will ount From 0 to 4 Last 6 Stages Selectable y Four it Select ode 8 ypass Input llows ypassing of First Eight Stages Set and Reset Inputs lock Inhibit and Oscillator Inhibit Inputs On hip R Oscillator Provisions On hip Monostable Output Provisions lock onditioning ircuit Permits Operation With Very Long Rise and Fall Times Test Mode llows Fast Test Sequence Supply Voltage Range = 3.0 Vdc to 8 Vdc apable of Driving Two Low power TTL Loads or One Low power Schottky TTL Load Over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MXIMUM RTINGS* (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD D Supply Voltage 0.5 to V Vin, Vout Input or Output Voltage (D or Transient) 0.5 to VDD V Iin, Iout Input or Output urrent (D or Transient), per Pin ± m PD Power Dissipation, per Package 500 mw Tstg Storage Temperature 65 to + 0 TL Lead Temperature (8 Second Soldering) 60 * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/ From 65 To 5 eramic L Packages: mw/ From 0 To 5 LOK DIGRM LOK INH. 8 YPSS 7 6 L SUFFIX ERMI SE 60 ORDERING INFORMTION M4XXXP M4XXXL M4XXXDW P SUFFIX PLSTI SE 648 DW SUFFIX SOI SE 75G Plastic eramic SOI T = 55 to 5 for all packages. OS. INHIIT 4 IN 3 STGES THRU STGES 9 THRU VDD = PIN 6 VSS = PIN 8 9 D MONO IN DEODER MONOSTLE MULTIVIRTOR 3 DEODE REV 3 /94 MOTOROL Motorola, Inc. 995 MOS LOGI DT

2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELETRIL HRTERISTIS (Voltages Referenced to VSS) haracteristic Output Voltage Vin = VDD or 0 Vin = 0 or VDD 0 Level Level Input Voltage 0 Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or.0 Vdc) (VO = 3.5 or.5 Vdc) (VO = 0.5 or 4.5 Vdc) (VO =.0 or 9.0 Vdc) (VO =.5 or 3.5 Vdc) Level Output Drive urrent (VOH =.5 Vdc) Source (VOH = 4.6 Vdc) Pins 4 & 5 (VOH = 9.5 Vdc) (VOH = 3.5 Vdc) (VOH =.5 Vdc) Source (VOH = 4.6 Vdc) Pin 3 (VOH = 9.5 Vdc) (VOH = 3.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL =.5 Vdc) Sink Symbol VOL VOH VIL VIH IOH VDD Vdc Min Max Min Typ # Max Min Max Unit IOL Input urrent Iin ±0. ± ±0. ±.0 µdc Input apacitance (Vin = 0) in 7.5 pf Vdc Vdc Vdc Vdc mdc mdc mdc uiescent urrent (Per Package) Total Supply urrent** (Dynamic plus uiescent, Per Package) (L = 50 pf on all outputs, all buffers switching) IDD IT IT = (.50 µ/khz) f + IDD IT = (.30 µ/khz) f + IDD IT = (3.55 µ/khz) f + IDD #Data labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance. ** The formulas given are for the typical characteristics only at 5. To calculate total supply current at loads other than 50 pf: IT(L) = IT(50 pf) + (L 50) Vfk where: IT is in µ (per package), L in pf, V = (VDD VSS) in volts, f in khz is input frequency, and k = µdc µdc

3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITHING HRTERISTIS* (L = 50 pf, T = 5 ) Output Rise and Fall Time (Pin 3) ttlh, tthl = (.5 ns/pf) L + 5 ns ttlh, tthl = (0.75 ns/pf) L +.5 ns ttlh, tthl = (0.55 ns/pf) L ns Propagation Delay Time lock to, 8 ypass (Pin 6) High tplh, tphl = (.7 ns/pf) L + 7 ns tplh, tphl = (0.66 ns/pf) L + 67 ns tplh, tphl = (0.5 ns/pf) L + 45 ns haracteristic Symbol VDD Min Typ # Max Unit ttlh, tthl tplh, tphl ns ns lock to, 8 ypass (Pin 6) Low tplh, tphl = (.7 ns/pf) L + 37 ns tplh, tphl = (0.66 ns/pf) L ns tplh, tphl = (0.5 ns/pf) L + 75 ns lock to 6 tphl, tplh = (.7 ns/pf) L + 69 ns tphl, tplh = (0.66 ns/pf) L ns tphl, tplh = (0.5 ns/pf) L + 75 ns Reset to n tphl = (.7 ns/pf) L + 4 ns tphl = (0.66 ns/pf) L ns tphl = (0.5 ns/pf) L + 45 ns tplh, tphl tplh, tphl tphl lock Pulse Width twh lock Pulse Frequency (50% Duty ycle) lock Rise and Fall Time fcl ttlh, tthl Reset Pulse Width twh No Limit * The formulas given are for the typical characteristics only at 5. #Data labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance µs µs ns ns MHz ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. PIN SSIGNMENT 6 VDD MONO IN IN 3 4 OS INH 4 3 DEODE 5 D 8 YPSS 6 LOK INH 7 VSS 8 9 3

4 PIN DESRIPTIONS INPUTS (Pin ) high on Set asynchronously forces Decode Out to a high level. This is accomplished by setting an output conditioning latch to a high level while at the same time resetting the 4 flip flop stages. fter Set goes low (inactive), the occurrence of the first negative clock transition on IN causes Decode Out to go low. The counter s flip flop stages begin counting on the second negative clock transition of IN. When Set is high, the on chip R oscillator is disabled. This allows for very low power standby operation. (Pin ) high on Reset asynchronously forces Decode Out to a low level; all 4 flip flop stages are also reset to a low level. Like the Set input, Reset disables the on chip R oscillator for standby operation. IN (Pin 3) The device s internal counters advance on the negative going edge of this input. IN may be used as an external clock input or used in conjunction with and to form an R oscillator. When an external clock is used, both and may be left unconnected or used to drive LSTTL or several MOS loads. 8 YPSS (Pin 6) high on this input causes the first 8 flip flop stages to be bypassed. This device essentially becomes a 6 stage counter with all 6 stages selectable. Selection is accomplished by the,,, and D inputs. (See the truth tables.) LOK INHIIT (Pin 7) high on this input disconnects the first counter stage from the clocking source. This holds the present count and inhibits further counting. However, the clocking source may continue to run. Therefore, when lock Inhibit is brought low, no oscillator start up time is required. When lock Inhibit is low, the counter will start counting on the occurrence of the first negative edge of the clocking source at IN. OS INHIIT (Pin 4) high level on this pin stops the R oscillator which allows for very low power standby operation. May also be used, in conjunction with an external clock, with essentially the same results as the lock Inhibit input. MONO IN (Pin ) Used as the timing pin for the on chip monostable multivibrator. If the Mono In input is connected to VSS, the monostable circuit is disabled, and Decode Out is directly connected to the selected output. The monostable circuit is enabled if a resistor is connected between Mono In and VDD. This resistor and the device s internal capacitance will determine the minimum output pulse widths. With the addition of an external capacitor to VSS, the pulse width range may be extended. For reliable operation the resistor value should be limited to the range of 5 kω to 0 kω and the capacitor value should be limited to a maximum of 00 pf. (See figures 3, 4, 5, and ).,,, D (Pins 9,,, ) These inputs select the flip flop stage to be connected to Decode Out. (See the truth tables.) PUTS, (Pin 4, 5) Outputs used in conjunction with IN to form an R oscillator. These outputs are buffered and may be used for 0 frequency division of an external clock. DEODE (Pin 3) Output function depends on configuration. When the monostable circuit is disabled, this output is a 50% duty cycle square wave during free run. TEST MODE The test mode configuration divides the 4 flip flop stages into three 8 stage sections to facilitate a fast test sequence. The test mode is enabled when 8 ypass, Set and Reset are at a high level. (See Figure 8.) 4

5 TRUTH TLES Input Stage Selected 8 ypass D for Decode Out Input Stage Selected 8 ypass D for Decode Out FUNTION TLE In Set Reset lock Inh OS Inh Out Out Decode Out No hange dvance to next state X X X No hange X No hange X 0 No hange dvance to next state X = Don t are 5

6 LOGI DIGRM OS INHIIT 4 3 IN LOK INHIIT S En R T STGES THRU YPSS 6 T 9 9 D MONO IN STGES THRU 6 DEODER 3 DEODER 7 STGES 8 THRU 3 V DD = PIN 6 V SS = PIN 8 4 6

7 TYPIL R OSILLTOR HRTERISTIS (For ircuit Diagram See Figure In pplication) FREUENY DEVITION (%) 8.0 VDD = V V V R T = 56 kω, R S = 0, f =. V DD = V, T = 5 = 00 pf R S = 0 kω, f = 7.8 V DD = V, T = * Device Only. T, MIENT TEMPERTURE ( )* Figure. R Oscillator Stability f, OSILLTOR FREUENY (khz) f S FUNTION OF (RT = 56 kω) (RS = 0 k) VDD = V f S FUNTION OF RT ( = 00 pf) (RS RT) 0..0 k k 0 k.0 M RT, RESISTNE (OHMS) , PITNE (µf) Figure. R Oscillator Frequency as a Function of RT and MONOSTLE HRTERISTIS (For ircuit Diagram See Figure In pplication) t W, PULSE WIDTH ( µs) FORMUL FOR LULTING tw IN MIROSEONDS IS S FOLLOWS: tw = RX X 0.85 WHERE R IS IN kω, X IN pf. RX = 0 kω 50 kω kω 5 kω 0 X, EXTERNL PITNE (pf) T = 5 VDD = 5 V Figure 3. Typical X versus Pulse VDD = V 00 t W, PULSE WIDTH ( µs) FORMUL FOR LULTING tw IN MIROSEONDS IS S FOLLOWS: tw = RX X 0.85 WHERE R IS IN kω, X IN pf. RX = 0 kω 50 kω kω 5 kω T = 5 VDD = V 0 X, EXTERNL PITNE (pf) Figure 4. Typical X versus Pulse VDD = V 00 t W, PULSE WIDTH ( µs) FORMUL FOR LULTING tw IN MIROSEONDS IS S FOLLOWS: tw = RX X 0.85 WHERE R IS IN kω, X IN pf. RX = 0 kω 50 kω kω 5 kω T = 5 VDD = V 0 X, EXTERNL PITNE (pf) Figure 5. Typical X versus Pulse VDD = V 00 7

8 V DD 500 µf I D 0.0 µf ERMI PULSE GENERTOR 8 YPSS IN INH MONO IN OS INH D DEODE V SS 0 ns 0 ns 90% 50% % 50% DUTY YLE L L L Figure 6. Power Dissipation Test ircuit and Waveform PULSE GENERTOR 8 YPSS IN INH MONO IN OS INH D V DD DEODE V SS 0 ns 0 ns IN twl L 90% % 50% t PLH t TLH t THL Figure 7. Switching Time Test ircuit and Waveforms twh 50% t PHL FUNTIONL TEST SEUENE Test function (Figure 8) has been included for the reduction of test time required to exercise all 4 counter stages. This test function divides the counter into three 8 stage sections and 55 counts are loaded in each of the 8 stage sections in parallel. ll flip flops are now at a. The counter is now returned to the normal 4 stages in series configuration. One more pulse is entered into In which will cause the counter to ripple from an all state to an all 0 state. PULSE GENERTOR 8 YPSS IN INH MONO IN OS INH D V DD DEODE V SS FUNTIONL TEST SEUENE Inputs Outputs omments In Set Reset 8 ypass Decade Out thru Figure 8. Functional Test ircuit ll 4 stages are in Reset mode. 0 ounter is in three 8 stage sections in parallel mode. 0 0 First to 0 transition of clock to 0 transitions are clocked in the counter. 0 The 55 to 0 transition ounter converted back to 4 stages in series mode. Set and Reset must be connected together and simultaneously go from to In Switches to a ounter Ripples from an all state to an all 0 state. 8

9 +V 6 PULSE GEN. PULSE GEN. LOK 6 8 YPSS VDD D OS INH MONO IN LOK INH IN DEODE 3 VSS 8 IN LOK INH DEODE POWER UP NOTE: When power is first applied to the device, Decode Out can be either at a high or low state. On the rising edge of a Set pulse the output goes high if initially at a low state. The output remains high if initially at a high state. ecause lock Inh is held high, the clock source on the input pin has no effect on the output. Once lock Inh is taken low, the output goes low on the first negative clock transition. The output returns high depending on the 8 ypass,,,, and D inputs, and the clock input period. n frequency division (where n = the number of stages selected from the truth table) is obtainable at Decode Out. 0 divided output of IN can be obtained at and. Figure 9. Time Interval onfiguration Using an External lock, Set, and lock Inhibit Functions (Divide by onfigured) 9

10 +V PULSE GEN. LOK RX X YPSS VDD D LOK INH MONO IN LOK INH IN DEODE 3 VSS 8 IN DEODE POWER UP *tw *tw.0047 RX X0.85 tw in µsec RX in kω X in pf NOTE: When Power is first applied to the device with the Reset input going high, Decode Out initializes low. ringing the Reset input low enables the chip s internal counters. fter Reset goes low, the n/ negative transition of the clock input causes Decode Out to go high. Since the Mono In input is being used, the output becomes monostable. The pulse width of the output is dependent on the external timing components. The second and all subsequent pulses occur at n x (the clock period) intervals where n = the number of stages selected from the truth table. Figure. Time Interval onfiguration Using an External lock, Reset, and Output Monostable to chieve a Pulse Output (Divide by 4 onfigured)

11 +V 6 RS PULSE GEN. 6 8 YPSS VDD D LOK INH MONO IN LOK INH IN DEODE 3 VSS 8 RT DEODE POWER UP tw fosc.3rtc Rs Rtc F = Hz R = Ohms = FRDS NOTE: This circuit is designed to use the on chip oscillation function. The oscillator frequency is determined by the external R and components. When power is first applied to the device, Decode Out initializes to a high state. ecause this output is tied directly to the Osc Inh input, the oscillator is disabled. This puts the device in a low current standby condition. The rising edge of the Reset pulse will cause the output to go low. This in turn causes Osc Inh to go low. However, while Reset is high, the oscillator is still disabled (i.e.: standy condition). fter Reset goes low, the output remains low for n/ of the oscillator s period. fter the part times out, the output again goes high. Figure. Time Interval onfiguration Using On hip R Oscillator and Reset Input to Initiate Time Interval (Divide by onfigured)

12 LINE DIMENSIONS L SUFFIX ERMI DIP PKGE SE 60 ISSUE V T SETING PLNE F E G D 6 PL 0.5 (0.0) M T N S K L M J 6 PL 0.5 (0.0) M T S NOTES:. DIMENSIONING ND TOLERNING PER NSI Y4.5M, 98.. ONTROLLING DIMENSION: INH. 3. DIMENSION L TO ENTER OF LED WHEN FORMED PRLLEL. 4. DIMENSION F MY NRROW TO 0.76 (0.030) WHERE THE LED ENTERS THE ERMI ODY. INHES MILLIMETERS DIM MIN MX MIN MX D E 0 S.7 S F G 0.0 S.54 S H K L S 7.6 S M 0 0 N P SUFFIX PLSTI DIP PKGE SE ISSUE R 6 H 8 G F 9 D 6 PL S K 0.5 (0.0) M T SETING T PLNE M J L M NOTES:. DIMENSIONING ND TOLERNING PER NSI Y4.5M, 98.. ONTROLLING DIMENSION: INH. 3. DIMENSION L TO ENTER OF LEDS WHEN FORMED PRLLEL. 4. DIMENSION DOES NOT INLUDE MOLD FLSH. 5. ROUNDED ORNERS OPTIONL. INHES MILLIMETERS DIM MIN MX MIN MX D F G 0.0 S.54 S H 0 S.7 S J K L M 0 0 S

13 LINE DIMENSIONS DW SUFFIX PLSTI SOI PKGE SE 75G 0 ISSUE 6 9 6X D 4X G 0.0 (0.5) M T S S 8 K 8X P T SETING PLNE 0.0 (0.5) M J F M M R X 45 NOTES:. DIMENSIONING ND TOLERNING PER NSI Y4.5M, 98.. ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS ND DO NOT INLUDE MOLD PROTRUSION. 4. MXIMUM MOLD PROTRUSION 0. (0.006) PER SIDE. 5. DIMENSION D DOES NOT INLUDE DMR PROTRUSION. LLOWLE DMR PROTRUSION SHLL E 0.3 (0.005) TOTL IN EXESS OF D DIMENSION T MXIMUM MTERIL ONDITION. MILLIMETERS INHES DIM MIN MX MIN MX D F G.7 S 0 S J K M P R Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should uyer purchase or use Motorola products for any such unintended or unauthorized application, uyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/ffirmative ction Employer. How to reach us: US/EUROPE/Locations Not Listed: Motorola Literature Distribution; JPN: Nippon Motorola Ltd.; Tatsumi SPD JLD, 6F Seibu utsuryu enter, P.O. ox 09; Phoenix, rizona or Tatsumi Koto Ku, Tokyo 35, Japan MFX: RMFX0@ .sps.mot.com TOUHTONE SI/PIFI: Motorola Semiconductors H.K. Ltd.; 8 Tai Ping Industrial Park, INTERNET: NET.com 5 Ting Kok Road, Tai Po, N.T., Hong Kong /D 3

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