pss InGaAs channel MOSFET with self-aligned source/drain MBE regrowth technology solidi status physica

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1 Phys. Status Solidi C 6, No. 6, (2009) / DOI /pss physia pss InGaAs hannel MOSFET with self-aligned soure/drain MBE regrowth tehnology urrent topis in solid state physis Uttam Singisetti *1, Mark A. istey 1,2, Gregory J. Burek 1, Erdem Arkun 2, Ashish K. Baraskar 1, Yanning Sun 3, Edward. Kiewra 3, Brian J. Thibeault 1, Arthur C. Gossard 1,2, Chris J. Palmstrøm 1,2, and Mark J.. Rod 1 1 ECE University of California, Santa Barbara, CA, USA 2 Materials Departments, University of California, Santa Barbara, CA, USA 3 IBM T.J. atson Researh Center, Yorktown Heights, NY, USA Reeived 13 September 2008, aepted 2 January 2009 Published online 20 April 2009 PACS Kp, Ea, Hi, Tv * Corresponding author: uttam@ee.usb.edu, Phone: , Fax: InGaAs is a promising alternative hannel material to Si for sub-22 nm node tehnology beause of its low eletron effetive mass (m * ) hene high eletron veloities. e report a gate-first MOSFET proess with self-aligned soure/drain formation using non-seletive MBE re-growth, suitable for realizing high performane saled III-V MOSFETs. A // gate stak was defined on thin (4 nm/2.5 nm) In- GaAs/InP hannel by an alternating seletive dry eth tehnique. A 5 nm Al 2 O 3 layer was used as gate dieletri. An InAlAs bottom provided vertial onfinement of the hannel. An in-situ H leaning of the wafer leaves an epiready surfae suitable for MBE or MOCVD regrowth. Soure/Drain region were defined by non-seletive MBE regrowth and in situ molybdenum ontats. First generation of devies fabriated using this proess showed extremely low drive urrent of 2 µa/µm. The drive urrent was limited by an extremely high soure resistane. A regrowth gap between soure/drain and gate was the ause for high soure resistane. The gap in the regrowth was beause of low growth temperature (400 ºC). A modified high temperature growth tehnique resolved the problem. Si is expeted to reah the saling limit beyond 22 nm gate node mainly due to the inability to ahieve low leakage sub-0.5 nm equivalent oxide thikness (EOT) gate dieletris. Also, sub-22 nm gate length and sub-1 nm EOT Si devies annot realize omplete ballisti transport, hene not ahieving the full potential drive urrents [1]. High eletron veloity III-V materials are investigated as an alternative hannel to Si in N-MOSFETs. In x Ga 1-x As (x 0.53) is a leading andidate as a hannel material beause of its low eletron effetive mass (m * ) and high saturation veloities (v). Also the large inter-valley separation in In 0.53 Ga 0.47 As (InGaAs) redues inter-valley sattering, blanket metal oxide InGaAs hannel InP subhannel SI substrate (starting material) Ti/ gate blanket gate deposition Figure 1 Overall proess flow. eth gate, eth dieletri eth upper hannel sidewall formation S/D regrowth S/D ontats sidewall mesa isolate S/D

2 Contributed Artile Phys. Status Solidi C 6, No. 6 (2009) 1395 so eletron veloities remain high even at high eletri fields. The main obstale of unpinned interfaes to high-k dieletri on InGaAs have been addressed by several groups with various high-k dieletris [2-4]. However these devies either have long gate lengths or were not saled vertially. The full potential of InGaAs hannel devies an only be realized in MOSFETs whih are saled both horizontally and vertially. e report the design and proess flow development of a self-aligned InGaAs MOSFET using MBE regrown soure/drain (S/D) regions. Detailed MOSFET saling laws and sub-22 nm III-V FET design are disussed in referenes [1, 5, 6]. Lateral saling of the gate length to 22 nm ditates a vertial saling of the devie. At sub-22 nm gate lengths, a maximum of 1 nm EOT dieletri and 5 nm thik hannel with strong vertial onfinement are required for maximum transondutane (g m ) and aeptably low drain indued lowering (DIBL). e use In 0.52 Al 0.48 As (InAlAs) heterojuntion to ahieve this onfinement. An alternative approah using eletrostati onfinement would need high p + doping in the InGaAs hannel, whih would redue the hannel mobility beause of impurity sattering and will also degrade the short hannel effets due to disrete dopant flutuations. In sub-22 nm devies, the devie parasiti apaitanes dominate and limit the iruit delay [1, 5]. The IC delay (τ) an be redued only through high drive urrent (I d ) and high g m. InGaAs MOSFETs are expeted to ahieve very high drive urrents (5 ma/μm) and transondutanes (7 ms/μm) beause of high thermal veloities (J = qnv) [1, 5, 6]. These urrent levels are ahieved at a sheet onentration of ~ m -2. Large intervalley separation (E Γ L, E Γ X = 0.5 ev) in InGaAs makes it possible to ahieve these densities without populating the slower satellite valleys. Furthermore, soure aess resistane plays an important role in saled devies beause it degrades the available I d and g m from the devie. Even a very low soure aess resistane of 15 Ω-μm would degrade I d by 10% [5]. This value is an order of magnitude smaller than the ITRS roadmap listed soure aess resistane of 180 Ω-μm [7]. IC layout density requirement would onstrain L = L g = 22 nm, whih means a speifi ontat resistivity ρ = 0.25 Ω- μm 2 orresponding to 10 Ω-μm resistane. A 4 Ω-μm S/D extension aess resistane translates into a high m -3 ative doping in these regions. Besides soure resistane, high doping onentrations is required in S/D to avoid soure starvation [6]. Unlike Si, ion implantation is not a viable tehnique for InGaAs due to various diffiulties. There is no data showing the apability of implantation realizing these high ative onentrations and ontat resistane values. Instead we are using MBE to regrow S/D regions after gate formation. Ative Si doping ~ m -3 and low ontat resistane of 0.5 Ω-μm 2 have Poly-InGaAs Gate Figure 2 SEM of Poly-InGaAs regrowth. been demonstrated by MBE and in-situ molybdenum (Mo) ontats [8]. Saled sub 50 nm Shottky FETs (HEMTs) with 1 nm EOT have been reported but have not been able to ahieve the high simulated drive urrents [9]. HEMTs have non-salable soure resistane beause of the high bandgap under the S/D ontats [10]. The Shottky gate also has a higher gate leakage urrent than dieletris do, making it unsuitable for VLSI appliations. The details of the proess flow are provided below, but the general flow is as follows. As shown in Fig. 1, the gate was defined first by a salable dry eth proess rather than by traditional III-V lifoff tehniques. The high-k dieletri was wet ethed and gate was enapsulated in a SiN sidewall, followed by InGaAs soure/drain regrowth by moleular beam epitaxy (MBE). Self-aligned ontats were defined by a blanket metal deposition and a heightseletive eth, then the devies were mesa isolated. e shall now disuss these steps in greater detail. First, a omposite InGaAs (4 nm)/inp (2.5 nm) hannel and 100 nm of InAlAs bak was grown by MBE on semi-insulating InP. Then the wafer was ooled to 50 ºC and apped with 100 nm of As. The wafer was unloaded and transferred to an Atomi Layer Deposition (ALD) hamber, then the As ap was desorbed, and 5 nm of Al 2 O 3 dieletri was grown immediately. Next, the blanket gate stak (50nm)/(50nm)/ (300nm)/(50nm) was deposited. For these devies, the gate dieletri is diretly on top of the thin hannel, without any intentional intermediate layers. This imparts a onsiderable proessing hallenge as thin layers are prone to damage during dry ethes. A damaged hannel layer would result in imperfet S/D regrowth, whih leads to high soure resistanes. Also, any pinhole introdued in the hannel beause of the dry eth would expose and oxidize the underlying InAlAs layer. This would again ause defet ridden S/D regrowth and high resistanes. Figure 2 shows the faeted and resistive poly-ingaas whih results from regrowth on a damaged hannel.

3 physia p s s 1396 U. Singisetti et al.: InGaAs hannel MOSFET with self-aligned soure/drain MBE regrowth tehnology SF 6 / Ar eth 50 SF 6 / Ar resist Cl 2 / O 2 eth mask Cl 2 / O 2 eth stop gate metal dieletri KOH wet eth Al 2 O 3 ( ) InGaAs InP SI substrate FIB oss-setion Damage free hannel Dry eth sheme Figure 3 Dry eth sheme and FIB rosssetion SEM image of a gate. Therefore a multiple layer gate stak and alternating seletive dry eth sheme was developed (Fig. 3). The top layer was used as a dry eth mask after patterning it with photoresist and i-line photolithography, followed by a Cl 2 /O 2 dry eth. The was removed before the hannel was exposed. Next, before the was ethed, the photoresist was stripped and O 2 plasma ethed; the proteted the hannel from damage, and the aggressive O 2 eth prevented organi ontamination of the MBE hamber. The alternating seletive dry eth sheme (Fig. 3) allows a final low power dry eth of the layer without damaging the hannel. The Al 2 O 3 dieletri was wet ethed in dilute KOH solution. As a result, 300 nm long and 400 nm thik gate staks were fabriated on 4 nm InGaAs hannel. The proess an be easily used to fabriate sub-50 nm features by using eletron beam lithography. A 45 nm, onformal layer of SiN x was deposited over the gates by PECVD, and a low power anisotropi eth was performed to remove the SiN x from the far field, leaving defined sidewalls. The final // struture with SiN x sidewalls leaves the metals unexposed in the MBE hamber during regrowth avoiding any possible metal ontamination. The InGaAs hannel was seletively wet ethed, stopping on the InP sub-hannel, and an overeth was done to eth a small amount InGaAs under the SiN x sidewall. Next the wafer was treated with 30 minute UV-Ozone forming a 1 nm sarifiial oxide. It was followed by 1 minute 1:10 HCl:DI treatment to remove the oxide, 1 minute DI rinse, and blown dry in N 2. Then it was immediately loaded into MBE hamber and baked overnight at 200 ºC. The wafer was atomi hydrogen leaned at 400 ºC for 30 minutes. A (2 4) surfae reonstrution was seen in refletion high energy eletron diffration (RHEED) before regrowth, indiating an epi-ready surfae. Using this leaning proedure, defet free epitaxial InGaAs films were regrown on InGaAs and showed low sheet and ontat resistanes [11]. A 25 nm/ 5 nm InGaAs/ InAs with m -3 ative Si doping was grown non-seletively at 400 C. Then the wafer was then transferred to an eletron beam evaporator attahed to the MBE under ultra high vauum, and 20 nm of Mo was deposited. Both the InGaAs regrowth and Mo are deposited over the top of the gate, shorting the soure to the drain. To remove the undesired material, the wafer was planarized by spinning photo-resist and ashed bak in an indutively oupled O 2 plasma (ICP) until the tops of the gates were exposed. Then the Mo was dry ethed in a SF 6 /Ar plasma, and the InGaAs layers were wet ethed [11, 12]. The PR was stripped to give a self-aligned S/D MOSFET. Next S/D pads were lifted-off, and devies were mesa isolated and measured by needle probe. A shemati of the saled InGaAs MOSFET is given in Fig. 4. The self-aligned S/D regrowth ensures the soure resistane does not degrade from surfae state indued depletion [13]. The RHEED was spotty during the regrowth on the MOSFET wafer, whih indiated a rough surfae. e attribute this to InP to InAs onversion during the initial N + soure InP N + drain Mo Figure 4 oss-setion shemati of final devie. stage of regrowth. [14] The highly strained InAs layer relaxed, and the subsequent InGaAs growth beame rough. This phenomenon was onfirmed by the failure of the seletive Arsenide wet eth to stop on the InP layer after regrowth. Spotty RHEED and rough InGaAs regrowth were

4 Contributed Artile Phys. Status Solidi C 6, No. 6 (2009) 1397 Drain Current (µa) L =10µm, =50µm g g V =0 to 2 V, V step = 0.25 V gs gs Vds (Volts) Figure 5 Measured I d -V d of the MOSFET. also observed on unproessed wafers with thin InP but with no gates. A similar rough surfae was observed even in hemial beam epitaxy (CBE) growth. This onfirmed A sanning eletron mirosope (SEM) image of the devie showed a nm gap between the n + regrowth regions and the gate. Similar gaps in regrowth were observed on o-proessed wafers with gates but without highk (Fig. 6). The gap is most likely due to shadowing by the gate during MBE regrowth and/or by a thin (nm) layer of SiN x remaining on the surfae near the gate even after the sidewall eth. The gap was also observed in proess monitor wafers on whih no sidewall was deposited. e attribute this to shadowing by the tall gate features as as redued surfae mobility of group III adatoms at the growth temperature (400 ºC). As a result, the hannel surfae next to gate is starved of group III elements, resulting in a gap. ithout the high doping from regrowth, the hannel in the gap region is depleted of all eletrons beause of the pinning of Fermi-level below the ondution band edge due to surfae states. Furthermore a large underut in Al 2 O 3 dieletri an introdue an additional depleted region between the hannel and the soure. Figure 7 shows // gate N + regrowth Gap Gap in regrowth InGaAs regrowth InP Figure 6 SEM and shemati image showing a gap in regrowth. that the problem was a growth related issue, rather than proess related ontamination. Transmission line measurements (TLM) on the regrowth layer gave a high sheet resistane of 310 Ω μm and a ontat resistane of 130 Ω μm 2. A soure resistane of 300 Ω μm was expeted from the TLM data. A low sheet resistane of 28 Ω μm and ontat resistane of 9 Ω μm 2 were measured on a oproessed wafer with no high-k and no InP, onfirming the possibility of high quality regrowth on a proessed wafer. e attribute the higher resistane observed in the MOS- FET wafer to relaxation and rough growth on the thin InP layer. Figure 5 shows the output harateristis of a 10 µm gate length devie. The maximum drive urrent is ~ 2 μa/μm at V gs = 2.0 V and V ds = 2.0 V. Similar low drive urrents were observed for the shorter gate length devies. The I d -V g haraterstis showed an extremely high soure resistane limited linear behavior with R s ~ kω. The on resistane is orders of magnitude higher than the value alulated from the TLM strutures. I d -V ds of a devie where the InGaAs hannel was not ethed. The breakdown voltage is 8 V onsistent with an InGaAs breakdown of 20 V/μm [15] for total S/D to gate gap of 400 nm as seen in SEM. Thus we believe the low drive urrents resulted from the undoped gaps in regrowth. The two main reasons for the high soure resistane are the inability to re-grow low resistane epitaxial InGaAs on thin InP sub-hannel, and a gap region with no regrowth next to the gate. Instead of the thin InP layer, introduing a 2 nm strained In 0.88 Ga 0.12 P (InGaP) sub-hannel eth stop layer allowed suessful regrowth of low resistane In- GaAs [11]. A high temperature migration enhaned epitaxy (MEE) regrowth tehnique showed no gaps next to the gate [16]. Furthermore, a 5-10 nm thik SiN x sidewall tehnology is being developed. This would mean a 5-10 nm lateral extension under sidewall, so the MBE regrowth would only need to fill in a horizontal void with a 1:1 or 1:2 aspet ratio. In summary, we developed a salable, self-aligned, III- V MOSFET proess with MBE S/D regrowth. The gate

5 physia p s s 1398 U. Singisetti et al.: InGaAs hannel MOSFET with self-aligned soure/drain MBE regrowth tehnology I d (µa) 1200 L = 10 µm =10 µm V =0.0 V g V (V) ds Figure 7 Breakdown haraterstis of the MOSFET. proess and H leaning leave a 5 nm thik, lean, undamaged, epi-ready hannel surfae suitable for MBE or MOCVD regrowth. orking devies were fabriated with this proess. The devies show low drive urrent beause of undoped gaps between the S/D and the gate in the early devies. Improved high temperature S/D growth tehniques have been developed and will be used in the next generation of devies. Aknowledgements e gratefully aknowledge Semiondutor Researh Corporation (SRC) for supporting this work. Referenes [1] P.M. Solomon and S. Laux, IEEE IEDM Teh. Dig. 2001, pp [2] Y. Sun et al., 66th DRC, Santa Barbara, 2008, pp [3] S. Koveshnikov et al., 66th DRC, Santa Barbara, 2008, pp [4] Y. Xuan et al., 66th DRC, Santa Barbara, 2008, pp [5] M. J. Rod, M. istey, U. Singisetti, G. Burek et al., 20th IEEE IPRM, [6] M.V. Fishetti et al., IEEE IEDM Teh. Dig., 2007, pp [7] International Tehnology Roadmap of Semiondutor, Front End Proesses, 2007, p. 21. [8] U. Singisetti et al., 65th DRC, Notre Dame, 2007, pp [9] D.-H. Kim et al., IEEE IEDM Teh. Dig., 2005, pp [10] T. Takahashi et al., 19th IEEE IPRM, 2007, pp [11] M. A. istey et al., Eletroni Materials Conferene, 2008, p. Z4. [12] G.J. Burek et al., J. yst. Growth, 2008, submitted for publiation. [13] T. Suemitsu et al., Jpn. J. Appl. Phy. 37, (1998). [14] M.A.istey et al., in preparation. [15] Yu.A. Goldberg and N. M. Shmidt, Handbook Series on Semiondutor Parameters, Vol. 2 (orld Sientifi, London, 1999), pp [16] M. A. istey et al., 15th Int. Conf. on Moleular Beam Epitaxy, Vanouver, Canada, Aug. 2008, p 199.