Website: vlsicad.ucsd.edu/ courses/ ece260bw05. ECE 260B CSE 241A Power Distribution 1

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1 ECE260B CSE241A Winter 2005 Power Distribution Website: / courses/ ece260bw05 ECE 260B CSE 241A Power Distribution 1

2 Motivation Power supply noise is a serious issue in DSM design Noise is getting worse as technology scales Noise margin decreases as supply voltage scales Power supply noise may slow down circuit performance Power supply noise may cause logic failures ECE 260B CSE 241A Power Distribution 2

3 Power = Routing resources Pins 20-40% of all metal tracks used by Vcc, Vss Increased power denser power grid Vcc or Vss pin carries 0.5-1W of power Pentium 4 uses 423 pins; 223 Vcc or Vss More pins package more expensive (+ package development, motherboard redesign, ) Battery cost 1kg NiCad battery powers a Pentium 4 alone for less than 1 hour Vcc Vss Vcc Vss Vcc Performance High chip temperatures degrade circuit performance Large across-chip temperature variations induce clock skew High chip power limits use of high-performance circuits Power transients determine minimum power supply voltage ECE 260B CSE 241A Power Distribution 3

4 Power = Package Pentium 4 die is about 1.5g and less than 1cm^3 Pentium-4 in package with interposer, heat sink, and fan can be 500g and 150cm^3 Fan Heat Sink Integrated Heat Spreader Decoupling Capacitors Interposer Processor Processor Pins OLGA Pins Package Pins Modern processor packaging is complex and adds significantly to product cost. ECE 260B CSE 241A Power Distribution 4 Courtesy M. McDermott UT-Austin

5 Planning for Power Early simulation of major power dissipation components Early quantification of chip power - Total chip power - Maximum power density - Total chip power fluctuations inherent & added fluctuations due to clock gating Early power distribution analysis (dc, ac, & multi-cycle) I.e., average, maximum, multi-cycle fluctuations Early allocation & coordination of chip resources - Wiring tracks for power grid - Low Vt devices - Dynamic circuits - Clock gating - Placement and quantity of added decoupling capacitors ECE 260B CSE 241A Power Distribution 5

6 Power and Ground Routing Floorplanning includes planning how the power, ground and clock should route Power supply distribution Tree: trunk must supply current to all branches Resistance must be very small since when a gate switches, its current flows through the supply lines - If the resistance of supply lines is too large, voltage supplied to gates will drop, which can cause the gate to malfunction - Usually, want at most 5-10% IR drop due to supply resistance Usually on the top layers of metal, then distributed to lower wiring layers ECE 260B CSE 241A Power Distribution 6

7 Planar Power Distribution Topology of V DD /V SS networks. Inter-digitated Design each macrocell such that all V DD and V SS terminals are on opposite sides. If floorplan places all macrocells with V DD on same side, then no crossing between V DD and V SS. V DD V DD V DD cell cut line V SS V SS V SS B V DD no cut line V SS V DD A V DD VSS V SS C V DD cut line V DD V SS no connection V SS ECE 260B CSE 241A Power Distribution 7 Courtesy K. Yang, UCLA

8 Gridded Power Distribution With more metal layers, power is striped Connection between the stripes allows a power grid - Minimizes series resistance Connection of lower layer layout/cells to the grid is through vias - Note that planar supply routing is often still needed for a strong lower layer connection. - There may not be sufficient area to make a strong connection in the middle of a design (connect better at periphery of die) ECE 260B CSE 241A Power Distribution 8 Courtesy K. Yang, UCLA

9 Power Supply Drop/ Noise Supply noise = variations in power supply voltage that act as noise source for logic gates Power supply wiring resistance voltage variations with current surges Current surges depend on dynamic behavior of circuit Solution approach Measure maximum current required by each block Redesign power/ground network to reduce resistance Worst case: move activity to another clock cycle to reduce peak current scheduling problem Example: Drive 32-bit bus, total bus wire load = 2pF, with delay 0.5ns R for each transistor needs to be < 0.25kΩ to meet RC = 0.5ns Effective R of bits together is 250/32 = 7.5Ω For < 10% drop, power distribution R must be < 1Ω ECE 260B CSE 241A Power Distribution 9 Courtesy K. Yang, UCLA

10 Electromigration Physical migration of metal atoms due to electron wind can eventually create a break in a wire MTTF (mean time to failure) 1/J 2 where J= current density Current density must not exceed specification wire I i /w i < J spec Specified as ma per µm wire width (e.g., 1mA/ µm) or ma per via cut EM occurs both in signal (AC=bidirectional) and power wires (DC = unidirectional) Much worse for DC than AC; DC occurs inside cells and in power buses May need more contacts on transistor sources and drains to meet EM limits Width of power buses must support both ir and EM requirements Issues in IR and EM constraint generation Topology is most likely not a tree How do we determine current patterns? ECE 260B CSE 241A Power Distribution 10 Effects of R, L

11 What Happens? Example of an AlCu line seen under microscope. Accelerated by higher temperature and high currents Voids form on grain boundaries Metal atoms move with current away from voids and collect at boundaries Catastrophic failure ECE 260B CSE 241A Power Distribution 11 Courtesy K. Yang, UCLA

12 Taken from Taken from Sverre Sjøthun, Electromigration In-Depth, from ECE 260B CSE 241A Power Distribution 12 Courtesy S. Sapatnekar, UMinn

13 Power Supply Rules of Thumb Rules depend on technology Tech file has rules for resistance and electromigration Examples: Must have a contact for each 16λ of transistor width (more is better) Wire must have less than 1mA/µm of width Power/Gnd width = Length of wire * Sum (all transistors connected to wire) / 3*10 6 λ (very approximate) For small designs, power supply design is non-issue ECE 260B CSE 241A Power Distribution 13 Courtesy K. Yang, UCLA

14 Basic Methodology Concepts Reliability (slotting, splitting) Alignment of hierarchical rings, stripes Isolation of analog power Styles of power distribution Rings and trunks Uniform grid Bottom-up grid generation Depends on: - Package: flip-chip vs. wire-bond; I/O count (fewer pads denser grid) - Power budget - IR drop limits - Floorplan constraints (hard macros, etc.) ECE 260B CSE 241A Power Distribution 14

15 Metal Slotting vs. Splitting Required by metal layout rules for uniform CMP (planarization) Split power wires Less data than traditional slotting More accurate R/C analysis of power mesh Not supported by all tools M1 Easy connections through standard via arrays M1 GND GND GND GND Difficult to connect - where should vias go? ECE 260B CSE 241A Power Distribution 15 Courtesy Cadence Design Systems, Inc.

16 Trunks and Rings Methodology Each Block has its own ring Rings may be inside the blocks or part of the top level Each Block has trunks connecting top level to block Rings may be shared with abutted blocks V G V G V G V block 5 block 4 G block 1 block 3 V block 2 G V G V Individual trunks connecting blocks to top level G V G V G V ECE 260B CSE 241A Power Distribution 16 Courtesy Cadence Design Systems, Inc.

17 Trunks and Rings Advantages Power tailored to the demands of each block (flexible) More area efficient since the demands of each block are uniquely met Simple implementation supported by many tools Rings can be shared between blocks by abutted blocks Disadvantages Limited redundancy, power grid built to match needs Assumptions in design may change or be invalid Non regular structure requires more detailed IR drop/em analysis missing vias/connections fatal Rings will require slotting/splitting due to wide widths Increase in data volume ECE 260B CSE 241A Power Distribution 17 Courtesy Cadence Design Systems, Inc.

18 Uniform Chip Grid Methodology Robust and redundant power network mainly in microprocessors and high end large ASICs Implementation Primary distribution through upper metal layers - Lower layers in blocks to connect to top through via stacks Typically pushed into blocks Blocks typically abut - Requires block grids to align Rows/Followpins should align with block pins - Global buffer insertion global grid higher layers V G V G V G G V Fine or custom grid or no grid on lower layers G V block 5 block 4 block 4 block 1 block 3 V G V G V G V G V ECE 260B CSE 241A Power Distribution 18 Courtesy Cadence Design Systems, Inc.

19 Uniform Chip Grid Advantages Easily implemented Lends itself to straightforward hand calculations Path redundancy allows less sensitively to changes in current pattern Mesh of power/ground provides shielding (for capacitance) and current returns (for inductance) Top-down propagation easy to use on this style Disadvantages Takes up significant routing resources (20%-40% of all routing tracks if not already reserved for power/ground) Fine grids may slow down P&R tools Imposes grid structure into each block which may be unnecessary Top and blocks coupled closely if top level routing pushed into blocks Changes to block/top must be reflected in other ECE 260B CSE 241A Power Distribution 19 Courtesy Cadence Design Systems, Inc.

20 Bottom-Up Grid Generation Methodology Design and optimize power grid for block, merge at top Advantages Able to tailor grid for routing resource efficiency in each block Flexibility to choose the best grid for the block (i.e. ring and stripe, power plane, grid) Disadvantages Designing grid in context of the big picture is more difficult Block grid may present challenging connections to top level Assumptions for block grid s connection to top level must be analyzed and validated ECE 260B CSE 241A Power Distribution 20 Courtesy Cadence Design Systems, Inc.

21 Power Routing in Area-Based P&R Power routing approaches (1) Pre-route parts of power grid during floorplanning (2) Build grid (except connections to standard cells) before P&R (3) Build entire grid before P&R N.B.: Area-based P&R tools respect pre-routes absolutely Cadence tools: power routing done inside SE, all other tasks (clock, place, route, scan, ) done by point tools Lab 5 tomorrow has a tiny bit of power routing (rings, stripes) Miscellany ECOs: What happens to rings and trunks if blocks change size? Layer choices: What is cost of skipping layers (to get from thick top-layer metal down to finer layers)? How wide should power wires be? Post-processing strategies ECE 260B CSE 241A Power Distribution 21 Courtesy Cadence Design Systems, Inc.

22 Power Routing Wire Width Considerations Slotting rules: Choose maximum width below slotting width Halation (width-dependent spacing) rules: Do as much as possible of power routing below wide wire width to save routing space Choose power routing widths carefully to avoid blocking extra tracks (and, use the space if blocking the track!) What is better power width here? Blocked tracks ECE 260B CSE 241A Power Distribution 22 Courtesy Cadence Design Systems, Inc.

23 Power Routing Tool Usage 4 layer power grid example (HVHV) Turn on via stacking Route metal2 vertically Route metal4 vertically (use same coordinates) Route metal3 horizontally (make coincident with every N metal1 routes) Turn off via stacking Route metal1 horizontally metal2/metal4 coincident metal1 inside cells metal3 every n micron ECE 260B CSE 241A Power Distribution 23 Courtesy Cadence Design Systems, Inc.

24 Post-Processing Flows (DEF or Layout Editing) During PnR After post processing ECE 260B CSE 241A Power Distribution 24 Courtesy Cadence Design Systems, Inc.

25 (Tree) Supply Network Design Tree topology assumption not very useful in practice, but illustrates some basic ideas Assume R dominates, L and C negligible marginally permissible assumption Current drawn at various points in the tree (time-varying waveform) Current causes a V=IR drop Ground is not at 0V Vdd is not at intended level Supply ECE 260B CSE 241A Power Distribution 25 Courtesy S. Sapatnekar, UMinn = sinks

26 IR Drop Constraints Chowdhury and Breuer, TCAD 7/88 Can write V drop to each sink as Supply Σ R i I i < V spec for all sink current patterns made available Tree structure: can compute I i easily R i α ρ l i / w i Change w i to reduce IR drop Objective: minimize Σ a i w i Current density must never exceed a specification For each wire, I i /w i < J spec ECE 260B CSE 241A Power Distribution 26 Courtesy S. Sapatnekar, UMinn

27 P/G Mesh Optimization (R only) Dutta and Marek-Sadowska, DAC 89 2 Cost function: Σ a i l i w i = Σ a i c i l i // = total wire area (since c i = conductance = w i /(ρ l i ) Constraints - EM: I i κ e w i // current density I/w less than upper bound Substitute I i = v i (w i / ρ l i ) // I = V/R v p - v q κ e ρ l i // divide by w i, * ρ l i - Wire width constraints: W min w i W max (translate to c i ) - Voltage drop constraints: v a - v b V spec1 and/or v i V spec2 - Circuit equations that determine the v s ECE 260B CSE 241A Power Distribution 27 Courtesy S. Sapatnekar, UMinn

28 Solution Technique Method of feasible directions Find an initial feasible solution (satisfies all constraints) Choose a direction that maintains feasibility Make a move in that direction to reduce cost function Given a set of c i s, must find corresponding v i s Feasible direction method: move from point c* to c + c* and c + must be close to each other (i.e., if you have the solution at c*, the solution at c + corresponds to a minor change in conductances) Solving for v i s : solving a system of linear equations - Solution at c* is a good guess for the solution at c + - Converges in a few iterations ECE 260B CSE 241A Power Distribution 28 Courtesy S. Sapatnekar, UMinn

29 Modeling Gate Currents Currents in supply grid caused by charging/discharging of capacitances by logic gates All analyses require generation of a worst-case switching scenario Enumeration is infeasible Two basic approaches Simulation based methods: designer supplies hot vectors, or we try to generate these hot vectors automatically Pattern-independent methods: try to estimate the worst-case (can be expensive, very inaccurate) Once current patterns are available, apply them to supply network to find out if constraints are satisfied ECE 260B CSE 241A Power Distribution 29 Courtesy S. Sapatnekar, UMinn

30 Complexity of Hot Vector Generation Devadas et al., TCAD 3/92: Assume zero gate delays for simplicity Find the maximum current drawn by a block of gates Using a current model for each gate - Find a set of input patterns so that the total current is maximized - Boolean assignment problem: equivalent to Weighted Max- Satisfiability Given a Boolean formula in conjunctive normal form (product of sums), is there an assignment of truth values to the variables such that the formula evaluates to True? - Checking for Satisfiability (for k-sat, k > 2) is NP-complete Difficult even under zero gate delay assumption ECE 260B CSE 241A Power Distribution 30 Courtesy S. Sapatnekar, UMinn

31 Pattern-Independent Methods imax approach: Kriplani et al., TCAD 8/95 Current model for a single gate I peak Delay Gates switch at different times Total current drawn from V dd (ignoring supply network C) is the sum of these time-shifted waveforms Objective: find the worst-case waveform ECE 260B CSE 241A Power Distribution 31 Courtesy S. Sapatnekar, UMinn

32 Example (Not to scale!) Maximum current not just a sum of individual maximum currents Temporal dependencies [Using deliberate clock skews can reduce the peak current, as we saw in the Useful-Skew discussion] ECE 260B CSE 241A Power Distribution 32 Courtesy S. Sapatnekar, UMinn

33 Maximum Envelope Current (MEC) Find the time interval during which a gate may switch Manufacturing process variations can cause changes Actual switching event can cause changes (unit gate delays) Switching at second gate can occur at t=1 or at t=2 In general, a large number of paths can go through a gate; assume (conservatively) that switching occurs in t [1,2] Assume that all gate inputs can switch independently provides an upper bound on the switching current ECE 260B CSE 241A Power Distribution 33 Courtesy S. Sapatnekar, UMinn

34 (Large) Errors in MEC Approach Correlation Problem Switching at G0, G1, G2 and G3 not independent G0 = 0 implies that G1, G2, G3 switch; G0 = 1 means that other inputs will determine gate activity If the other inputs cannot make the gate switch in the same time window, then imax estimates are pessimistic G0 G1 G2 G3 Reconvergent Fanout Problem Signals that diverge at G0 reconverge at Gk inputs to Gk are not independent G1 Assumption of independent switching is not valid G0 G2 Gk Many heuristic refinements proposed, but guardbanding (error) of power estimation still a huge issue ECE 260B CSE 241A Power Distribution 34 Courtesy S. Sapatnekar, UMinn G3

35 Outline Motivation Power Supply Noise Estimation Decoupling Capacitance (decap) Budget Allocation of Decoupling Capacitance Experiment Results Conclusion ECE 260B CSE 241A Power Distribution 35

36 Why Decoupling Capacitance Frequency point of view Decaps form low-pass filters They cancel anti- effects Physical point of view Decaps serve as charge reservoirs They shortcut supply current paths and reduces voltage drop No effect to DC supply currents ECE 260B CSE 241A Power Distribution 36

37 Power Supply Network RLC Mesh :Current Source : VDD pin Lp VDD Rp VDD VDD VDD ECE 260B CSE 241A Power Distribution 37 Slide courtesy of S Zhao, K Roy & C.-K. Kok

38 Current Distribution in Power Supply Mesh Illustration :Connection point, VDD (1) :VDD pin Current contribution (3) Current flowing path (5) VDD (2) (6) Module A B C ECE 260B CSE 241A Power Distribution 38 Slide courtesy of S Zhao, K Roy & C.-K. Kok

39 Current Distribution in Power Supply Network Distribute switching current for each module in the power supply mesh Observation: Currents tend to flow along the leastimpedance paths Approximation: Consider only those paths with minimal impedance --shortest, second shortest, I 1 I 2 I n =I Z 1 I 1 =Z 2 I 2 = =Z n I n I j = Y j n i =1 Y i I, j=1,2, n ECE 260B CSE 241A Power Distribution 39 Slide courtesy of S Zhao, K Roy & C.-K. Kok

40 Current Flowing Paths and Power Supply Noise Calculation Power supply noise at a target module is the voltage difference between the VDD pin and the module Apply KVL: i3(t) VDD R1 L1 C1 i1(t) R2 L2 C2 k i 2(t) V k di noise = i j R P L j P P j T k jk j k dt ECE 260B CSE 241A Power Distribution 40 Slide courtesy of S Zhao, K Roy & C.-K. Kok

41 Why Decoupling Capacitance? i3(t) VDD R1 L1 C1 R2 L2 k i1(t) C2 i 2(t) P/G network wiresizing won t change voltage drop frequency spectrum To reduce Vdrop by k times needs to size up wires by k times along the supply current path Decoupling caps act as a low-pass filter Efficient to remove high frequency elements of Vdrop ECE 260B CSE 241A Power Distribution 41

42 Decoupling Capacitance Budget Decap budget for each module can be determined based on its noise level Initial budget can be estimated as follows: Ch arg e : Q k = 0 I k t dt k Noise ratio : =max 1, V noise V lim noise Decap : lim C k = 1 1 Q k /V noise, k =1,2, M Iterations are performed if necessary until noise at each module in the floorplan is kept under certain limit ECE 260B CSE 241A Power Distribution 42 Slide courtesy of S Zhao, K Roy & C.-K. Kok

43 Allocation of Decoupling Capacitance Decap needs to be placed in the vicinity of each target module Decap requires WS to manufacture on Use MOS capacitors Decap allocation is reduced to WS allocation Two-phase approach: Allocate the existing WS in the floorplan Insert additional WS into the floorplan if required ECE 260B CSE 241A Power Distribution 43 Slide courtesy of S Zhao, K Roy & C.-K. Kok

44 Allocation of Existing White Space A w2 WS B D w1 C E w3 ECE 260B CSE 241A Power Distribution 44 Slide courtesy of S Zhao, K Roy & C.-K. Kok

45 Allocation of Existing WS--Linear Programming (LP) Approach Objective: Maximize the utilization of available WS Existing WS can be allocated to neighboring modules using LP Notation: S : sum of allocated WS S k : area of WS k S j : decap budget of mod j x k j : ws allocated to mod j from WS k N k : neighbors set of WS k LP Approach: H max imize S = k =1 s.t. k = H k =1 j x k S k, j N k x k j 0, x k j S j, j x k, j N k j, k k =1,2,, H j=1,2,, M ECE 260B CSE 241A Power Distribution 45 Slide courtesy of S Zhao, K Roy & C.-K. Kok

46 Insert Additional WS into Floorplan If Necessary Update decap budget for each module after existing WS has been allocated If additional WS if required, insert WS into floorplan by extending it horizontally and vertically Two-phase procedure: insert WS band between rows based the decap budgets of the modules in the row insert WS band between columns based on the decap budgets of the modules in the column ECE 260B CSE 241A Power Distribution 46 Slide courtesy of S Zhao, K Roy & C.-K. Kok

47 Moving Modules to Insert WS Original floorplan 0 A C 2 B D ExtY Moving modules in y+ direction A C B D WS band E G F E F G (a) (b) ECE 260B CSE 241A Power Distribution 47 Slide courtesy of S Zhao, K Roy & C.-K. Kok

48 Experimental Results Comparison of Decap Budgets (Ours vs Greedy Solution ) Circuit decap budget (nf) (our method) decap budget (nf) ( greedy solution ) Percentage (%) apte xerox hp ami ami playout ECE 260B CSE 241A Power Distribution 48

49 Experimental Results for MCNC Benchmark Circuits Circuit Modules Existing WS (µm 2 ) (%) apte (1.6) xerox (5.5) hp (7.8) ami33 ami (21.3) (7.0) playout (6.6) decap Budget (nf) Inacc. WS (µm 2 ) (%) Added WS (µm 2 ) (%) (0) (10.3) (0) (2.7) (3.5) (3.4) Est. Peak Noise (V) before N/A (2.5) (0.9) (1.3) (4.0) Est. Peak Noise (V) after ECE 260B CSE 241A Power Distribution 49

50 Floorplan of playout Before/ After WS Insertion ECE 260B CSE 241A Power Distribution 50

51 Conclusion A methodology for decoupling capacitance allocation at floorplan level is proposed Linear programming technique is used to allocate existing WS to maximize its utilization A heuristic is proposed for additional WS insertion Compared with Greedy solution, our method produces significantly smaller decap budgets ECE 260B CSE 241A Power Distribution 51

52 ECE 260B CSE 241A Power Distribution 52