Charge Controlled Meminductor Emulator

Transcription

1 JOURNAL OF SEMICONDUCOR ECHNOLOGY AND SCIENCE, VOL.4, NO.6, DECEMBER, 04 Charge Controlled Memductor Emulator Mahehwar Pd. Sah,, Ram Kaji Budhathoki, Changju Yang, and Hyonguk Kim,* Abtract Emulation of memritor-family element are very important, ce their phyical realization are very difficult to achieve with recent technologie. Although ome previou tudie ucceeded deigng memritor and memcapacitor emulator, no ignificant contribution toward memductor emulator ha been preented o far. he implementation of a memductor emulator i very important, ce real memductor are not expected to appear near future. We deigned the firt memductor emulator whoe ductance can be varied by an external current ource without employg any memriitve ytem. he prciple of our architecture and it feaibility have been verified ug SPICE imulation. Index erm Pched hyterei loop, memritor, memcapacitor, memductor, emulator I. INRODUCION Memritor, memcapacitor, and memductor are the three major element of the memritor-family. hey are paive circuit element that tore formation the form of reitance, capacitance, and ductance, repectively []. Although, thee three element are promig for the implementation of memory maller than conventional ilicon memorie, they are not expected to be available the market near future. Utilizg emulator might be eential for the Manucript received May., 04; accepted Sep., 04 Diviion of Electronic and Information Engeerg and Intelligent Robot Reearch Center, Chonbuk National Univerity, Jeonju, Jeonbuk, Republic of Korea Department of Computer Science and Engeerg, Univerity of Notre Dame, Indiana, USA Correpondg Author, Hyonguk Kim, hkim@jbnu.ac.kr development of application circuit of memritor-family element. hough there i active reearch on memritor and memcapacitor emulator [, 3], there are not many tudie on memductor. he contribution toward memductor are only confed to build mathematical model, pice macro model, and the tranformation of memritive ytem to memcapacitve and memductive ytem ug mutator [4-8]. However, the mathematical model and pice macro model are only ueful for imulation and cannot be ued for phyical implementable circuit. Similarly, the memductor built an direct way by employg mutator i complicated and lead to difficulty employg memductor application circuit. In thi paper, we propoe the firt imple and dedicated memductor emulator that doe not require any mutator to tranform memritor to memductor. he feature of the propoed memductor ha been verified via PSPICE circuit imulation. II. PROPOSED MEMIDUCOR EMULAOR he relationhip between the put current (i ) and flux (φ) the charge-controlled memductor i defed a: j = L ( q) i () M where L M (q) i the memductance of a memductor. he baic idea to build a memductor emulator i by compog the put ductance a a function of put current. Fig. (a) and (b) how the baic concept and it equivalent circuit repectively to deign a memductor emulator. In Fig. (a), the relationhip between put current i and flux φ generated acro ductor L i given a:

2 JOURNAL OF SEMICONDUCOR ECHNOLOGY AND SCIENCE, VOL.4, NO.6, DECEMBER, v L i L L v (a) - R f i Fig.. Baic concept of propoed memductor emulator (a) Input ductance a a function of voltage v, (b) Equivalent circuit. (b) whoe ductance i variable dependg upon the tegration of the put current. An analog memductor to emulate v (3) i contructed ug a capacitor, a reitor, an analog multiplier, and a voltage differentiator, a hown Fig. (a). In Fig. (a), an ductor and feedback voltage v are connected acro the put termal and the non-vertg termal of OPAMP U 0, repectively. he put current i can be expreed term of the ductor voltage v L and feedback voltage v a: j = L i ò v dt () where v i the voltage acro the non-vertg termal of the OPAMP circuit. If the tegration of v () i compoed proportion to the put current i, then: ò where v dt mi = ( ) j = L m) i (3). Eq. (3) implie that the memductance of the charge-dependent memductor i defed a ( L m). If m i controlled by the time tegral of i, then the circuit of Fig. act a a memductor i = ( vl - v ) dt L ò (4) he replica of poitive and negative current are generated ug NMOS and PMOS current mirror and proceed eparately at different part of the circuit []. A hown Fig. (a), the poitive part of the current, duplicated by a current mirror MN0 and MN i fed to a reitor R and a capacitor C by current mirror MP3 and MP4 with couple of MP repectively. On the other hand, MP0 and MP act a the negative part of current mirror that flow out from reitor R and capacitor C by current mirror MN3 and MN4 with MN couple tranitor, repectively. he capacitor C our emulator Fig. Architecture of propoed memductor (a) Propoed memductor emulator circuit, (b) Symbol of the memductor.

3 75 Mahehwar Pd. Sah et al : CHARGE CONROLLED MEMINDUCOR EMULAOR tored programmed formation the form of charge. he buffer U avoid the dichargg durg the period when an put ignal doe not exit. he voltage acro capacitor C i the tegration of mirrored current i, and the voltage acro R i proportional to the mirrored current i. Let v C and v R be the voltage acro C and R, repectively. hen, ( ) q vc = i t dt C ò = (5) C v = i R (6) R where q = ò i dt i the charge acro capacitor C. A four-quadrant analog multiplier AD633 perform analog multiplication between voltage v c and v R repectively [9]. It clude high impedance, differential X and Y put, and high impedance ummg put (W). he output and put relation of thi multiplier i given by, ( X - X - )( Y -Y- ) Z = W (7) 0 From Fig. (a), the output voltage v mul of a voltage multiplier AD633 i given by: R vmul = q i (8) he output voltage v mul i fed to a differentiator compoed of C D, R D, and OPAMP U3. he output voltage v of the differentiator circuit can be expreed a: R RD CD d v = - [ q i ] dt (9) From (4) and (8), we get: æ R RD C ö D j = ç L - q i è ø (0) Eq. (0) decribe the operation of the memductor circuit, which the memductance of the memductor i: L ( q) = L - a q () M 5 where 0 current (µa) (a) L M (H) φ(mwb) (c) R RD CD a =. (b) flux (0.mWb) i(µa) i (µa) III. SIMULAION RESULS t(m) Fig. 3 Variou waveform meaured acro our memductor emulator (a) Input current, flux with repect to time t, (b) Memductance (L M ) v. current (i), (c) Pched hyterei loop on φ v. i plane φ (mwb) f=40 Hz f=00 Hz f=300 Hz PSPICE imulation wa performed to verify the performance of the preented memductor emulator. he parameter ued for the imulation are ±5 V power upply, C =0. μf, R =4 KΩ, L =80 H, C D =0.8 μf, and 30 i (µa) Fig. 4. Pched hyterei loop obtaed with the propoed memductor emulator for variou frequencie.

4 JOURNAL OF SEMICONDUCOR ECHNOLOGY AND SCIENCE, VOL.4, NO.6, DECEMBER, R D =00 KΩ. One of the characteritic of a memductor i a zero crog pched hyterei loop under the φ veru i plane for any bipolar periodic ignal. hi feature wa verified the propoed memductor emulator for a uoidal put current ignal with a frequency of 00 Hz and amplitude of 5 μa. he put current ignal and the correpondg waveform of the flux meaured acro our memductor emulator are hown the Fig. 3(a). Fig. 3(b) and (c) are the correpondg variation of memductance with repect to the applied put current (i) and the pched hyterei loop on the φ veru i plane, repectively. Oberve that the loci on the φ veru i plane for the put ignal exhibit zero crog pched hyterei loop a expected. Another characteritic of memductor i the frequency dependency of the pched hyterei loop. he hape of the pched hyterei loop decreae a the frequency of the put ignal creae. In our emulator circuit, the variation of flux (φ) and memductance (L M ) depend on the charge (q) tored the capacitor. If the frequency of the put ignal i low, then the rate of change of q acro capacitor i wide and vice vera. herefore, the flux φ defed (0) will be wider for low frequency and narrow for high frequency ignal. In order to verify the pched hyterei fgerprt of a memductor circuit, we carried out the imulation of the propoed circuit at 40 Hz, 00 Hz, and 300 Hz for a uoidal current ignal with amplitude of 5 µa. Oberve that, all of the φ veru i curve have a zerocrog, and the hape of the pched hyterei loop are hrunken a the frequency creae. All the pched hyterei loop of the propoed memductor emulator atify the required fgerprt of a device to be memductor. IV. CONCLUSION We preented a dedicated memductor emulator without employg any memriitve device. he PSPICE imulation of the propoed architecture confirmed that our emulator atifie all the criteria for a memductor circuit. Sce olid-tate memductor circuit are not expected to appear the near future, our propoed memductor emulator could be an expenive and imple olution to develop memductor application circuit. ACKNOWLEDGMENS hi work wa upported part by National Reearch Foundation of Korea(NRF) funded by the Korea government Grant No. 03RAAA and Grant No. 0RAA REFERENCES [] L. Chua, An Introduction to Memritor, IEEE Expert Now Coure, 009. [] H. Kim, M. P. Sah, C. Yang, S. Cho, and L. O. Chua, Memritor Emulator for Memritor Circuit Application, Circuit and Sytem-I, IEEE ran. on, vol. 59, no.0, pp. 4-43, Oct. 0. [3] M. P. Sah, C. Yang, R. K. Budhathoki, H. Kim, and H. J. Joo, Implementation of a Memcapacitor Emulator with Off-the Shelf Device, Journal of Electronic and Electrical Engeerg, vol. 9, no. 8, pp , Oct. 03. [4] Z. Hu, Y. Li, L. Jia, and J. Yu, Chaotic Ocillator Baed on Current-Controlled Memductor, International Conference on Communication, Circuit and Sytem (ICCCAS), pp , July 00. [5] D. Biolek, Z. Biolek, and V. Biolkova, PSPICE Modelg of Memductor, Analog Integrated Circuit and Signal Proceg, vol. 66, no., pp. 9-37, Jan. 0. [6] Y. V. Perh, and M. Di Ventra, Emulation of Floatg Memcapacitor and Memductor ug Current Conveyor, Electronic Letter, vol. 47, no. 4, pp , Feb. 0. [7] M. P. Sah, R. K. Budhathoki, C. Yang, and H. Kim, Expandable circuit of mutator-baed memcapacitor emulator, International Journal of Bifurcation and Chao (IJBC), vol. 3, no. 5, pp () (7), May 03. [8] M. P. Sah, R. K. Budhathoki, C. Yang, and H. Kim, Mutator-Baed Memductor Emulator for Circuit Application, Circuit Sytem Signal Proceg Sprger, vol. 33, no. 8, pp , March 04. [9] data_heet/ad633.pdf

5 754 Mahehwar Pd. Sah et al : CHARGE CONROLLED MEMINDUCOR EMULAOR Mahehwar Pd. Sah received the B.E. Electronic and Communication Engeerg from Pokhara Univerity, Nepal 005, M.E. and Ph.D Electronic Engeerg from Chonbuk National Univerity, Republic of Korea 00 and 03 repectively, where he worked a a pot-doctoral cholar from 03 to 04. He i currently workg a a Potdoctoral cholar at Univerity of Notre Dame, Indiana, USA. Hi ma reearch teret clude Emergg ranitor echnology, Circuit deign, Cellular Neural Network, Analog viterbi decoder, analyi of Memritor and Memritive Sytem. Ram Kaji Budhathoki received the B.E degree Electrical and Electronic Engeerg from Kathmandu Univerity, Nepal 00. He received M.E. degree from Pokhara Univerity, Nepal 009. He joed Nepal Engeerg College (nec), Nepal, 00 and ha been an Aitant Profeor at nec ce 007. He i curently workg toward the Ph.D degree at the Diviion of Electronic Engeerg, Chonbuk National Univerity, South Korea. Hi current reearch teret clude circuit deign and analyi of memritor and memritive ytem. Changju Yang received the B.S and M.S. degree Electronic and Information Engeerg from Chonbuk National Univerity Korea 008 and 00 repectively, where he i currently tudyg toward the Ph.D. degree Electronic and Information Engeerg. Hi ma reearch teret clude Circuit deign, Analog viterbi decoder, analyi of Memritor and Memritive Sytem Hyonguk Kim received the Ph.D. degree Electrical Engeerg from the Univerity of Miouri, Columbia, 99. Sce 993, he ha been a Profeor with the Diviion of Electronic Engeerg, Chonbuk National Univerity, Republic of Korea. From 000 to 00 and aga from 009 to 00, he wa with the Nonlear Electronic Laboratory, EECS Department, Univerity of California, Berkeley, a a Viitg Scholar. Hi current reearch teret clude memritor and it application to Cellular Neural/ Nonlear Network.