A Parallel-Connected High Voltage Multiplier for Non-Thermal Food Processing

Transcription

1 7th nternational Conference on Electrical, Electronic an Civil Engeerg (CEECE'05) June 7-8, 05 Pattaya (hailan) A Parallel-Connecte High oltage Multiplier for Non-hermal Foo Proceg Kei Eguchi, Kanji Abe, Shya eraa, an chirou Oota Abtract n thi paper, a parallel-connecte high voltage multiplier i proe for non-thermal foo proceg utilizg an unerwater hockwave. he proe multiplier conit of two itive multiplier block an two negative multiplier block. n the proe multiplier, thee multiplier block are operate opite larity. By connectg thee block parallel, the proe multiplier provie a high teppe-up voltage at high pee, the put voltage acro the put capacitor i generate by combg the put of thee multiplier block. Concerng the proe multiplier with ix tage, imulation program with tegrate circuit emphai (SPCE) imulation an theoretical analyi ug a four-termal equivalent circuit are performe. he reult of thi tuy are a follow: ) Settlg time of the proe voltage multiplier i le than 50m when the put capacitance i 0μF an ) the theoretical reult are goo agreement with SPCE imulate reult. he erive theoretical equation are effective to etimate the wer efficiency an put voltage of the proe multiplier. Keywor Cockcroft-alton multiplier, High pee multiplier, Non-thermal foo proceg, Parallel-connecte multiplier.. NODUCON ECENLY, non-thermal foo proceg [] i attractg much attention. Ang other, we focu on non-thermal foo proceg utilizg an unerwater hockwave [], a high-voltage electric icharge i ue a the ource of the hock wave. For thi reaon, everal type of high-voltage generator have been proe. Ang other, one of the t fau high-voltage generator i the Cockcroft-alton voltage multiplier (CM) []-[5]. n pat tuie, qbal proe a ymmetrical CM ug a cacae rectifier circuit [] an Bear et al. uggete a bilar CM [5]. Unlike a high voltage tranformer with high turn ratio, the CM can elimate the requirement for the heavy core. However, ue to the electrical impeance of capacitor lower tage, the put voltage of the CM beg to ag accorg to the Kei Eguchi i with the Department of nformation Electronic, Fukuoka ntitute of echnology, -0- ajirohigahi, Higahi-ku, Fukuoka, Japan ( phone: ; fax: ; eguti@fit.ac.jp). Kanji Abe i with the Department of nformation Electronic, Fukuoka ntitute of echnology, -0- ajirohigahi, Higahi-ku, Fukuoka, Japan ( mam500@bene.fit.ac.jp). Shya eraa i with the Department of Control an nformation Sytem Engeerg, Kumato National College of echnology, 659-, Suya, Kouhi, Kumato, Japan ( teraa@kumato-nct.ac.jp). chirou Oota i with the Department of nformation an Communication, Kumato National College of echnology, 659-, Suya, Kouhi, Kumato, Japan ( oota-i@kumato-nct.ac.jp). creae of the number of tage. Furtherre, the pee of the conventional CM []-[5] i low, becaue the ioe witch i controlle by a uoial waveform upplie by a commercial wer ource. n the non-thermal foo proceg utilizg an unerwater hockwave, the CM which exhibit not only high tep-up ga but alo high rene pee i eirable to cruh har foo. n thi paper, a parallel-connecte high voltage multiplier i proe for non-thermal foo proceg utilizg an unerwater hockwave. he proe multiplier conit of two itive multiplier block an two negative multiplier block. n the proe multiplier, thee multiplier block are connecte parallel an are operate opite larity. By combg the put voltage of thee multiplier block, a high put voltage acro the put capacitor i generate. Furtherre, by controllg ioe witche by two-phae rectangular pule, the proe voltage multiplier can achieve high pee operation. o confirm the valiity of the proe multiplier, imulation program with tegrate circuit emphai (SPCE) imulation an theoretical analyi ug a four-termal equivalent circuit are performe concerng the proe multiplier.. CCU CONFGUAON A. Conventional oltage Multiplier Fig. how the Cockcroft-alton voltage multiplier (CM) with N tage (N=,, ) []. By convertg a uoial waveform upplie by a commercial wer ource, the conventional multiplier generate the followg voltage: N.,, th N () n (), i the maximum value of an AC put voltage an th i the threhol voltage of the ioe witch. A Fig. how, the conventional CM can realize the imple circuit contitution. However, the pee of the conventional CM i low, becaue the frequency of electric current i 50 Hz Eatern Japan an 60 Hz etern Japan. Fig. Conventional Cockcroft-alton voltage multiplier

2 7th nternational Conference on Electrical, Electronic an Civil Engeerg (CEECE'05) June 7-8, 05 Pattaya (hailan) proe multiplier. n Fig., the ioe witch i ele by an ieal witch, an on-reitance on, an a threhol voltage ource th. n the teay tate, the ifferential value of electric charge C pk, C pk, C mk, an C mk (k=,, N) atifie the followg equation: pk q 0, pk q 0, mk q i 0, i i i i an mk i 0 i i q, k,,, N () Fig. Proe voltage multiplier B. Proe oltage Multiplier Fig. how the proe voltage multiplier. he proe multiplier conit of four voltage multiplier block: two itive multiplier block an two negative multiplier block. Firt, the AC ignal AC i full-wave rectifie by a full-wave rectifier. hen, the non-overlappe two-phae rectangular pule an are generate by ug the full-wave rectifie voltage. A Fig. how, the proe multiplier ha four tate: State-, State-, State-, an State-. Fally, by controllg ioe witche by an, the proe multiplier provie the followg teppe-up voltage:, () th an N N th. N,, N N n (), i the put voltage of the itive multiplier block an i the put voltage of the negative multiplier block. n the proe multiplier, the parameter N i et to ix to generate an put voltage ab.5k. Owg to high pee rectangular pule an parallel-connecte tructure, the proe multiplier can achieve high pee operation. Furtherre, the number of tage of the proe multiplier i ab a half of that of the conventional CM hown Fig.. herefore, the proe multiplier can alleviate the ag of the put voltage. Δq pk i an Δq pk i (i=,,, ) enote electric charge of the k-th capacitor of the itive voltage multiplier block the cae of State- i. On the other han, Δq mk i an Δq m i enote electric charge of the k-th capacitor of the negative voltage multiplier block the cae of State- i. he terval of State- i atifie the followg conition: an, () i the perio of clock pule an δ i the parameter to eterme the time of State- an State-. n State-, the ifferential value of electric charge the put an put termal, Δq,, Δq,, an Δq,, are expree by State- : an q q p q p q, q mn q p pn, q q pn q m, (5) q, (6) mn, q q q. (7). HEOECAL ANALYSS n thi ection, the property of the proe voltage multiplier i analyze theoretically. he theoretical analyi i performe by aumg the equivalent circuit of Fig., becaue it i known that the general equivalent circuit of the gle-put gle-put SC DC-DC converter can be expree by a four-termal circuit [6]. n Fig., m an m are the converion ratio of ieal tranformer an c i calle the SC reitance. n the theoretical analyi, thee parameter are erive by ug tantaneou equivalent circuit with complex matrix calculation. Fig. how the tantaneou equivalent circuit of the Fig. Equivalent circuit of the proe voltage multiplier 5

3 7th nternational Conference on Electrical, Electronic an Civil Engeerg (CEECE'05) June 7-8, 05 Pattaya (hailan) (a) (b) (c) () Fig. ntantaneou equivalent circuit; (a) State-, (b) State-, (c) State-, an () State- On the other han, State-, the ifferential value of electric charge the put an put termal, Δq,, Δq,, an Δq,, are expree by State- : q 0, (8) an,, q q, (9), q q. (0) n the ame way, the ifferential value of electric charge State- an State- are expree by p p pn State- : q q q q, q p q mn pn, q q q m, () q, () an mn, q q q. () State- : q 0, () an,, q q, (5), q q. (6) Ug (5)-(6), the average put current an the average put current can be expree a an q q i, (7) i, (8) 6

4 7th nternational Conference on Electrical, Electronic an Civil Engeerg (CEECE'05) June 7-8, 05 Pattaya (hailan) an q i i q i, (9) q q i,. (0) n (7)-(0), Δq, Δq, an Δq are electric charge,, an, repectively. Subtitutg ()-(6) to (7)-(0), we have the relation between the put current an the put current a follow: N N, () q N q Nq. From (), the converion ratio Fig. are obtae a m = N+ an m =-N. Next, orer to erive the SC reitance SC, the conume energy one perio i icue. From Fig., the total conume energy one perio can be expree a i i p p pn pn q q q q pn pn q q, () m m mn mn q q q q mn mn q q p p pn pn q q q q m m mn mn q q q q pn mn q q q q pn mn q q p m q q p m q q m p Ug ()-(6), () can be rewritten a q N q q mn pn q q q N p m on on. () on. () Here, the conume energy of Fig. i obtae a q : SC, (5) herefore, from () an (5), we have the SC reitance a follow: SC N N on. (6) Epecially, when the parameter δ i zero, (6) can be rewritten a SC N N on. (7) By combg () an (6), the equivalent circuit of the proe voltage multiplier can be expree by the followg matrix: N th N 0 SC N. 0 N 0 (8) herefore, when the put loa i the reitive loa L, the wer efficiency an the put voltage are expree a L N N th (9) L SC N L an N N th L. (0) SC. SMULAON o clarify circuit characteritic, SPCE imulation are performe concerng the proe voltage multiplier with ix tage. Firt, the property of the proe voltage multiplier i compare with that of the conventional CM hown Fig.. Fig. 5 how the imulate put voltage. n Fig. 5 (a), the SPCE imulation were performe uner conition that AC = 00@50Hz, = 00, = 9.9, δ= 0.00, C pk= C pk= C mk= C mk=0μf, C = C =pf, an C =0μF. On the other han, Fig. 5 (b), the imulation conition are a follow: AC = 00@50Hz, C j = 0μF, an C =0μF. he imulate voltage multiplier wa eigne by ug the ioe el MU60 an the capacitor el with 0.00Ω ternal reitance. A Fig. 5 how, the proe multiplier can generate an put voltage at high pee. Concretely, the ettlg time of the proe multiplier i le than 50m. On the other han, the ettlg time of the conventional CM i ab 0 econ. Next, to confirm the valiity of the theoretical analyi ecribe Sect., the SPCE imulation are performe. Fig. 6 how the comparion between imulate efficiency an theoretical efficiency. Fig. 7 how the comparion between imulate put an theoretical put. n the SPCE imulation of Fig. 6 an 7, the ioe witch wa ele by an 7

5 7th nternational Conference on Electrical, Electronic an Civil Engeerg (CEECE'05) June 7-8, 05 Pattaya (hailan) (a). CONCLUSON For non-thermal foo proceg utilizg an unerwater hockwave, a parallel-connecte high voltage multiplier ha been proe thi paper. he valiity of circuit eign wa confirme by SPCE imulation an theoretical analyi. he reult of SPCE imulation howe that the proe multiplier can achieve higher pee than the conventional Cockcroft-alton voltage multiplier. Concretely, the ettlg time of the proe multiplier with ix tage i le than 50m when the put capacitance i 0F. On the other han, the ettlg time of the conventional voltage multiplier i ab 0 econ when the put capacitance i 0F. Concerng the put voltage an wer efficiency, hany theoretical equation were erive by ug a four-termal equivalent circuit. hee theoretical reult were goo agreement with SPCE imulate reult. herefore, the formula obtae by the theoretical analyi will be helpful to eign the proe voltage multiplier. (b) Fig. 5 Simulate put voltage; (a) Proe voltage multiplier an (b) Conventional Cockcroft-alton voltage multiplier EFEENCES [] M. Stoica, L. Mihalcea, D. Bpra, an P. Alexe, Non-thermal novel foo proceg technologie. An overview, Journal of Agroalimentary Procee an echnologie, vol. 9, ue, pp. 7, May 0. [] C. H. Zhang,. Namihira,. Kiyan, K. Nakahima, S. Katuki, H. Akiyama, H. to, an Y. maizumi, nvetigation of hockwave prouce by large volume pule icharge uner water, EEE Pule Power Conf., pp , June 005. [] A. Lamantia, P. Maranei, an L. arizzani, he ynamic of the Cockcroft-alton voltage multiplier, Proc. of the EEE Power Electronic Specialit Conf., pp , June 990. [] S. qbal, A hybri ymmetrical voltage multiplier, EEE ran. Power Electronic, vol. 9, no., pp. 6, Jan. 0. [5] S. qbal an. Bear, A bilar Cockcroft-alton voltage multiplier for ga laer, American Journal of Applie Science, vol., no.0, pp , Jan [6] K. Eguchi, K. Fujito, an H. Saaki, A hybri put charge-pump ug micrower therelectric generator, EEJ ran. Electrical an Electronic Engeerg, vol.7, no., 5-, July 0. Fig. 6 Comparion between imulate efficiency an theoretical efficiency Fig. 7 Comparion between imulate put an theoretical put ieal witch, an on-reitance on =Ω, an a threhol voltage ource th =. A thee figure how, the theoretical reult are goo agreement with the SPCE imulate reult. Conequently, the valiity of the theoretical analyi wa confirme. 8