A Multi-Channel Analog-To-Digital Conversion Technique Using Parallel Duty-Cycle Modulation

Transcription

1 Iteratioal Joural o Electroics ad Computer Sciece Egieerig 86 Available Olie at ISSN: A Multi-Chael Aalog-To-Digital Coversio Techique Usig Parallel Dut-Ccle Modulatio Jea Mbihi Léadre Neme Neme Advaced Teachers' Traiig College or Techical Educatio, Uiversit o Douala, BP 87, Douala, Camerou mbihidr@ahoo.r* Advaced Teachers' Traiig College or Techical Educatio, Uiversit o Douala, BP 87, Douala, Camerou Abstract- A ew tpe o multi-chael aalog-to-digital coversio techique is preseted i this research work. It is ouded o the use o parallel dut-ccle modulatio cells, each o which beig used as a idepedet iteracig circuit with -bit modulated output bit per chael. I additio, the set o modulated bits associated to the whole aalog iputs, are simultaeous samplig ad processig. The priciple ad importat properties o the proposed multi-chael A/D coversio are studied i depth i the paper. The, a origial 4-chael virtual illope is preseted, i order to show a potetial applicatio o the proposed multi-chael aalog-to-digital coversio techolog i istrumetatio egieerig. Fiall, a sample o sigals acquired usig that prototpig virtual illope are preseted. Kewords A/D coversio, multi-chael, dut-ccle modulatio, simultaeous samplig, IIR ilters, virtual illope.. Itroductio The eeds o buildig multi-chael A/D (aalog-to-digital) coversio coiguratios, has received icreasigl the attetio o ma researchers ad proessioals i istrumetatio egieerig. The variet o multi-chael A/D coversio schemes ecoutered i the literature ([]-[4]), could be classiied ito three mai architectural tpes as illustrated i Fig, each o which is implemeted usig either a itegrated modular desig or a sstem o-chip techolog. I the case o multipleed iputs architecture (Fig. (a)), a sigle -bit ADC (aalog-to-digital coverter) is shared b p aalog iput sigals via a multipleig circuit. Such a coiguratio ields low hardware cost at the epese o a comple cotrol logic. The simultaeous iputs-outputs structure (Fig. (b)) requires a idepedetl cotrolled - bit ADC (aalog-to-digital coverter) per chael. I the simultaeous iputs with multipleed output structure bus (Fig. (c), the eteral output, results rom a bus multipleig process. As a result, a overall iput bus with legth (p ) bits is traslated ito a -bit output bus related to the selected ADC (with = 0,,, p-). Most multi-chael A/D coversio schemes described above, requires at least both a -bit output bus ad a ew cotrol sigals due to multipleig, startig ad ed o coversio. The maor beeit oers b the aoremetioed multichael ADCs structures, relies o the act that the -bit output bus provided is a read-to-use biar code, i which case the role o a host computer used or data acquisitio, is reduced to decodig the -bit word available at the output o the target A/D coverter. However, the weakesses o the commol used multi-chael A/D coversio architectures, is the great compleit associated with both the iteracig hardware ad the bus multipleig logic retaied. Thus, as illustrated b the block diagram preseted i Fig., the origialit o the p-chael A/D coversio scheme proposed i this paper, is ouded o parallel DCM (dut-ccle modulatio), with simultaeous samplig ad parallel digital sigal processig. It cosists o a set o p parallel DCM cells (Fig. (a)), each o which behaves as a timevarig periodic switchig sigal source (see Fig (b)). The, the resultig p-bit modulated word could be simultaeousl sampled ad iltered usig a digital processig program. The parallel DCM architecture results rom the etesio o a basic DCM circuit studied i a previous research work ocused o aalog istrumetatio [5]. As a implicatio, the st cotributio o this paper relies o the etesio o the DCM-based A/D coversio cocept, to multi-chael data acquisitio sstems. Secodl, a well tested virtual illope preseted as a prototpig sstem, appears to be a ovelt or didactic use, i istrumetatio egieerig educatio. ISSN /VN

2 87 Figure : Stadard multi-chael A/D coversio schemes The remaider o the paper is orgaized as ollows. I Sectio, a p-chael DCM is modeled. The, the simultaeous samplig process o the set o p switchig modulated waves is reported i Sectio. I Sectio 3, the parallel digital ilterig uit required i the computer side or simultaeous decodig the whole modulatig iputs is outlied. I Sectio 4, a well tested virtual illope built as a prototpig applicatio is preseted, whereas the eperimetal results ad idigs obtaied whe testig the related virtual illope are preseted i order to show both the realistic easibilit ad the potetial use o the proposed p-chael A/D coversio i istrumetatio egieerig.. Modelig a p-chael A/D coversio via DCM The proposed p-chael A/D coversio scheme via simultaeous DCM ad samplig is preseted i Fig. Viewed rom the -bit data microbus, the time varig dut-ccle o the th modulated sigal ( {0,,, p-}), is deied as ollows : ISSN /VN

3 IJECSE,Volume,Number 3 Jea Mbihi ad Léadre Neme Neme To ( ( t )) R ( ( t )) =, () T ( ( t)) where T ( (t)) = T o ( (t))+t o ( (t)) is the modulatio period at time t, T o ( (t)) ad T o ( (t)) beig the duratios or which (a) Set o p simultaeous -state coders; (b) Ed-usig computer with p-bit microbus. Figure : Bock diagram o the proposed p-chael A/D coversio architecture. M (t) i Fig ((b)) switches ad remais +E Volts ad -E Volts respectivel. As a implicatio, the Fourier series related to M (t) obtaied ater a straightorward developmet, is give b : ( π R( ( t)) ) 4 E t M t ( R t ) E si T t ( ) = ( ( )) + cos π π Low requec term = ( ( )) 3 High requec terms The modulated wave () cosists o a low requec term depedig o the dut-ccle R( (t)), ad high requec terms due to switchig ad modulatio eects. A realistic assumptio cosidered here or the sake o aalsis easiess is that the dut-ccle uctio R( (t)) could be approimated b : ~ R( ( t)) = β ( t) + (3) where the slope β is a desig parameter. As a implicatio, a modulatig sigal (t) could be recovered rom Eq. give Eq. 3 usig a low-pass ilter with a static gai K give b, K = (4) β E () ISSN /VN

4 89 3. Simultaeous Samplig Process The TTL states o the switchig modulated sigals (t) (or = 0,,, p-) are available or simultaeousl samplig at the iput o a p-bit data microbus. The, the sequeces o p-bit iput words related to the whole set o p- chael modulated iput waves, are red over time b the digital processors uder a p-bit addressig mode, ad ed ito the p-bit sstem register. As a result, give a appropriate samplig period T, the the sampled versio o () at discrete times t k = k T (k = 0,,,, N), is give b : ( π R( ( ) ) 4 E k T M k ( R k ) E T k si ( ) = ( ( )) + cos π (5) π Low requec term = ( ( )) 3 High requec As i the case o sigle iput DCM or sigma-delta A/D coverters ([6], [7]), a importat problem to take ito accout whe samplig a discrete sequece give b Eq. 5, is the over samplig pheomeo. It is due to the act that the aalog origial versio o Eq. 5 give b Eq. is a time varig square wave, with a wider badwidth compared to that o the modulatig wave (t) ecapsulated i R( (t)). Thus, the samplig theorem used i digital sigal processig [8], is applicable i this case to the target modulated wave M (t) to be sampled. Let ( ( t)) beig the udametal requec o the illator associated with the th chael, its imum value be a idetical costat or all chaels, i which case the badwidth eough compared to B terms which occurs or (t) = 0, is assumed to B related to the periodic square wave is large. Thus, assumig that the admissible badwidth o the th aalog sigal (t) is a costat, the the ollowig costrait should be satisied whe choosig the simultaeous samplig requec s, B << << B s << or all = 0,,, p- (6) I this case, the over samplig actor icurred is s B. 4. Parallel digital ilterig Idetical M th order low-pass IIR (iiite impulse respose) ilters could be implemeted, i order to simultaeousl recovered the set o p modulatig discrete sigals ( or {,,, p}, usig the ollowig parallel recursive Equatios : 0( X( ( X ( = ( X ( p ( X p( X ( k M + ) X ( k M + ) X ( k M + ) ( k M + ) ( k ) ( k ) ( k ) ( k ) ( k N) b 0 ( k N) b M ( k N) a p( k N a X p p ) where M, N, b i ad a m (or i {0,,, M-}, m {,,, N 0 }) are desig parameters. 4. Case stud : A prototpig p-chael virtual illope 4. Hardware descriptio The schematic diagram o the proposed p-chael virtual illope is preseted i Fig 3. Without lost o geeralit, it cosists o p = 4 idetical DCM circuits (Fig 3(a)), ad a NEC Powermate PC (Petium 4, MHz cloc with a embedded LPT port as show i Fig 3(b). The sigal geeratio sstem with p = 4 outputs (Fig. 3(c)), cosists o N (7) ISSN /VN

5 IJECSE,Volume,Number 3 Jea Mbihi ad Léadre Neme Neme a itegrated ICL 8038 circuit with three outputs (sie, triagle ad square), ad p-3 = eteral low requec sigal, geerated usig Philips PM507 istrumet. The iput sigals associated with the irst chaels (CH0-sie, CH-square, CH-triagle) are geerated b the ICL 8038 circuit, while the CH3-eterel iput is coected to the output o PM507 istrumet. Followig the results obtaied i a sigle iput sstem, the dut-ccle provided per chael could be give b [5]: T R( ( ) = T o α ( ( + α ) E l ( ( ) α + ( α ) E = ( ( ) l ( α ) ( + ) ( ) ( ) ( ( α ) E α ( ( α ) E R with α = = , α = α, = 0,,, p-. Thus, the parameter β i Eq. 4 related to the irst R + R order Talor series o Eq. 8 is : α α E ( α ) β = + α log α (9) (8) Figure 3: Bloc diagram o the virtual illope. Followig the idig reported i [5] or a sigle chael A/D coversio via DCM techique, umerical simulatio ad compariso idicate that, depedig o the choice o α, Eq. 3 give Eq. 9, is a ecellet liear approimatio o Eq. 8 over a suicietl wide modulatig rage. Sice the set o p parallel DCM cells cosidered here idepedetl operates, that importat idig remais valid. ISSN /VN

6 83 4. Quatitative stud ad programmig data For didactic purpose, the samplig requec s is chose accordig to Eq. 6 or a modulatig requec badwidth = 30 Hz per chael. The, rom the compoet values o the modulatio circuit give i Fig. 3(b), (R = B 0 kω, C = 33 F, R = 8. kω ad R 3 =0 kω), the real value o Assumig i Eq. 6 that B = 9 R log + R = R C 3 is computed as ollows: =.47 KHz (0) =3.3KHz, a good choice o the samplig requec is s = 50 Khz. The IIR ilter required per chael, results rom the discretizatio o a aalog d order low-pass active ilter, with traser uctio give as ollows : F c Y ( s ) K ω ( s ) = = () X ( s ) s + ξ ω s + ω where K is the ilter gai deied b Eq. 4 give Eq. 9, ω the atural requec, ad ξ beig the dampig coeiciet. Give a samplig period T =0.0 ms, the recursive equatio is computed rom Eq. 7, usig Tusti s discretizatio techique [8] (b replacig i Eq. the comple variable s b (/T) (z-)/(z+)) to obtai the ollowig recursive equatios (or = 0,,, ): (0) = b 0 (0), () = b 0 () + b (0) - a (0), () where (k ) = b 0 ( + b (k - ) + b (k - ) - a (k - ) - a (k - ) b0, b, b, a ad a deped o K, ω ad ξ. It is importat to remark that, Eq. is equivalet to Eq. 7 or a secod order IIR ilter. The moitorig sstem is a visual cotrol pael, allowig the user to coigure ad cotrol the multichael virtual illope, ad to visualize the results obtaied. 4.3 Virtual istrumetatio sotware ad eperimetal results For the sake o simultaeous samplig ad digital ilterig purposes, a custom Visual Basic applicatio sotware has bee developed ad implemeted accordig to the theor developed rom sectio to 4. Additioal virtual istrumetatio capabilities provided b the visual istrumet are: biligual dialog displa (Eglish/Frech), parameters coiguratio, leible data grid, graphs displa with shitig values i plottig time or the sake o visual clarit, horizotal ad vertical zoom, database savig i Matlab ormat, ad more. A sample o sigals viewed o the visual cotrol pael scree whe testig the 4-chael virtual illope, is preseted i Fig. 4. ISSN /VN

7 IJECSE,Volume,Number 3 Jea Mbihi ad Léadre Neme Neme Figure 4 : Sample o digital sigal acquisitio o the cotrol pael o theprototpig 4-chael virtual illope with simultaeous DCM. The idetical parameters used i each chael to coduct the eperimets are summarized as ollows : T = 0,0 ms (samplig period) : N/N (proportio o the sample size to be displaed i the data grid), E = 9 Volts (suppl voltage o modulatio circuits), α = ad α = -α, c = 45 Hz (desired cut-o requec o the IIR ilter per chael), ξ = 0.7 (dampig coeiciet o a IIR ilter per chael). From these values, ω = rad/s (atural requec) ad K =.747 (ilter gai), are computed umericall ad displaed. Fig 4(a) presets the graphs o sampled TTL dut-ccle modulated waves, simultaeousl acquired rom chaels CH0, CH ad CH3 respectivel. I additio, the overall A/D coversio results obtaied rom CH0 (3 Hz - sie), CH ISSN /VN

8 833 (3 Hz - square), CH (3 Hz - triagle) ad CH3 (30 Hz -sie) respectivel over 500 ms acquisitio time, are show i Fig 4(b), where each graph is shited accordig to a related value or the sake o clarit view. It is importat to remark that, eve a aalog square wave with a wider badwidth is quit recovered with good qualit uder simultaeous digital acquisitio. A ew distortios observed i this case, are due to both Gibbs' pheomeo [8]. It is ot surprisig that uder widows, the tests o the prototpig virtual illope model, has bee limited to low requec modulatig iputs. This is due to the greed oversamplig costraits i a multitaskig operatig sstem. Fortuatel, a more reliable ad high perormace DCM-based data acquisitio sstems might be implemeted usig a o-chip digital processig techolog, with a embedded high requec ad precisio oversamplig clock, as it is the case or most itegrated multichael sigma-delta coverters ([9], [0]). 5. Coclusio The A/D coversio scheme studied ad well tested i this paper is ouded o a umber o beeits icludig hardware simplicit (-bit o code per aalog caal), simultaeous sigal samplig, ad digital decodig simplicit based o IIR ilters. However, beside the metioed beeits, iterestig problems remai usolved. It would be useul to id optimal desig modulatio ad demodulatio parameters, which miimizes the boud o the overall A/D coversio error per chael. It would be a challege also to built a o-chip model o a optimal DCM-based p-chael A/D coversio sstem, i order to cover idustrial applicatios area requirig high requec modulatig badwidth. These ruitul perspectives will be ivestigated i uture research works. Reereces [] Bob Judd, "Everthig You Ever Wated to Kow about Data Acquisitio: Part Oe - Aalog Iputs", Jauar 008, Uited Electroic Idustries ( [] Maim, "ADCs or Simultaeous Samplig", Applicatio ote 90, October 0, 000, Maim ( [3] Maim, "Desig guidelies or high-perormace, multi-chael, simultaeous samplig ADCs i Data acquisitio sstems", Applicatio otes, pp -6, Mars 009, Maim. [4] Maim, "Desig Guidelies or High-Perormace, Multichael, Simultaeous-Samplig ADCs i Data-Acquisitio Sstems (DAS)", Applicatio ote, pp -6, Mars 009, Maim. [5] J. Mbihi, F. Ndali Beg & M. Mboueda, "Modellig ad simulatio o a class o dut-ccle modulators or idustrial istrumetatio", Iraia Joural o Electrical ad Computer egieerig, 4 () (005) pp. -8. [6] E. Roza, "Aalog-to-digital coversio via dut-ccle modulatio", IEEE trasactios o circuits ad sstems II: Aalog ad digital sigal processig, 44 (), (997) pp [7] Sagil Park, "Motorola digital sigal processors Priciples o sigma-delta modulatio or aalog-digital coverters (Februar, 00)", pp [8] J. G. Proakis ad D. G. Maolakis, Digital sigal processig-third Editio", 968 p., Pretice Hall, 996. [9] Maim, Multichael oversamplig sigma-delta ADC, [0] Aalog Device, AD833A: Multi-Chael, 4-Bit, 9 khz Sigma-Delta DAC,. ISSN /VN