Digital-DC Control Loop Compensation

Transcription

1 Digital-DC Cotrol Loop Compesatio Applicatio Note May 0, 009 AN06.0 verview All power supplies require some type o eedback loop to regulate the output voltage. A simpliied diagram o a buck cotroller is show i Figure with a pulse width modulator (PWM ad a error ampliier / compesator. For this eedback loop to be stable, egative eedback is used. This meas that the output voltage (V UT is compared to the reerece voltage (V R ad the dierece (V R V UT is ampliied by the error ampliier. The output o the error ampliier is called the error voltage. The error voltage polarity is iverted with respect to V UT ad is thereore -80 out o phase with V UT. The goal o the eedback loop is to miimize the error betwee V UT ad V R. The error is small whe the overall eedback loop gai is high. Ideally, a eedback loop would have iiite gai or all requecies, thus providig perect regulatio regardless o the demads o the load. PWM GPWM VIN/VSAW D -D Type 3 Ampliier VIN L C Rc Ro VR VUT Practical limitatios such as the sampled ature o the switchig power supply, iite gai ad badwidth o real compoets, ad time delays i the cotrol loop limit the possible gai ad badwidth o the eedback loop. I practical terms, the goal o power supply loop compesatio is to have as high a gai as possible at DC ad reduce this gai to less tha (0dB beore the phase shit i the cotrol loop reaches 360. Recall that the error ampliier itroduces -80 o phase shit. The output stage used i the buck coverter is a LC ilter. There are several characteristics o this ilter that impact its requecy respose. Primarily, the LC ilter has -80 o phase shit ad has a atteuatio o 40dB per decade above its atural requecy (ƒ. The atural requecy o the LC ilter is approximated by: Eq. [] π LC Also, the compoets i the LC ilter are ot ideal because they cotai parasitic impedaces. I may capacitors used i output ilters, the Equivalet Series Resistace (ESR, show as R C i Figure is large eough to alter the respose o the LC ilter at requecies that impact the cotrol loop desig. This is called the ESR zero (ƒ zesr. It has the eect o chagig the LC ilter s atteuatio slope rom -40dB (- slope per decade to -0dB (- slope per decade ad addig 90 o phase back ito the eedback loop. The ESR zero o the output capacitor is calculated usig Eq. []: zesr πcr Eq. [] C Figure. Simpliied Buck Cotroller -888-INTERSIL or Itersil (ad desig is a registered trademark o Itersil Americas Ic. Copyright Itersil Americas Ic All Rights Reserved All other trademarks metioed are the property o their respective owers

2 Applicatio Note 06 Closig the Cotrol Loop Frequecy compesatio is used to achieve the goal o less tha 360 o phase shit whe the ope-loop gai is above 0dB. I the circuit o Figure, compesatio is provided by the type 3 ampliier. The easiest method o compesatig cotrol loops usig Digital-DC Techology is by usig compesatio pi-strap settigs listed i the datasheet or each device. Zilker Labs, Ic. also oers user-riedly tools or calculatig compesatio coeiciets usig regulator desig costraits ad ilter compoet parameters. LC ilters exhibit resoat behavior. Near the atural requecy (ƒ, the LC ilter traser uctio will eectively ampliy the iput sigal. The extet to which this occurs is determied by the quality actor (Q. I eect, the Q o the circuit is a measure o the gai the LC ilter exhibits at ƒ ad how abrupt the phase shit rom 0 to -80 will be. I power supply applicatios, it is also idirectly a measure o the circuit s eiciecy: the lower the resistaces i the circuit, the higher the Q. However, a high Q also correspods to a abrupt phase shit rom 0 to -80. For a simpliied power stage ad output ilter cosistig o high-side MSFET o-resistace R N-H, low-side MSFET o-resistace R N-L, output iductor L havig resistace R L, a output capacitace array o parallel capacitors havig capacitace C ad equivalet series resistace R C ad or a load resistace R, the atural requecy ad quality actor o the circuit are give by Equatios [3] ad [4], respectively. RC L π C R Re R or Eq. [3] RC R π LC R R e Q or RC L C R Re R L RC ReR C Re R Re R LC Q L C ( RC R ( Re R ( R ( R R R R C e e Eq. [4] where R e is the eective resistace o the MSFETs averaged over a switchig period combied with the iductor resistace. For a give duty cycle, D, R e is give by e NH ( D RNL RL R D R Eq. [5] For Q >, which is the case or may low-cost power supplies, the phase ca be assumed to shit rom 0 to - 80 at ƒ. The PWM has a ixed gai o V IN G PWM Eq. [6] VSAW where V SAW is the peak amplitude o the PWM sawtooth waveorm used i the PWM cotroller. G PWM is a costat ad has o phase impact o the eedback loop. The power stage gai, g PS, (i.e., cotrol-to-output traser uctio cosists o a DC gai, G PS, ad a requecy-depedet compoet which is a uctio o zesr, ad Q. g PS s π zesr GPS Eq. [7] s s π Q (π This traser uctio is plotted i Figure. We deie a term, G FIX, which combies all the DC gais i the loop except that o the compesator. G G G Eq. [8] FIX PWM PS I g CMP represets the gai o the compesator, the ope-loop traser uctio o the simpliied buck coverter is the Applicatio Note Revisio 5/0/009

3 Applicatio Note 06 s π zesr g gcmpgfix Eq. [9] s s π Q (π phase (Figure 3. Comparig Figure ad Figure 3 reveals what the requecy respose o the compesatio circuit should be. The compesatio circuit requecy respose is show i Figure 4. The desired eedback ope-loop respose is show i Figure 3. Figure. Buck Coverter Power Stage Frequecy Respose Figure 3. Desired pe Loop Respose The goal o the compesatio circuit is to modiy the gai ad add phase to the requecy respose o the modulator ad LC ilter sectios o the power supply (Figure to achieve the desired eedback gai ad Figure 4. Compesatio Circuit Frequecy Respose I a voltage mode aalog power supply, this compesatio is doe with resistors ad capacitors coigured to provide poles, zeroes, ad gai i the error ampliier. To provide the highest possible gai at low requecies, the compesator is geerally chose to be a itegrator. This meas that the compesator has a pole at the origi (DC, a - gai slope ad a phase shit o -90. Because the phase shit due to the error ampliier is -80, the phase shit due to the LC ilter is -80 ad the phase shit o the itegrator is -90, the compesator must provide a positive phase boost. I additio, because the LC ilter has a - gai slope ad the itegrator has a - slope, the compesator must have a gai slope to yield the desired et gai slope o -. The compesator accomplishes this with two zeroes placed ear the LC ilter atural requecy, ƒ. These zeroes provide the 80 phase shit ad slope eeded to couteract the itegrator ad LC ilter characteristics. 3 Applicatio Note Revisio 5/0/009

4 Applicatio Note 06 Although the loop gai is usually below 0dB beore the ESR zero, the compesator ote provides a pole (-90, - slope to eutralize the eects o the ESR zero (90, slope. Fially, due to limitatios o realworld ampliiers, the compesator provides a additioal pole to keep the error ampliier rom operatig beyod its gai-badwidth product limit ad to keep the switchig requecy ripple rom itererig with the operatio o the PWM circuitry. To complete the compesatio circuit desig, the amout o gai required by the compesatio circuit must be determied. First, select a cross-over requecy (ƒ xo, which is a ractio o the switchig requecy (ƒ sw. Geerally, a ratio o /0 o the switchig requecy is a coservative startig poit (~ƒ sw /π is the theoretical max []. The gai eeded rom the compesator is determied by assumig the cotrol loop is compesated so the gai plot crosses 0dB at a - slope as show i Figure 3. The DC gai eeded or this aalog compesator (G ACMP-DC is calculated by assumig a - slope or the compesated cotrol loop or a give crossover requecy. This ca be expressed as G Eq. [0] 0G xo ACMP _ DC swgfix As oted above, the compesator has two zeroes at the LC resoat requecy (ƒ. A pole is added at the ESR zero (ƒ zesr to keep the gai o the ope-loop traser uctio at a slope o -, ad a additioal pole is added at ƒ sw / to reject oise. The ampliier circuit show i Figure 5 is used to achieve the compesatio. [] FIX The compoet values are calculated usig the ollowig equatios: R / C /(π R C C /(π R R G ACMP DC /(π zesrr 3 /(π ( sw / C3 3 R The combiatio o the buck coverter ad compesatio ampliier traser uctios yields the desired ope-loop respose show i Figure 3. ce the compesatio values have bee determied, the stability o the power supply ca be evaluated. Usig the equatio or the buck coverter traser uctio ad the gai, pole ad zero locatios rom the compesatio circuit, the resultig cross-over requecy, phase ad gai margi ca be evaluated. Although, ideally, the phase margi usig this techique would be 90 ad the gai margi would be 0dB or more, i reality 60 ad 6dB are cosidered to be good desig goals that strike a balace betwee perormace ad stability. Decreasig phase margi to less tha 60 or gai margi to less tha 6dB will icrease the output voltage overshoot with trasiet output loads. Digital PWM The block diagram or a power supply cotrolled by a digital PWM is show i Figure 6. The digitally cotrolled power supply diers rom the aalog versio oly by the values show i the PWM block ad the compesatio block. The gai o the digital PWM block is see i the uctioal block diagram o Figure 7. The PWM block is derived rom several uctios withi the device. These uctios, although implemeted i high speed mixed sigal circuitry, ca be modeled with costat values because o the relatively high requecy at which these blocks operate compared to the requecies o iterest to the cotrol loop (i.e., >0X the switchig requecy. Figure 5. Aalog Compesatio Ampliier 4 Applicatio Note Revisio 5/0/009

5 Applicatio Note 06 DPWM GPWM D -D VIN L C Ro VUT gai o 64 at low requecies, but a large atteuatio at the switchig requecy without addig excessive phase loss. This phase loss ca be expressed as a uctio o the switchig requecy ad is discussed later as part o the compesatio. Rc CMPENSATIN ACCUMULATR Figure 6. DPWM-Cotrolled Power Supply Figure 7. Digital-DC Fuctioal Block Diagram The output voltage is irst applied to a programmable gai ampliier (PGA that has a gai o betwee 0. ad.0. This ampliier is used to eable higher accuracy i the settig o the output voltage. Its gai is cacelled by the gai corrector, which modiies the compesatio settigs to yield a et gai o. The gai correctio uctio also compesates or chages i the iput voltage by the same process. The gai corrector ormalizes the iput voltage to 5V ad automatically modiies the gai so that the et result is a loop gai that would exist i the iput were at 5V. Followig the PGA, the error sigal is applied to the A/D coverter, which coverts this error voltage ito a digital value. Its gai is /V step (/5 mv or 00. Followig the A/D coverter is the ati-aliasig ilter, which is a multi-stage ilter that provides sigal gai ad high requecy oise rejectio. It elimiates the eed or the secod pole used i the aalog compesator. As ca be see i Figure 8, it has a ixed Figure 8. Ati-Aliasig Filter Respose Ater passig through the compesator ad accumulator, the sigal is applied to the digital pulse width modulator (DPWM. The DPWM coverts the output o the itegrator ito the duty cycle that is applied to the power supply MSFETs. I summary, the DPWM block i Figure 6 is a combiatio o the PGA, the gai o the A/D, the ati-aliasig ilter, ad the DPWM. This is also a ixed gai ad ca be expressed as Eq. [] GFIX G 8 PS The traser uctio o the digital voltage mode coverter ca ow be expressed as a equatio i the same orm as the aalog cotroller: s π zesr g gcmpgfix Eq. [] s s π Q (π 5 Applicatio Note Revisio 5/0/009

6 Applicatio Note 06 As metioed earlier, the aalog compesator o Figure 5 provides two zeroes to cacel the two poles o Equatio [] (at, but it also provides three poles. e o these poles cacels the ESR zero o Equatio [] (at zesr, a high requecy pole (at sw / improves oise immuity ad the third pole is at the origi a itegrator which provides the desired respose o a slope o -. Fially, the aalog compesator provides a DC gai term (G ACMP-DC which ultimately determies the crossover requecy ad impacts phase margi ad gai margi as well. To obtai the ideal respose o Figure 3 ad provide oise rejectio above sw /, the aalog compesator s traser uctio must be Like the aalog compesator, the digital compesator has two zeroes at the LC resoat requecy (ƒ. Istead o a op-amp circuit, the digital compesator uses a recursive ilter, which is simply a adder with our iputs: the output o the A/D coverter (the error voltage multiplied by a costat, the error voltage rom the previous switchig cycle (show as z - multiplied by aother costat, 3 the itegrator ad 4 the error voltage rom the switchig cycle two cycles previous (show as a additioal z - multiplied by a third costat. This ilter is show schematically i Figure 9. g ACMP G ACMP _ DC s s πq (π s s s πzesr πsw Eq. [3] Trasormig Equatio [] to the digital domai yields a equatio o the orm ( dz ( bz cz gz gzcmpgzfix Eq. [4] where g ZCMP is the z-domai compesator, G ZFIX is a trascedetal uctio o G FIX,, zesr ad sw represetig the DC gai i the z-domai, d is a trascedetal uctio o zesr ad sw, ad b ad c are trascedetal uctios o ad sw. It should be oted that, or Q > 0.5, b becomes complex but may be coverted to a real umber usig Euler s idetity. The digital cotrol loop is compesated i much the same way as the aalog cotrol loop. However, because the digital cotrol loop has a ati-aliasig ilter that provides oise rejectio above ƒ sw /0, the poles at zesr ad sw / i Eq. [3] are ot required i the digital compesatio ilter. For this reaso, the crossover requecy should occur at least oe octave beore the ESR zero (ƒ xo zesr /. The pole at the origi is implemeted usig a accumulator. Agai, a crossover requecy o ƒ xo ƒ sw /0 is selected ad the DC gai o the digital compesator is calculated, usig a equatio similar to Equatio [0] or the aalog compesator: G xo ZCMP _ DC Eq. [5] swgzfix 0 GZFIX Figure 9. Digital Compesator / Recursive Filter By substitutig z - e -st or each delay (where T is the samplig period, the digital compesator / recursive ilter ca be represeted as ollows: g or g ZCMP CMP A Bz A Be ( z st Cz Ce st ( e st Eq. [6] The term /( e -st is due to the accumulator ad models both the gai ad phase respose o the itegrator. Although i trascedetal orm, the digital compesator / recursive ilter ca be coigured to have the same respose as the aalog compesator by selectig appropriate costats or A, B ad C i Eq. [6]. 6 Applicatio Note Revisio 5/0/009

7 Applicatio Note 06 To do so, set like terms equal i the umerator o Eq. [6] ad the deomiator o Eq. [4], beig sure to divide by the compesator DC gai, G ZCMP-DC. This yields Equatios [7] or real zeroes (at z ad z ad Equatios [8] or complex zeroes (at or Q > 0.5. To simpliy these equatios, ew terms r ad r are deied or Eq. [7] ad r ad θ are deied or Eq. [8]. Compesatio Coeiciets or Real Zeroes: Let A B r e G ( r ( r A ( r r C A r r π z sw ZCMP DC r e π sw z Eq. [7] Compesatio Coeiciets or Complex Zeroes: Let r e GZCMP DC A r cosθ r B A r cosθ C A r π Q sw π θ sw 4 Q Eq. [8] As with the aalog compesator, select the zero requecies ad the gai desired or the compesator stage. Solve the equatios to yield the appropriate A, B, ad C coeiciets. These coeiciets are loaded ito the digital compesator usig a PMBus commad. Additioal details o the use o the PMBus or loadig compesatio coeiciets are i Applicatio Note AN03. [3] The power supply respose ca be simulated ad tested i the same maer as a aalog cotroller. The digital compesator also provides a meas o correctig or the Q o the LC ilter. Usig the calculated coeiciets, both the gai ad phase o the LC ilter are cacelled by the digital compesator, as show i Figure 0. Figure 0. pe-loop Respose As metioed previously, Zilker Labs, Ic. oers userriedly tools or calculatig compesatio coeiciets usig regulator desig costraits ad ilter compoet parameters. Cotact your regioal sales oice or details. Perormace Veriicatio ce the coeiciets have bee loaded ito the device, the circuit ca be tested or stability ad trasiet respose perormace. Trasiet respose is the easiest to test. It is doe by applyig a rapidly chagig output curret, or step load, to the output ad measurig the respose usig a oscilloscope. I a programmable electroic load is available, Set the step load slew rate to that o the expected ed-use applicatio. Set the load step to cause a -3% deviatio i the output voltage. Set the step duty cycle to ~50% Select a repetitio requecy that allows the power supply to settle ater each trasitio; ƒ xo /00 should be a good startig poit. The power supply output should be 95% settled withi three time-costats o the crossover requecy, or 3 τ Eq. [9] π 95 % 3 xo t xo 7 Applicatio Note Revisio 5/0/009

8 Applicatio Note 06 The respose to the step load may have some overshoot. However, more tha three oscillatios idicate margial stability; a expoetial decay is preerred. The cotrol-loop respose should also be veriied by ijectig a requecy swept sigal ito the loop ad measurig the requecy respose with a etwork aalyzer. This is doe by placig a small resistor (0 00Ω betwee the output ad the VSEN pi ad ijectig the sigal ito the eedback loop by applyig a loatig AC sigal across this resistor, as show i Figure. The voltage rom VSEN to groud is the iput sigal (sometimes called reerece sigal, ad the power supply output voltage (V UT is the output sigal (sometimes called the test sigal. The etwork aalyzer will read out the relative phase ad gai o the traser uctio: output sigal/iput sigal. The goal is to veriy a phase margi o >60 ad a gai margi o >6dB over a rage o operatig coditios. The test sigal should be moitored with a oscilloscope ad adjusted so that the test sigal peak amplitude does ot exceed % o the V UT. Excessive test sigal amplitude will result i erroeous loop gai measuremets. Proper correlatio betwee measuremets ad simulatios depeds o the accuracy o the models used, ad Zilker Labs, Ic. is costatly workig to esure the accuracy o its models. Reereces [] Lloyd H. Dixo, Jr., Cotrol Loop Cookbook, Uitrode Power Supply Desig Semiar Maual SEM-00, 996, p [] Veable, Dea ad Foster, S. R., Practical Techiques or Aalyzig, Measurig ad Stabilizig Feedback Cotrol Loops i Switchig Regulators ad Coverters, PowerCo7 Proceedigs, 980. [3] AN03 Zilker Labs PMBus Commad Set, Zilker Labs, 006. Revisio History Date Rev. # 09/7/006.0 Iitial Release 0//006. Update Eqs 5, 8 ad 4 06/4/007. Corrected Fig. 09/04/007.3 Geeral updates. 09/04/007.3 Mior text revisios. /06/ /0/009 AN06.0 Corrected loop respose descriptios to say ope loop Assiged ile umber AN06 to app ote as this will be the irst release with a Itersil ile umber. Replaced header ad ooter with Itersil header ad ooter. Updated disclaimer iormatio to read Itersil ad it s subsidiaries icludig Zilker Labs, Ic. No chages to applicatio ote cotet. Figure. Loop Gai Measuremet 8 Applicatio Note Revisio 5/0/009

9 Applicatio Note 06 NTES 9 Applicatio Note Revisio 5/0/009

10 Applicatio Note 06 Zilker Labs, Ic. 430 Westbak Drive Buildig A-00 Austi, TX Tel: Fax: , Zilker Labs, Ic. All rights reserved. Zilker Labs, Digital-DC ad the Zilker Labs Logo are trademarks o Zilker Labs, Ic. All other products or brad ames metioed herei are trademarks o their respective holders. Speciicatios are subject to chage without otice. Please see or updated iormatio. This product is ot iteded or use i coectio with ay high-risk activity, icludig without limitatio, air travel, lie critical medical operatios, uclear acilities or equipmet, or the like. The reerece desigs cotaied i this documet are or reerece ad example purposes oly. THE REFER- ENCE DESIGNS ARE PRVIDED "AS IS" AND "WITH ALL FAULTS" AND INTERSIL AND IT S SUBSIDIARIES INCLUDING ZILKER LABS, INC. DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS R IMPLIED. ZILKER LABS SHALL NT BE LIABLE FR ANY DAMAGES, WHETHER DIRECT, INDIRECT, CNSEQUENTIAL (INCLUDING LSS F PRFITS, R THERWISE, RESULTING FRM THE REFERENCE DESIGNS R ANY USE THEREF. Ay use o such reerece desigs is at your ow risk ad you agree to idemiy Itersil ad it s subsidiaries icludig Zilker Labs, Ic. or ay damages resultig rom such use. 0 Applicatio Note Revisio 5/0/009