EE5324. VLSI Design II

Transcription

1 EE5324 VLSI Design II Professor Chris H. Kim University of Minnesota Dept. of ECE Practical Information Class webpage Instructor: Chris Kim Office: EE/CSci 4-161, Ph: (612) Office hrs: M 11am noon, or by appointment TA: Wei Zhang zhang758@umn.edu Ph: (612) Office hrs: W 11am-noon, or by appointment (EE/CSci 4-168) UNITE videos 2 1

2 Action Required Make sure your CAD tools are setup properly Tutorial on class website 3 Course Overview Targeted for students who have already taken EE5323 or an equivalent class Focus this year will be on circuit design, device issues, and implementation of functional units (memories and arithmetic units) Real world challenges and solutions for designing high-performance and low-power circuits 4 2

3 Prerequisites EE 5323 VLSI Design I or equivalent MOS transistor Static, dynamic logic, pass transistor logic Sequential logic Familiarity with VLSI CAD tools Cadence: LVS, DRC, Extract HSPICE, Cosmoscope Basic knowledge on CMOS device operation 5 Class Materials J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective, Prentice Hall, 2nd edition, Lecture notes Check the class webpage on a regular basis Other references Y. Taur, T. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, A. Chandrakasan, W. Bowhill, F. Fox, Design of High- Performance Microprocessor Circuits, IEEE Press,

4 Other References Conferences International Solid-State Circuits Conference (ISSCC, slides posted on IEEExplore) Symposium on VLSI Circuits (VLSI) Custom Integrated Circuits Conference (CICC) Off campus access to IEEExplore: Journal IEEE Journal of Solid-State Circuits (JSSC) IEEE Trans. On VLSI Systems (TVLSI) Intel Technology Journal IBM Journal on R & D 7 Grading Policy Assignments (20%) ~4 homeworks 20 min paper review (2 person team) Midterm exam (25%) In class, open book, open notes, calculators permitted Final exam (30%) Open book, open notes, calculators permitted Term-long project (25%) 2k-bit SRAM design Optimize for area, stability, speed, and power consumption 8 4

5 Cadence CAD Tools Schematic editor, layout editor, DRC, LVS, EXT HSPICE, cosmoscope Technology files FreePDK 32nm You need to be familiar with the tools in order to execute the term project 9 Term Project Two-person project me if you need a partner 2k-bit (128x16b) SRAM design Full custom LVS, DRC clean Design parameters: area, stability, speed, and power consumption (leakage and active) Simulations using predictive 32nm technology model Literature survey, search for SRAM design references Prepare to spend long hours on schematic and layout Interim, final report, final presentation 10 5

6 Class Policies Students caught engaging in an academically dishonest practice will receive a failing grade for the course. University policy on academic dishonesty will be followed strictly. No late homework/project No extra work will be accepted for improving the final grade 13 Course Topics Scaling issues, CMOS (2-3 weeks) Memories: ROM, RAM (2-3 weeks) Arithmetic units: Adder, multiplier (1-2 weeks) High performance design (1-2 weeks) High performance logic family, clocking strategies, interconnects Low power design (2-3 weeks) Low voltage designs, leakage control techniques, circuit/device/technology issues, memory Variation tolerant design (1-2 weeks) PVT compensating techniques Power and clock distribution, interconnect, reliability (1-2 weeks) Bulk and SOI 14 6

7 Moore s Law Intel founder and chairman Gordon Moore predicted in 1965 that the number of transistors on a chip will double every months 16 Transistor Scaling Constant E-field scaling: voltage and dimensions (both horizontal and vertical) are scaled by the same factor k, (~1.4), such that the electrical field remains unchanged. 17 7

8 Scaling in the Vertical Dimension Transistor V t rolls off as the channel length is reduced Shallow junction depth reduces V t roll-off However, series resistance increases 18 Scaling in the Vertical Dimension Vertical dimension scales less than horizontal Aggravates short channel effect (V t roll-off) 19 8

9 Constant Field Scaling Scaling assumptions Device parameters Circuit parameters Device and circuit parameters Device dimensions (t ox, L, W, X j ) Doping concentration (N a, N d ) Voltage (V) Electric field (E) Capacitance (C=εA/t) Current (I) Channel resistance (R ch ) Delay (CV/I) Power (VI) Switching energy (CV 2 ) Circuit density (1/A) Power density (P/A) Factor 1/k k 1/k 1 1/k 1/k 1 1/k 1/k 2 1/k 3 k Constant Voltage Scaling Scaling assumptions Device parameters Circuit parameters Device and circuit parameters Device dimensions (t ox, L, W, X j ) Doping concentration (N a, N d ) Voltage (V) Electric field (E) Capacitance (C=εA/t) Current (I) Channel resistance (R ch ) Delay (CV/I) Power (VI) Switching energy (CV 2 ) Circuit density (1/A) Power density (P/A) Factor 1/k k 1 k 1/k k 1/k 1/k 2 k 1/k k 2 k

10 Constant Voltage Scaling More aggressive scaling than constant field Limitations Reliability problems due to high field Power density increases too fast Both constant field and constant voltage scaling have been followed in practice Field and power density has gone up as a byproduct of high performance, but till now designers are able to handle the problems 22 ITRS Roadmap 1 B 1 V 3 GHz 100 W Leakage International power Technology and process-voltage-temperature Roadmap for Semiconductors variation poses 2002 projection enormous ( threat to Moore s law 23 10

11 Transistor Scaling 65nm in production, 45nm near production, 32nm in research phase New technology generation introduced every 2-3 years 24 Cost per Transistor You can buy 10M transistors for a buck They even throw in the interconnect and package for free 25 11

12 Transistors Shipped Per Year Today, there are about 100 transistors for every ant - Gordon Moore, ISSCC Transistors per Chip 1.7B transistors in Montecito (next generation Itanium) Most of the devices used for on-die cache memory 27 12

13 Moore s Wrong Prediction 28 Chip Frequency 30% higher frequency every new generation 29 13

14 Die Size ~15% larger die every new generation This means more than 2X increase in transistors per chip 30 Supply Voltage Scaling Supply voltage is reduced for active power control 2 P active C Vdd f 31 14

15 4 Decades of Transistor Scaling Single Core Itanium Processor Dual Core Xeon Processor An 8-Core 64-Thread 64b Power- Efficient SPARC SoC, Sun Microsystems, ISSCC 2007 Concurrency to combat power and thermal issues IBM s CELL processor Power Density Power density (W/cm 2 ) Year High-end microprocessors: Packaging, cooling Mobile/handheld applications: Short battery life 33 15

16 Power Trend: High Performance vs. Low Power Applications Power (W) 100 x4 / 3years Year Published at ISSCC [Sakurai] 34 Active and Leakage Power Power (W) Year CL delay Vt V Ileak exp( ) 1 t mkt / q Vdd Transistors are becoming dimmers 35 16

17 Leakage Power Crawling Up in Itanium 2 Transistor leakage is perhaps the biggest problem 36 Leakage Power versus Temp. 56% 49% Power (Watts) µ, 15mm die, 1.4V Leakage Active 0% 0% 1% 1% 2% 3% 5% 7% 9% Power (Watts) % 41% 33% 26% 19% 9% 14% 0.1µ, 15mm die, 0.7V Leakage Active - - Temp (C) Temp (C) Leakage power is problematic in active mode for high performance microprocessors 37 17

18 Thermal Runaway Increased heating Higher leakage Higher power dissipation Increased static current Destructive positive feedback mechanism Leakage increases exponentially with temperature May destroy the test socket thermal sensors required 38 Gate Oxide Thickness Electrical t ox > Physical t ox Due to gate depletion and carrier quantization in the channel 39 18

19 Gate Tunneling Leakage MOSFET no longer have infinite input resistance Impacts both power and functionality of circuits 40 Process Variation in Microprocessors Fast chips burn too much power Slow chips cannot meet the frequency requirement 41 19

20 Process Variation in Transistors Normalized I ON NMOS PMOS 2X 100X 150nm, 110 C Normalized I OFF More than 2X variation in I on, 100X variation I off Within-dies, die-to-die, lot-to-lot 42 Sources of Process Variation Intrinsic parameter variation (static) - Channel length, random dopant fluctuation Environmental variation (dynamic) - Temperature, supply variations 43 20

21 Sub-wavelength Lithography 44 Line Edge/Width Roughness I off and I dsat impacted by LER and LWR 45 21

22 Random Dopant Fluctuation V t variation caused by non-uniform channel dopant distribution 46 Resolution Enhancement Techniques (RET) Optical Proximity Correction (OPC) Phase Shift Masking (PSM) 47 22

23 Supply Voltage Integrity IR noise due to large current consumption Ldi/dt noise due to new power reduction techniques (clock gating, power gating, body biasing) with power down mode 48 Supply Voltage Integrity Degrades circuit performance Supply voltage overshoot causes reliability issues Power wasted by parasitic resistance causes self-heating V dd fluctuation should be less than 10% Courtesy IBM 49 23

24 Productivity Gap Design complexity surpasses manpower Effective CAD tools, memory dominated chips 50 Lithography Tool Cost What will end Moore s law, economics or physics? 51 24

25 Interconnect Scaling Global interconnects get longer due to larger die size Wire scaling increases R, L and C Example: local vs. global interconnect delay SIA technology roadmap Interconnect Delay Problem Local interconnect has sped up (shorter wires) Global interconnect has slowed down (RC doesn t scale) 53 25

26 Interconnect Metal Layers M6 M5 M4 M3 M2 M1 Local wires have high density to accommodate the increasing number of devices Global wires have low RC (tall, wide, thick, scarce wires) 54 Cross Talk Noise As wires are brought closer with scaling, capacitive coupling becomes significant Adjacent wires on same layer have stronger coupling 55 26

27 Cross Talk Noise Multiple aggressors multiple victims possible Cross talk noise can cause logic faults in dynamic circuits 56 Cross Talk and Delay Capacitive cross talk can affect delay If aggressor(s) switch in opposite direction, effective coupling capacitance is doubled On the other hand, if aggressor(s) switch in the same direction, Cc is eliminated Significant difference in RC delay depending on adjacent switching activity 57 27

28 Soft Error In Storage Nodes Logic 1 Logic 0 V induced Soft errors are caused by Alpha particles from package materials Cosmic rays from outer space 58 Soft Error In Storage Nodes Error correction code Shielding SOI Radiation-hardened cell 59 28

29 More Roadblocks Memory stability Long term reliability Mixed signal design issues Mask cost Testing multi-ghz processors Skeptics: Do we need a faster computer? Eventually, it all boils down to economics 60 Summary Digital IC Business is Unique Things Get Better Every Few Years Companies Have to Stay on Moore s Law Curve to Survive Benefits of Transistor Scaling Higher Frequencies of Operation Massive Functional Units, Increasing On-Die Memory Cost/MIPS Going Down Downside of Transistor Scaling Power (Dynamic and Static) Process Variation Design/Manufacturing Cost