TABLE 1. Performance comparison of state-of-the-art wideband CMOS receivers.

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1 Dept. o ECE, CEG Campus, Anna University End Semester Examination April-May 2014 B.E(ECE) VIII Semester (FT) EC 9044 RF Microelectronics Answer All Questions Part A (10x2=20 Marks) Ql. Give any one expression or Q and state its units. Q2. An ampliier noise can normally be speciied in terms o its input 'Vn' and 'In'. Explain what these represent and what are their units. Q3. A passive linear ilter with no lossy elements has an insertion loss o 2dB. Comment on its Noise Figure and IIP3 Q4. An ampliier that does not exhibit nonlinearity may not be useul in building an oscillator. Justiy Q5. Image rejection may not be a problem with transmit mixers. Justiy Q6. What should be the relation between IIP3 and OIP3 o an ampliier. Q7. How is impedance matching dierent or optimum power transer or optimum noise perormance. Q8. Derive the expression or K PD or an analog multiplier used as a phase detector. Q9. What are the units used or phase noise. What should be the ideal value or this. QIC. On what actors does the requency resolution o a requency synthesizer depend. Part B(16x5=80 Marks) Qll. The table below compares state o the art wideband receiver realizations or spectrum sensing applications. In your answers, you can reer to either the 'row' number or the Re. number in the Table. (i) Ignoring all other criteria, select the best case and worst case rom Noise perormance point alone. (4) (ii) Consider the realization in the second row (indicated as Re [11]) in the Table. Suppose two closely spaced tones, each o power -70dBm, are superposed and given as input to this receiver. What are the expected output powers o (a) at each tone (linear term) and (b) third order intermodulation terms and (c) second order intermodulation terms. (6) (iii) Compare all the perormances o only the realizations o second and last rows o the Table given below. Which one o these two would you consider as better and why? (6) TABLE 1. Perormance comparison o state-o-the-art wideband CMOS receivers. Frequency Cain NF IIP3 11P2 Power Cons. CMOS Re. (GHz) (db) (db) (dbm) (dbm) (mw) Technology [9] 0.05-O.86 no nm [11] nm [12] < nm [23] nm Our work [24] nm Q12.a. Careully study the igure given in Fig.12a (i) and also read its title careully. This is taken rom an article whose title is " Single RF Front End MIMO Transceiver". (i) Explain the principle o operation o this receiver by discussing briely the unction o each and every block o the receiver shown in the diagram. This should also justiy the title o the article stated above. (8) (ii) Careully study the igure and determine/identiy the numerical value o' c ' o this system. (2) (iii) The circuit diagram in Fig.l2a (ii) gives a more detailed view o the complete LNA used in this system. Explain the principle o operation o this LNA and identiy the LNA architecture used. Please note that the codes used in this case are the irst two Hadamard codes and are orthogonal. (6) Q12.b Consider the circuits in Fig.l2b(i) and Fig.l2b (ii) below. The irst one is a conventional mixer and the second is derived rom it. Explain the principle o operation here and determine the expression or conversion gain.

2 Q13a. The Fig.13 a (i) shown below represents a eedback scheme or cancelling out the blocker signal. Since this a zero IF receiver, the wanted received signal is shown centered at L0 at the input. The closed loop transer unction rom input to output is given by G{S) = <7m,LNA(s) ' Z LC represents the transer unction o the LC tank in the orward path, and H core represents the transer unction o the total ilter 'core' located in the eedback path. Note that there is a baseband DC blocking ilter inside the eedback path. The transer unctions o the DC blocking ilter and that o the ilter core are also shown below. In the eedback core, the two arms shown are ed quadrature LO ater division by 2. Explain the principle o operation o this whole circuit in the orm o short points. Sketch the possible magnitude plot o the overall transer unction G(jw). Q13.b Study the Fig.l3b(i) shown below careully. This is part o a zero IF receiver, and hence the wanted signal at the input will be centered at LO. (i)what is the problem being addressed here, particularly due to the phase noise o LO. (ii) The circuit in Fig.l3b(ii) provides a solution to the blocker problem. Explain its operation briely. Note that the LO requencies in the two paths are dierent. Q14.a. In the GSM receiver chip shown in Fig.l4a, the dual modulus divider is equivalent to using a ractional requency divider. For the numbers indicated, what should be the values this raction (you need to give two possible values). In this igure, the numbers '2' and '4' indicate requency division ratio. Q14.b In the Fig.l4b, assume that the maximum values gain and NF rom the ranges shown or each block. Initially, determine the cascaded NF o the Balun and SDR stages alone. Assume the noise power available rom the SDR stage as a voltage source with 50 ohm source impedance and that the VGA input impedance is ininite. Now determine the cascaded NF upto the input o the ADC stage. Q15.a Draw the block diagram o an integer N PLL synthesizer. Determine the expression or the phase transer unction, assuming the loop ilter has a transer unction given by H(s). Q15.b Draw the circuit diagram o a common gate LNA and derive an expression or its Noise Figure. Note: 1. Oil is taken rom "Eicient Use o Spectrum": IEEE Microwave Magazine Jan/Feb a is taken IEEE Comm. Mag Dec and IEEE JSSC May Q.12. b is taken rom IEEE JSSC May 2009 pp Q13a. is taken rom IEEE JSSC May 2010 pp b. is taken rom IEEE JSSC April 2014 pp a. is taken rom IEEE JSSC Jan 2008 pp Q14a. is taken rom IEEE JSSC May 2014 pp 1104

3 l -10 MHz /Combined spread clock siyna Q branch This chip t (Same as I. branch) Balunt, 50 i j I branch IMIMO DSP Equivalent CM-LNA unction Code c-, Siq r, ^Combined sig. Sig. r z r^p Code c 2 To mixer To Q mixer PFD/CP/ IPF/VCO ipll re. 109,4! ^ MHz! \3> Equivalent DMF unction c 2 * k i \d r Combined sig, A, j 2.i r v rc } +r 2,rc 2^^\(k-VT d Orthogonal codes guarantee ktt Jcvc^-O and <k-vt d ktt Jc 2 C2*=1 *-1)r d Fig.12 a(i). 5 GHz IC or a two antenna single RF Front End System >V«*i. \ Lo LJ It J Li Lo r'' ^"'I gt.ll ^'"l gt, t.g Rs "' Vs, VBJ J_ J L VSJ Cods-modulator 1 Code-modulator 2 Sym, Sym, Sym, Sym*... Va> m^mi^minterval Tt-code period T «' u tm m ipi SUP j Code Sequences Cod9Ci:et(T ci)=1 Cod9Ci:C2(Tti)=1 ttej)=-1 Hatama (Orthogonal); Code Modulated, Summed Output rout[t ci)*ri+r2 r^jtej) = ri! F\g.l2a(\\) Code Modulating LNA Realization

4 20 10K X r^l O-Clilp II 0.1 J 10K 75 1 U J LO -H From IM u UNA RF. I PATH CHPATH Fig.l2b i Fig.l2b(ii) si to LNA LCtartk r 0 Baseband transer unction active cancellation itercore locker pica 3g 2io Filter core transer unction HPO r HP Block diagram o eedback cancellation mcctaniim. LO LO Filter core transer unction ns a result o translating the baseband transer unction to the LO requency. Fig.l3a (i) Fig. 13a (ii) 7X Leakage Linearity LC match H8> GEHii}-* o F^^] r -LO 0 aggressor vr'c/m HXLO phase-noise Antennas Wo SAW/ Or Duplexer 4. PAD ~ \ r PA rx aggressor wetm RF IC Ml /n LO VCO/PU HM Mam path TF TTA/LPH LO@ TIA/LPFj tu T A H,l Aux path TF LO&, TIA Fig. 13b{i) Fig. 13b(i)

5 DCXO 26MHz crystal Power Ampliier ra> Multi Modulus Divider Ea-Modulaior Gaussian Filter Gain B6- Control Control Filler 1800/ 10. MIX Front-End Module Block diagram o GSM single-chip Rp pan. Fig.l4.a RF In OmW PLL Reerence 10 mw Clk Buer Gain:0dB BW: 720 MHz V mw 150 mw SDR CMOS Chip Baseband VGA 1.8 V 50 mw DDS MHz PN: -135 dbc/hz > 1 khz oset Eiciency: > 85% 1.2 VO LDO \ DC-DC 1.8 Vn LDO 1 DC-DC j 2.5 VQ LDO 1 DC-DC O LDO 1 DC-DC DDS Control Bits VGA & LPF Control Bits 195 mw 148 mw 5 V Micro- = Controller = RF Balun 3 GHz GHz IL: dB Galn:0-35dB BW: 2-35 MHz NF:<10dB Gain:0-60dB BW: 1-30 MHz BW: 150 MHz BW Step: 1 MHz Noise In: 5 nw/lz Gain: 0 db OIP3:>20dBm CP. MB,, n = 0 db Gain RF Chip Control Bits Fig.l4b 12-bit Dual ADC I,: 100 MHz SNR: 70 db SFDR: 91 db USB 3.0 to PC USB3.0 Interace 32-blt data bus ARM926EJ CPU Up to 2.56 Gb/s