Appendix E7 Logic Family Signal Integrity Comparisons. Roy Leventhal 11/10/99 Used with permission of 3Com
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1 Appendix E7 Logic Family Signal Integrity Comparisons Roy Leventhal 11/10/99 Used with permission of 3Com
2 Contents * Indicates an unfinished section Signal Integrity (SI) Summary and Recommendations... 4 Switching Standards... 5 Capabilities... 7 Test Circuit Examples... 8 Logic Family Results Volt Logic ABT: Advanced BiCMOS Technology ACT: Advanced CMOS Logic ACTQ: Advanced CMOS Logic AHC: Advanced High Speed CMOS Logic AHCT: Advanced High Speed CMOS Logic *ALS *AS CDS Default: Cadence Design Systems CMOS Default HC: High Speed CMOS Logic HCT: High Speed CMOS Logic LS: Low Power Schottky Logic *S: Schottky Logic VHC: Volt Logic AHC/AHCT: Advanced High Speed CMOS Logic ALVC: Advanced Low Voltage CMOS Technology ALVCH: Advanced Low Voltage CMOS Technology ALVT: Advanced Low Voltage CMOS Technology HSTL: High Speed Transceiver Logic LV/LVC: Low Voltage CMOS Logic LVCH: Low Voltage CMOS Logic LCX LVT: Low Voltage BiCMOS Technology LVX: SSTL: Stub Series Terminated Logic Volt Logic ALB: Advanced Low Voltage BiCMOS Technology F/FAST: F Logic NC: VCX /2.1 Volt Logic (Backplane Technology) *BCT BTL/FB: Futurebus+ Backplane Transceiver Logic LVT: Backplane Behavior
3 *CBT *CBTLV GTL/GTLP/GTL+: Gunning Transceiver Logic Differential Nets CDS Default: Cadence Design Systems CMOS Default Differential Switch *ECL: Emitter Coupled Logic LVDS: Low Voltage Differential Switching
4 Signal Integrity (SI) Summary and Recommendations Only some very general recommendations are made regarding the choice of a default IBIS model for different logic levels. The recommendation of a particular technology as "best" for a particular application is not made. This catalog of SI response was originally put together to aid in choosing a default IBIS model for each of the major logic family classifications into voltage ranges. Cadence Design Systems, Inc., SI simulation tools are used here at 3Com and they come set up with a 5 volt default IBIS model, CDSDefault Similarity to that model is used to guide my choices in other voltage ranges. The semiconductor industry's major voltage ranges appear to be 5, 3.3, and (possibly in the future) These voltages refer to the Vcc supply voltage and do not consistently imply a set value for the switching threshold standards of Vol, Vil, Vt, Vih, and Vol once you choose the Vcc. Further, backplane and differential switching are really categories by themselves. Default choices are merely a starting point for running SI simulations when you do not have an IBIS model for the part. They are set up because, for instance, 2.1 volt logic has switching threshold standards that are totally inconsistent with 5 volt logic parts. Thus, totally irrelevant reports on noise margin, indeed the ability to switch at all, will result by letting the simulator automatically fall through to CDSDefault in all cases. 5.0 volt choice: CDSDefault 3.3 volt choice: LVT 2.5 volt choice: ALB 2.1 (and below) volt choices: Not enough data as of this date: 9/22/99. Backplanes: LVT 1 Differential nets: LVT 2 Defaults are only good for seeing if a net is functional at all. As topology becomes more complex and frequency (edge rate) goes up they become less relevant even as a first approximation. This report will be updated as more IBIS models become available. 1 LVT has reasonable capability to run on a bi-directional unterminated daisy-chain bus. GTLP actually performs much better than LVT, but is more expensive. For large, complex busses switch to GTLP. 2 By default, at this point in time. 4
5 Switching Standards Family Vol Vil Vt Vih Voh Vcc ABT ABTE AC ACQ 5 ACT ACTQ 5 AHC AHCT AS 5 ALS 5 FAST 5 HC HCT LS 5 S 5 TTL 5 VHC 5 VHCT 5 AC 3.3 ACQ 3.3 ALVC ALVT HSTL LCX 3.3 LV LVC LVQ 3.3 LVT LVX 3.3 SSTL VCX 3.3 VHC 3.3 5
6 Family Vol Vil Vt Vih Voh Vcc ALB ALVC ALVT F FAST HC LCX LVC VCX 2.5 BTL ECL GTL /GTL+ LVDS 6
7 Capabilities Family Drive I ol /I oh ma t PD ns t r ns t f ns Supply Current Icc ABT 64/ ma AC 24/ ua ACQ 24/ ua ACT 24/ ua ACTQ 24/ ua AHC 8/-8 4/-4 8.5/13.5 ALS 24/ ma ALVC 24/-24 3 ALVT 64/-32 AS 64/ ma FAST 64/ ma GTL/GTLP 34/OD ua HC 6/ ua HCT 6/ ua LCX 24/ ua LS 24/ ma LVC 24/ LVQ 12/ ua LVT 64/ ma LVX 4/ ua S 64/ ma SSTL 20/-20 TTL 40/ ma VCX 24/ / / / ua VHC 8/ ua VHCT 8/ ua 7
8 Test Circuit Examples General Simulation Settings: Most reflection simulations were done at 50 MHz and 1 cycle with the Typical IBIS model selected. The transmission line was set at Zo = 60 ohms and 1 ns delay. Unterminated 8
9 Terminated For terminations a V-I curve with Rin = R L = 65 ohms was used. This provides a small, non-zero reflection at the receiver: ρ = R R L L Zo + Zo So, depending on input capacitance of the receiver and the frequency content of the driver, reflection coefficient ("matched") will be around
10 18 Board Backplane Pitch = 957 mils, Stubs = 1500 mils, f = MHz, Driver = slot 9, Pullups = 30 Ohms, Zo = 63 ohms, V_pullup = 1.5 Volts 10
11 Logic Family Results 5 Volt Logic CMOS:, CDS Default, AC, ACQ ACT, ACTQ, AHC, AHCT, HC, HCT, VHC, VHCT BiCMOS: ABT, ABTE TTL (BP): ALS, AS, F, LS, S, TTL 11
12 ABT: Advanced BiCMOS Technology TI 0.8-µ Un-Terminated TI ABT: Driver = ABT16245a_IO, Receiver = ABT16245a_IO Run1 12
13 Terminated TI ABT: Driver = ABT16245a_IO, Receiver = ABT16245a_IO Run2 13
14 Un-Terminated TI ABT: Driver = ABT245a_IO, Receiver = ABT245a_IO Run3 14
15 Terminated TI ABT: Driver = ABT245a_IO, Receiver = ABT245a_IO Run4 15
16 Un-Terminated TI ABT: Driver = ABT25245_A_port (IO), Receiver = ABT25245_A_port (IO) Run5 16
17 Terminated TI ABT: Driver = ABT25245_A_port (IO), Receiver = ABT25245_A_port (IO) Run6 17
18 Un-Terminated TI ABT: Driver = ABT25245_B_port (IO), Receiver = ABT25245_B_port (IO) Run7 18
19 Terminated TI ABT: Driver = ABT25245_B_port (IO), Receiver = ABT25245_B_port (IO) Run8 19
20 Un-Terminated Fairchild ABT: Driver = ABT16244_data_o, Receiver = ABT16244_data_i Run1 20
21 Terminated Fairchild ABT: Driver = ABT16244_data_o, Receiver = ABT16244_data_i Run2 21
22 Un-Terminated Fairchild ABT: Driver = ABT244_data_o, Receiver = ABT244_data_i Run3 22
23 Terminated Fairchild ABT: Driver = ABT244_data_o, Receiver = ABT244_data_i Run4 23
24 AC: Advanced CMOS Logic TI, Fairchild Un-Terminated Fairchild AC: Driver = AC244 data_o, Receiver = AC244 data_i Run1 Terminated 24
25 Terminated Fairchild AC: Driver = AC244 data_o, Receiver = AC244 data_i Run2 25
26 ACT: Advanced CMOS Logic Fairchild Un-Terminated Fairchild ACTQ: Driver = 74ACT245SC data_io, Receiver = 74ACT245SC data_io Run1 26
27 Terminated Fairchild ACT: Driver = 74ACTQ245SC data_io, Receiver = 74ACT245SC data_io Run2 27
28 ACTQ: Advanced CMOS Logic Fairchild Un-Terminated Fairchild ACTQ: Driver = 74ACTQ245SC data_io, Receiver = 74ACTQ245SC data_io Run1 28
29 Terminated Fairchild ACTQ: Driver = 74ACTQ245SC data_io, Receiver = 74ACTQ245SC data_io Run2 29
30 AHC: Advanced High Speed CMOS Logic TI, Phillips Un-Terminated Phillips AHC: Driver = 74AHC245_IO_5V, Receiver = 74AHC245_IO_5V Run1 30
31 Terminated Phillips AHC: Driver = 74AHC245_IO_3V, Receiver = 74AHC245_IO_3V Run2 31
32 AHCT: Advanced High Speed CMOS Logic TI, Phillips Un-Terminated Phillips: Driver = 74AHCT245 IO_TTL, Receiver = 74AHCT245 IO_TTL Run1 32
33 Terminated Phillips: Driver = 74AHCT245 IO_TTL, Receiver = 74AHCT245 IO_TTL Run1 33
34 *ALS Advanced Low Power Schottky Logic TI 34
35 *AS Advanced Schottky Logic TI 35
36 CDS Default: Cadence Design Systems CMOS Default Un-Terminated CDS Default: Driver = CDSDefaultIO, Receiver = CDSDefaultIO Run1 36
37 Terminated CDS Default: Driver = CDSDefaultIO, Receiver = CDSDefaultIO Run1 37
38 HC: High Speed CMOS Logic Fairchild Un-Terminated Fairchild HC: Driver = 74HC245SC data_io, Receiver = 74HC245SC data_io Run1 38
39 Terminated Fairchild HC: Driver = 74HC245SC data_io, Receiver = 74HC245SC data_io Run2 39
40 HCT: High Speed CMOS Logic Fairchild Un-Terminated Fairchild HCT: Driver = 74HCT245SC data_io, Receiver = 74HCT245SC data_io Run1 40
41 Terminated Fairchild HCT: Driver = 74HCT245SC data_io, Receiver = 74HCT245SC data_io Run2 41
42 LS: Low Power Schottky Logic TI, Fairchild Un-Terminated Fairchild LS: Driver = 74LS245SC data_io, Receiver = 74LS245SC data_io Run1 42
43 Terminated Fairchild LS: Driver = 74LS245SC data_io, Receiver = 74LS245SC data_io Run2 43
44 *S: Schottky Logic TI Un-Terminated 44
45 Terminated 45
46 VHC: Fairchild Un-Terminated Fairchild VHC: Driver = 74VHC245SC data_io, Receiver = 74VHC245SC data_io Run1 46
47 Terminated Fairchild VHC: Driver = 74VHC245SC data_io, Receiver = 74VHC245SC data_io Run2 47
48 48
49 3.3 Volt Logic CMOS: AC, ACQ, ALVC, LCX, LV, LVC, LVQ, LVX, VCX, VHC BiCMOS: ALVT, LVT TTL (BP): GTL, GTL+, HSTL, CTT, SSTL 49
50 AHC/AHCT: Advanced High Speed CMOS Logic TI, Phillips Un-Terminated Phillips AHC: Driver = 74AHC245_IO_3V, Receiver = 74AHC245_IO_3V Run1 50
51 Terminated Phillips AHC: Driver = 74AHC245_IO_3V, Receiver = 74AHC245_IO_3V Run2 51
52 ALVC: Advanced Low Voltage CMOS Technology Phillips Unterminated Phillips ALVC: Driver = 74ALVC16245_IO, Receiver = 74ALVC16245_IO Run1 52
53 Terminated Phillips ALVC: Driver = 74ALVC16245_IO, Receiver = 74ALVC16245_IO Run2 53
54 ALVCH: Advanced Low Voltage CMOS Technology TI, Phillips Un-Terminated TI: Driver = ALVCH16245_IO, Receiver =ALVCH16245_IO Run1 54
55 Terminated TI: Driver = ALVCH16245_IO, Receiver =ALVCH16245_IO Run2 55
56 Un-Terminated Phillips ALVCH: Driver = 74ALVCH162245_OUT, Receiver = 74ALVCH162245_IN Run3 56
57 Terminated Phillips ALVCH: Driver = 74ALVCH162245_OUT, Receiver = 74ALVCH162245_IN Run4 57
58 Un-Terminated Phillips ALVCH: Driver = 74ALVCH16245_IO, Receiver = 74ALVCH16245_IO Run5 58
59 Terminated Phillips ALVCH: Driver = 74ALVCH16245_IO, Receiver = 74ALVCH16245_IO Run6 59
60 ALVT: Advanced Low Voltage CMOS Technology Phillips Un-Terminated Phillips ALVT: Driver = 74ALVT162245_OUT, Receiver = 74ALVT162245_IN Run1 60
61 Terminated Phillips ALVT: Driver = 74ALVT162245_OUT, Receiver = 74ALVT162245_IN Run2 61
62 Unterminated Phillips ALVT: Driver = 74ALVT16245_OUT, Receiver = 74ALVT16245_IN Run3 62
63 Terminated Phillips ALVT: Driver = 74ALVT162245_OUT, Receiver = 74ALVT162245_IN Run2 63
64 HSTL: High Speed Transceiver Logic TI Un-Terminated TI: Driver = HSTL16918_OUT, Receiver = HSTL16918_IN Run1 64
65 Terminated TI: Driver = HSTL16918_OUT, Receiver = HSTL16918_IN Run2 65
66 LV/LVC: Low Voltage CMOS Logic Fairchild, Phillips, TI Un-Terminated Phillips: Driver = 74LVC16245_OUT, Receiver = 74LVC16245_OUT Run1 66
67 Terminated Phillips: Driver = 74LVC16245_OUT, Receiver = 74LVC16245_OUT Run2 67
68 Un-Terminated Phillips: Driver = 74LVC245_OUT, Receiver = 74LVC245_OUT Run3 68
69 Terminated Phillips: Driver = 74LVC245_OUT, Receiver = 74LVC245_OUT Run3 69
70 Un-Terminated TI: Driver = LVC16245A_IO, Receiver = LVC16245A_IO Run1 70
71 Terminated TI: Driver = LVC16245A_IO, Receiver = LVC16245A_IO Run2 71
72 LVCH: Low Voltage CMOS Logic Phillips Un-Terminated Phillips: Driver = 74LVCH16245_OUT, Receiver = 74LVCH16245_IN Run1 72
73 Terminated Phillips: Driver = 74LVCH16245_OUT, Receiver = 74LVCH16245_IN Run2 73
74 LCX Fairchild Un-Terminated Fairchild: Driver = 74LCX245SC data_io, Receiver = 74LCX245SC data_io Run1 74
75 Terminated Fairchild: Driver = 74LCX245SC data_io, Receiver = 74LCX245SC data_io Run1 75
76 LVT: Low Voltage BiCMOS Technology TI, Fairchild, Phillips Un-Terminated Fairchild: Driver = 74LVT245SC data_io, Receiver = 74LVT245SC data_io Run1 76
77 Terminated Fairchild: Driver = 74LVT245SC data_io, Receiver = 74LVT245SC data_io Run2 77
78 Un-Terminated Phillips: Driver = 74LVT245_OUT, Receiver = 74LVT245_IN Run1 78
79 Terminated Phillips: Driver = 74LVT245_OUT, Receiver = 74LVT245_IN Run2 79
80 Un-Terminated TI: Driver = LVT16244A_OUT, Receiver = LVT16244A_IN Run1 80
81 Terminated TI: Driver = LVT16244A_OUT, Receiver = LVT16244A_IN Run2 81
82 LVX: Fairchild Un-Terminated Fairchild: Driver = 74LVX245SC data_io, Receiver = 74LVX245SC data_io Run1 82
83 Terminated Fairchild: Driver = 74LVX245SC data_io, Receiver = 74LVX245SC data_io Run2 83
84 SSTL: Stub Series Terminated Logic TI Un-Terminated TI: Driver = SSTL16837_OUT, Receiver = SSTL16837_IN Run1 84
85 Terminated TI: Driver = SSTL16837_OUT, Receiver = SSTL16837_IN Run1 85
86 2.5 Volt Logic CMOS: ALVC, ALVT, LVC, VCX BiCMOS: ALB, F/FAST 86
87 ALB: Advanced Low Voltage BiCMOS Technology TI Un-Terminated TI: Driver = ALB16244_OUT, Receiver = ALB16244_IN Run1 87
88 Terminated TI: Driver = ALB16244_OUT, Receiver = ALB16244_IN Run2 88
89 F/FAST: F Logic Fairchild, TI Un-Terminated Fairchild: Driver = 74F245SC data_io, Receiver = 74F245SC data_io Run1 89
90 Terminated Fairchild: Driver = 74F245SC data_io, Receiver = 74F245SC data_io Run1 90
91 NC: Fairchild Terminated Fairchild NC: Driver = 74NC7SZ125_out, Receiver = 74NC7SZ125_in Run1 91
92 Terminated Fairchild NC: Driver = 74NC7SZ125_out, Receiver = 74NC7SZ125_in Run2 92
93 Unterminated Fairchild NC: Driver = 74NC7WZ04_data_out, Receiver = 74NC7WZ04_data_in Run3 93
94 Terminated Fairchild NC: Driver = 74NC7WZ04_data_out, Receiver = 74NC7WZ04_data_in Run4 94
95 VCX Fairchild Un-Terminated Fairchild: Driver = 74VCX16245MTD data_io, Receiver = 74VCX16245MTD data_io Run1 95
96 Terminated Fairchild: Driver = 74VCX16245MTD data_io, Receiver = 74VCX16245MTD data_io Run2 96
97 97
98 2.5/2.1 Volt Logic (Backplane Technology) BCT, BTL/ FB+, CBT, CBTLV, GTL/GTLP+ 98
99 *BCT BiCMOS Bus Interface Technology TI Un-Terminated 99
100 Terminated 100
101 BTL/FB: Futurebus+ Backplane Transceiver Logic TI Un-Terminated TTL TI: Driver = FB1650_AOUT, Receiver = FB1650_AIN Run1 101
102 Terminated TTL TI: Driver = FB1650_AOUT, Receiver = FB1650_AIN Run2 102
103 BTL Point-Point TI: Driver = FB1650_BIO, Receiver = FB1650_BIO Run3 103
104 BTL Backplane behavior. Pullup resistor at each end of backplane bus is 33 ohms, V_pullup = 2.1 Volts. TI: Driver = FB1650_BIO, Receiver = FB1650_BIO Run1 104
105 LVT: Backplane Behavior Bias network at each end of backplane bus is resistor divider of 100/75 ohms from 5 volts to ground. Fairchild: Driver = 74LVT245SC data_io, Receiver = 74LVT245SC data_io Run1 105
106 *CBT Crossbar Technology TI Un-Terminated 106
107 Terminated 107
108 *CBTLV Low Voltage Crossbar Technology TI Un-Terminated 108
109 Terminated 109
110 GTL/GTLP/GTL+: Gunning Transceiver Logic TI, Fairchild Un-Terminated TTL Fairchild: Driver = 74GTLP16616_TTL (IO), Receiver = 74GTLP16616_TTL (IO) Run1 110
111 Terminated TTL Fairchild: Driver = 74GTLP16616_TTL (IO), Receiver = 74GTLP16616_TTL (IO) Run2 111
112 GTLP Point-Point Fairchild: Driver = 74GTLP16616_GTL (IO), Receiver = 74GTLP16616_GTL (IO) Run3 112
113 GTLP 18 Board Backplane Fairchild: Driver = 74GTLP16616_GTL (IO), Receiver = 74GTLP16616_GTL (IO) Run1 113
114 TI TTL Un-Terminated TI: Driver = 16612a_TTL_IO, Receiver = 16612a_TTL_IO Run1 114
115 TTL Terminated TI: Driver = 16612a_TTL_IO, Receiver = 16612a_TTL_IO Run2 115
116 GTLP Point-Point TI: Driver = 16612a_GTL_IO, Receiver = 16612a_GTL_IO Run3 116
117 GTLP 18 Board Backplane TI: Driver = 16612a_GTL_IO, Receiver = 16612a_GTL_IO Run1 117
118 Differential Nets CDSDefault (5 Volt), LVDS (2.5/2.1 Volt) 118
119 CDS Default: Cadence Design Systems CMOS Default Differential Switch Un-Terminated CDS Default: Driver = CDSDefaultIO (differential), Receiver = CDSDefaultIO (differential) Run1 119
120 Terminated Single-Ended (78 ohms) CDS Default: Driver = CDSDefaultIO (differential), Receiver = CDSDefaultIO (differential) Run2 120
121 Terminated Differentially (125 ohms) CDS Default: Driver = CDSDefaultIO (differential), Receiver = CDSDefaultIO (differential) Run3 121
122 *ECL: Emitter Coupled Logic Fairchild Unterminated Fairchild ECL: Driver =, Receiver = Run1 122
123 Terminated Fairchild ECL: Driver =, Receiver = Run2 123
124 Terminated Fairchild ECL: Driver =, Receiver = Run3 124
125 LVDS: Low Voltage Differential Switching TI, NSC Un-Terminated Single Ended TI: Driver = SN65LVDS3486_ROUT, Receiver = SN65LVDS3486_RIN Run1 125
126 Terminated Single Ended TI: Driver = SN65LVDS3486_ROUT, Receiver = SN65LVDS3486_RIN Run2 126
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