Chap. 8 Integrated-Circuit Logic Families

Transcription

1 8-1 Introduction Digital IC technology has advanced rapidly(chap 4) Complexity Number of Gates Small-scale integration(ssi) Fewer Medium-scale integration(msi) 12 to 99( ) Large-scale integration(lsi) 100 to 9,999( ) Very large-scale integration(vlsi) 10,000 to 99,999( ) Ultra large-scale integration(ulsi) 100,000 to 999,999( ) Giga-scale integration(gsi) 1,000,000 or more( ) Tera-scale integration(tsi) (10 12 or more) Moore s Law» The number of components that can be packed on a computer chip doubles every 18 months while price stays the same. Most of the reasons that modern digital systems use integrated circuits Integrated circuits pack a lot more circuitry in a small package» the overall size of any digital system is reduced the cost is dramatically reduced because of the economies of mass-producing large volumes of similar devices Integrated circuits have made digital systems more reliable by reducing the number of external interconnections» Discrete components(transistor, diode, resistor, etc.) are protected from poor soldering, breaks or shorts in connecting paths on a circuit board

2 8-2 Integrated circuits have drastically reduced the amount of electrical power needed to perform a given function» Integrated circuitry typically requires less power than their discrete counterparts the saving in power supply costs does not require much cooling There are some things that Integrated Circuits cannot do Integrated circuits can not handle very large currents or voltages (because the heat generated in such small spaces would cause temperatures to rise beyond acceptable limits) Integrated circuits can not easily implement certain electrical devices such as inductors, transformers, and large capacitors For these reason Integrated circuits are principally used to perform low-power circuit operations that are commonly called information processing The operations that require high power levels or devices that can not be integrated are still handled by discrete components Various Logic Families Bipolar transistors : TTL and ECL Unipolar MOSFET transistors : NMOS, PMOS, and CMOS * Transistor 의작용은 carrier 로서 1) Electron 과 Hole, 모두의이동을이용하는 Bipolar 2) Electron 또는 Hole 중하나만의이동을이용하는 Unipolar

3 8-3 In this chapter We will present the important characteristics of each of IC families You will be much better prepared to do analysis, troubleshooting, and some design of digital circuits 8-1 Digital IC Terminology Current and Voltage Parameters : Fig. 8-1 V IH (min) : high- level input voltage V IL (max) : low- level input voltage V OH (min) : high- level output voltage V OL (max) : low- level output voltage I IH : high- level input current I IL : low- level input current I OH : high- level output current I OL : low- level output current» Actual current direction : Fig. 8-5 Fan-Out( = Loading Factor ) min, max 는 Fig. 8-4 참조 maximum number of standard logic inputs that an output can drive reliably» Fan-Out = 10 : one logic gate can drive 10 standard logic inputs

4 8-4 Propagation Delays : Fig. 8-2 (INVERTER) t PLH : delay going from LOW to HIGH t PHL : delay going from HIGH to LOW Power Requirements Every IC requires a certain amount of electrical power to operate. Power supply terminal on a chip : V CC (for TTL), V DD (for MOS) Current drain I CC on the V CC supply : Fig. 8-3» I CCH : Current drain when all of the gate outputs are HIGH» I CCL : Current drain when all of the gate outputs are LOW Average Current» I CC (avg) = ( I CCH + I CCL ) / 2 Average Power» P D (avg) = I CC (avg) X V CC Speed-Power Product Digital IC families have historically been characterized for both speed and power» shorter gate propagation delays (higher speed)» lower values of power dissipation Multiply the gate propagation delay by the gate power dissipation

5 8-5 예제 ) average propagation delay = 10 ns, average power dissipation = 5 mw» Speed-Power Product = 10 ns X 5 mw = 50 X watt-second = 50 Pico-joules (pj) Noise Immunity Stray electric and magnetic fields can induce voltages on the connecting wires between logic circuits» These unwanted, spurious signals are called noise Noise Immunity» Circuit s ability to tolerate noise without causing spurious changes in the output voltage Noise Margin : Fig. 8-4» Quantitative measure of noise immunity High-state noise margin : V NH = V OH (min) - V IH (min) Low-state noise margin : V NL = V IL (max) - V OL (max) Exam. 8-1) Determine the following by using Tab. 8-1 (a) The maximum-amplitude noise spike that can be tolerated when a HIGH output is driving an input : V NH = V OH (min) - V IH (min) = 2.4 V V = 0.4 V (b) The maximum-amplitude noise spike that can be tolerated when a LOW output is driving an input : V NL = V IL (max) - V OL (max) = 0.8 V V = 0.4 V

6 8-6 Fig. 8-4 dc noise margins

7 8-7 Invalid Voltage Levels Invalid Voltage Level : Input voltage between 0.8 and 2.0 V» produce an unpredictable output response In normal operation, a logic input voltage will not fall into the invalid region (because it comes from a standard logic output) Invalid Input Voltage Level 의원인» 1) Output is overloaded (= its fan-out is exceeded)» 2) Power-supply voltages are outside the acceptable range Current Sourcing/ Current Sinking Action Current Sourcing Action : Fig. 8-5(a)» When the output of gate 1 is in the HIGH state the output of gate 1 is acting as a source of current for the gate 2 input Current Sinking Action : Fig. 8-5(b) IC Packages» When the output of gate 1 is in the LOW state the output of gate 1 is acting as a sink of current for the gate 2 input Common IC Packages : Fig. 8-6» DIP : Leads are inserted through holes in the board ( 또는 socket 사용 )» QFP, SOIC (gull-wing) : surface mount technology places an IC onto conductive pads on the surface of the board

8 8-8 Fig. 8-5 current sourcing and sinking High Low

9 8-9» PLCC (J-lead) : socket or surface mount Package Dimensions : Tab. 8-2» Lead pitch : space between pins mil = 1 / 1000 inch 8-2 The TTL Logic Family Basic TTL NAND gate : Fig. 8-7(a) Tr. Q1 has two emitters» Multiple-emitter input transistor can have up to eight emitters for an eight-input NAND gate Totem-Pole arrangement : Tr. Q3 and Q4» Either Q3 or Q4 will be conducting (ON) Diode equivalent of the multiple-emitter Tr. Q1 : Fig. 8-7(b) DTL Diodes D2 and D3 : two E-B junctions of Q1 Diode D4 : C-B junction of Q1 Circuit Operation - LOW output state : Fig. 8-8(a) D1 is needed to keep Q3 off ( = Level Shift Diode ) Saturate Region» Base Voltage (Q3) = 0.8 V = V BE (Q4) + V CE (Q2) = 0.7 V V 그러나 Q3 가 ON 되려면 V CE (Q4) + V D1 + V BE (Q3) = 0.1 V V V = 1.5 V 가필요하지만 0.8 V 밖에안되어 Q3 는항상 OFF I C V CE(sat) ON OFF I B Transistor Characteristic V CE V BE (on) = 0.7 V V CE (sat) = 0.1 V -Ge 0.2 V - Si Active Region Cut-off Region

10 NAND Gate : Low output 8-10 = = 0.8 V Q3 = off 1 x 0.1 V 0.7 V 1 x 0.1 V 0 Leakage current Fig. 8-8(a) Low output

11 NAND Gate : High output 8-11? V R2 1 0 x V BE 0.7 V x V D1 0.7 V 1 Emitter-follower : Q3 -Input = Base -Output = Emitter Fig. 8-8(b) High output

12 8-12 Circuit Operation - HIGH output state : Fig. 8-8(a) V OH will be around 3.4 to 3.8 V (typically 3.6 V)» 5 V (Vcc) - V BE (Q3) - V D1 V R2 = 5 V V V - V R2 3.6 V I IL = V / R = ( V cc -V D3 ) / R 1 = ( 5 V V ) / 4 K = ma R1, R2, R3, and R4 in Fig. 8-8(b) R1 : A 와 B 중에서어느한쪽이 0 일때, R1 이없으면 Vcc 가그대로 Ground 로연결되어전원이 Short 된다 R2 : R2 가없으면 Q2 의 ON/OFF 에관계없이 Q3 의 Base 에는항상 Vcc 가인가되어 Q3 는항상 ON 된다. R3 : R3 가없으면 Q2 와 Q4 가 Darlington 접속이되어 h FE = h FE (Q2) X h FE (Q4) 로매우크게되어발열이심하여동작이불안하다. R4 : Q3 가 ON 일때전류제한용으로사용된다. Current-Sinking Action : Fig. 8-9(a) Q4 : Current-sinking transistor or Pull-down transistor Current-Sourcing Action : Fig. 8-9(b) Q3 : Current-sourcing transistor or Pull-up transistor I IH : small reverse-bias leakage current (typically 10 A)» Fig. 8-8(a) 참고

13 8-13 Totem-Pole Output Circuit Totem-Pole 을사용하는이유» Q3 와 Q4 가교대로동작하여열방출을감소시킬수있다. Q3 가없을때는 Q4 가 ON 되면아주큰전류 (5 V / 130 = 40 ma) 가흘러서많은열발생.» Output HIGH state 에서 Q3 가낮은출력 Impedance(10 ) 를갖는 Emitter Follower 로동작한다. This low output impedance provides a short time constant for charging up any capacitive load on the output 효율적인신호전송을위해서는출력단의출력 impedance 는적을수록, 그리고입력단의입력 impedance 는클수록좋다 ( 전압분배의법칙 ). Totem-Pole 의단점 : Current Transients, Fig 8-18» During the transition from LOW to HIGH, Q4 turns off more slowly than Q3 turns on. So there is a period of a few nanoseconds during both transistors are conducting (ON) 이때 Relatively large current (30 to 40 ma) will be drawn from the power supply. TTL NOR Gate : Fig Fig. 8-8 에서 Q3 와 D1 을제거하고 R4 와 Q4 를연결해도 NAND gate 가능 Multiple-emitter transistor is not used» each input is applied to the emitter of a separate transistor The same totem-pole arrangement as the NAND gate is used Output HIGH : Input A = B = 0» Q1 = Q2 = ON, Q3 = Q4 = OFF, Q5 = ON, Q6 = OFF Output LOW : Input A = B = 1» Q1 = Q2 = OFF, Q3 = Q4 = ON, Q5 = OFF, Q6 = ON

14 8-14 Fig TTL NOR gate off 0 1 on off on on off 0 1 on off off on off on A B X LOW LOW HIGH LOW HIGH LOW HIGH LOW LOW HIGH HIGH LOW

15 TTL Data Sheets TTL Series Characteristics Manufacturers use same numbering system Manufacturers attach unique prefix» Texas Instruments - SN (SN7402)» National Semiconductor - DM (DM7402)» Signetics - S (S7402) 74 and 54 Series basically the same» 54 series can operate over Wider temperature range Power- supply voltage Original Standard Series» 74, 74LS, 74S No longer recommended by the manufacturers for use in new design Still enough demand in the market to keep them in production Advanced and Fast TTL Series» 74AS, 74ALS, 74F Manufacturer s Data Sheets Data Sheet for 5400/7400 NAND gate : Fig. 8-11» Recommended operating conditions, Electrical characteristics, and Switching Characteristics are shown 다음 Paragraph 부터 Data Sheet의내용을하나씩설명함

16 8-16 Supply Voltage and Temperature Range 74 and 54 have nominal supply voltage V CC = 5 V Supply Voltage» Standard 74 operate reliably from 4.75 to 5.25 V» Standard 54 operate reliably from 4.5 to 5.5 V» 74/54 ALS operate reliably from 4.5 to 5.5 V Temperature Range : T A» 74 operates from 0 to 70 C» 54 operates from -55 to +125 C 54 series more expensive : Military or Space application Voltage Levels (74ALS) : Tab. 8-3 LOW state noise margin = 300 mv» V NL = V IL (max) - V OL (max) = 0.8 V V = 0.3 V HIGH state noise margin = 500 mv» V NH = V OH (min) - V IH (min) = 2.5 V V = 0.5 V Maximum Voltage Ratings Voltages applied to any input of a standard 74 ALS series» HIGH : never exceed V not shown in Fig. 8-11» LOW : never be smaller than 0.5 V generally given at the top of a data sheet Input Clamp Diode(Shunt Diode) : to clamp negative input ringing (the most negative voltage at Refer to Fig an input) V IK (MAX) : V in Fig. 8-11

17 8-17 Power Dissipation(ALS) I CC (avg) = ( I CCH + I CCL ) / 2 = ( 0.85 ma + 3 ma ) / 2 = 1.93 ma» Fig 에서 I CCH = 0.85 ma, I CCL = 3 ma P D (avg) = 1.93 ma X 5 V = 9.65 mw : 한개 IC 에 4 개 NAND gate 의전력소모량» 따라서한개의 Standard TTL NAND gate 전력소모량 = 2.4 mw power (1/4) Propagation Delays t pd (avg) = ( t PLH + t PHL ) / 2 = 6 ns» t PLH = 7 ns, t PHL = 5 ns ( 중간값 in Fig. 8-11) Exam. 8-2) Determine the maximum average power dissipation and the maximum average propagation delay of a single gate (74ALS00 in Fig. 8-11) P D (max) = I CC (max) X Vcc(max) = 1.93 ma X 5.5 V = mw 따라서 4 로나누면 P D (max) = 2.6 mw per gate» I CC (max) = [ I CCH (max) + I CCL (max) ] / 2 = ( 0.85 ma + 3 ma ) / 2 = 1.93 ma t pd (max) = [ t PLH (max) + t PHL (max) ] / 2 = ( 11 ns + 8 ns ) / 2 = 9.5 ns» t PLH (max) = 11 ns, t PHL (max) = 8 ns

18 TTL Series Characteristics (= TTL Subfamilies) 74 : Standard TTL No longer a reasonable choice for new designs 74L : Low-power TTL Low-power (1 mw) Longer propagation delay (33 ns) 74H : High-speed TTL High-speed (6 ns) Higher-power (23 mw) 74S : Schottky TTL 74S series reduces a storage-time delay by not allowing the transistor to go as deeply into saturation 74S00 NAND gate : Fig. 8-12(b)» High-speed (3 ns) i» Power dissipation (20 mw)» Darlington pair (Q3 and Q4) shorter output rise time when switching from ON to OFF * Schottky Barrier Diode(SBD) 금속과반도체를연결하면 ECL 보다는느리지만동작속도가빨라짐 ( Volt 에서동작 ) Forward Bias V 가증가하면서 Off 에서 On 된후, 다시 Forward Bias V 가감소하면서 On 에서 Off 되는시간 * Standard TTL Power Dissipation : 10 mw Propagation Delays : 9 ns Forward Bias V Pt Si Schottky Barrier Diode = Schottky Transistor

19 LS : Low-power Schottky TTL Lower-power (2 mw) Slower-speed (9.5 ns) 74AS : Advanced Schottky TTL Fastest TTL series (1.7 ns) 74AS compare with 74S : Tab ALS : Advanced Low-power Schottky TTL Lowest speed-power product (4.8 pj = 4 ns x 1.2mW) Lowest gate power dissipation (1.2 mw) 74ALS compare with 74LS : Tab F : Fast TTL Propagation delay (3 ns) Power dissipation (6 mw) 1980 년대 74LS TTL series 가주류를이루었으나현재는 CMOS series 74HC 와 74HCT series 가주류를이루고있음. 74AS 와 74ALS 사이의성능을갖고있음 Comparison of TTL Series Characteristics : Tab. 8-6 Exam. 8-3) Calculate the dc noise margins for a 74LS IC, and compare with the standard TTL noise margins. 74LS : V NH = V OH (min) - V IH (min) = 2.7 V V = 0.7 V (Standard = 0.4 V) V NL = V IL (max) - V OL (max) = 0.8 V V = 0.3 V (Standard = 0.4 V)

20 8-20 Exam. 8-4) Which TTL series can drive the most device inputs of the same series? 각각의 Series 마다 Fan-out 이다르며같은 series 에서는 Tab. 8-6 과같다. 따라서가장많은 input 을 drive 할수있는 series 는 74AS series 로 40 개이다. 만약다른 series 와혼용해서사용하는경우는각각 series 의 I OL, I IL, I OH, I IH 에따라다르며 Sec.8-5 에서공부함. 8-5 TTL Loading and Fan-Out Fan-Out : Load drive capability of an IC output LOW state ( Q3 = OFF ) : Fig. 8-13(a)» Q4 = ON : acting as current sink = I OL I OL : sum of I IL currents from each input» Q4 = ON : collector-emitter resistant is very small * 전류의방향 + : 전류가외부에서흘러들어옴 -: 전류가외부로흘러나감 But not zero : produce a voltage drop V OL V OL must not exceed V OL (max) : 0.4 Volt 이하 HIGH state ( Q4 = OFF ) : Fig. 8-13(b)» Q3 = ON : acting as current source = I OH I OH : sum of I IH currents from each input» Q3 = ON, Q4 = OFF : V OH = Vcc - I OH (R2 + emitter-base resistant + D1 resistant) V OH must not be lower than V OH (min) : 2.4 Volt 이상 Determining the Fan-Out An IC output can drive how many different inputs

21 V 0.7 V 0.1 V 0.4 V = V R2 3.6 V Typ. 2.4 V Low I OL I IL + I IL +.. High I OH I IH + I IH +..

22 8-22 Must Know I OL (max), I OH (max), I IL (max), I IH (max)» presented in the manufacturer s IC data sheet Exam. 8-5) How many 74ALS00 NAND gate inputs can be drive by a 74ALS00 NAND gate output? Refer to the data sheet in Fig. 8-11» Fan-out(LOW) : Fig I OL (max) / I IL (max) = 8 ma / 0.1 ma = 80» Fan-out(HIGH) I OH (max) / I IH (max) = 400 A / 20 A = 20 Overall Fan-Out = 20» Lower of the two values ( 80 and 20 ) Exam. 8-6) How many 74AS20 NAND gate inputs can be drive by the output of another 74AS20 NAND gate? Refer to the data sheet in Tab. 8-7» Fan-out(LOW) I OL (max) / I IL (max) = 20 ma / 0.5 ma = 40» Fan-out(HIGH) I OH (max) / I IH (max) = 2000 A / 20 A = 100 Overall Fan-Out = 40» Lower of the two values ( 100 and 40 )

23 8-23 Fan-Out in Combination of various logic families Method for determining the loading of any digital output» Step 1 : Fan-Out (HIGH) Add up the I IH for all inputs connected to an output. This sum must be less than the output s I OH specification» Step 2 : Fan-Out (LOW) Add up the I IL for all inputs connected to an output. This sum must be less than the output s I OL specification Specifications for input/output current : Tab. 8-7» I OH = I IL = negative : current flows out of the output (sourcing current)» I OL = I IH = positive : current flows into the output (sinking current) Exam. 8-7) Determine if there is a loading problem (when A 74ALS00 NAND gate outputs is driving three 74S gate inputs and one 7406 gate input). Refer to the data sheet in Tab. 8-7» Step 1 : Fan-Out (HIGH) Add all I IH = Total I IH = 3 ( I IH for 74S ) + 1 (I IH for 74 ) = 3 ( 50 A ) + 1 ( 40 A ) = 190 A This sum 190 A < 400 A ( I OH ) : No Problem» Step 2 : Fan-Out (LOW) Add all I IL = Total I IL = 3 ( I IL for 74S ) + 1 (I IL for 74 ) = 3 ( 2 ma ) + 1 ( 1.6 ma ) = 7.6 ma This sum 7.6 ma < 8 ma ( I OL ) : No Problem

24 8-24 Exam. 8-8) The output could drive how many additional 74ALS inputs without being overloaded in Exam. 8-7? Refer to the data sheet in Tab. 8-7» Additional current in LOW = I OL - I IL (sum of load) = 8 ma ma = 0.4 ma I IL = 0.1 ma, 따라서 drive up to four more 74ALS inputs» Additional current in HIGH = I OH - I IH (sum of load) = 400 A A = 210 A I IH = 20 A, 따라서 drive up to ten more 74ALS inputs This output can drive up to four more 74ALS inputs» Lower of the two values ( 10 and 4 ) Exam. 8-9) What is the maximum number of F/F CLR inputs that this gate can drive? The output of a 74AS04 inverter is providing the CLR signal to a parallel register(74as74 D F/F) Refer to the 74AS74 data sheet (not in Tab. 8-7 ) * PRE and CLR input of 74AS74 : I IL = 1.8 ma, I IH = 40 A * Output of 74AS04 : I OL = 20 ma, I OH = 2 ma (Tab. 8-7 )» Maximum number of inputs(low) I OH / I IH = 2 ma / 40 A = 50» Maximum number of inputs(high) I OL / I IL = 20 ma / 1.8 ma = Overall Fan-Out = 11» Lower of the two values ( 50 and 11 )

25 Other TTL Characteristics Several other characteristics of TTL logic must be understood Intelligently use TTL in a digital system application Unconnected Inputs (Floating) Unconnected TTL inputs act like a logical 1 Floating : input is left unconnected Unused Inputs» Diode D2 and D3 will not be forward-biased : D2 and D3 는모두 OFF 3 가지처리방법 따라서 A 와 B 에모두 1 이입력된것과같음» 1) Unconnected (Floating) : Fig. 8-15(a) act as a logical 1» 2) Connected to +5 V through a 1 k resistor : Fig. 8-15(b) 1 k resistor is for current protection of the emitter-base junctions in case of spikes on the power supply line.» 3) Tied to a used input : Fig. 8-15(c) This technique can be used for any type of gate Tied input do not exceed fan-out current : Exam Tied-Together Inputs Two (or more) TTL inputs on the same gate are connected together Fig. 8-8(a) 참조 NAND, AND gate 에만적용되며 NOR, OR 에는출력이항상 1 이되어사용불가능 NAND, AND gate 에만적용되며 NOR, OR 에는출력이항상 1 이되기때문에 GND 에연결해야함

26 8-26 Generally act as each individual input for fan-out counting» Only Exception : NAND and AND gates in LOW state Act as single input regardless of number tied together The reason for this characteristics : Fig. 8-8(b) p. 499 If input A and B are tied together and grounded, I IL is not changed (I IL is only limited by the R1) This situation is different for OR and NOR gates : Fig p. 502 OR and NOR gates do not use multiple-emitter transistor (OR and NOR gates have separate input transistor for each input) R1/R2 Exam. 8-10) Determine the load current at the output X in Fig ( Each gate is a 74LS, I IL = 0.4 ma, I IH = 20 A ) HIGH : gate 2 NAND 는 2 개 Input 으로계산 ( 40 A = 2 X 20 A ) LOW : gate 2 NAND 는 1 개 Input 으로계산 ( 0.4 ma ) Biasing TTL Inputs Low One-shot trigger on a positive transition : Fig. 8-17» Resistor R serves to keep the T input LOW while switch is open I IL will not exceed V IL (max) : the largest value of R» I IL X R max = V IL (max), 따라서 R max = V IL (max) / I IL

27 8-27 Exam. 8-11) Determine an acceptable value for R ( OS gate is a 74LS TTL, I IL = 0.4 ma ) R max = V IL (max) / I IL = 0.8 V / 0.4 ma = 2000 Standard resistor value for a good choice = 1.8 k Current Transients : Fig i=c(dv/dt) 에서 dt = 2 ns 임으로 i 가커진다. v=l(di/dt) 에서 dt = 2 ns 임으로 v 가커진다. Bypass Capacitor Whenever a totem-pole TTL output goes from LOW to HIGH, a high amplitude current spike is drawn from the Vcc supply.» 원인 : Q4 가 saturated (ON) 상태에있기때문에 Q3 보다 switching time 이늦어서순간적으로 Q3 와 Q4 가동시에 ON 이되는순간 (about 2 ns) 이존재. 이때 load capacitance 에의해비교적큰 surge current (30 to 50 ma) 발생. 이와동시에 Power Supply Line (PCB Pattern Line) 의 distributed inductance 가미분기의역할을하여 surge current 에의해 Voltage spike 가발생함 This spike can cause serious malfunctions» 해결책 : Power-Supply Decoupling Connect a 0.01 F or 0.1 F ceramic (low inductance) capacitor between Vcc and Ground near each TTL IC to short out high frequency spikes The Capacitor leads are kept very short to minimize series inductance Connect single large capacitor ( 2 to 20 F ) between Vcc and Ground on each board to filter out relatively low frequency variations in Vcc

28 8-28 Q4 ON OFF time > Q3 OFF ON time * 원인 : Q4 saturated, capacitive load Vout 0 1 Q4 on off

29 MOS Technology MOS digital ICs = MOSFET Normal Metal Oxide Semiconductor Field Effect Transistor Advantages Relatively simple and inexpensive to fabricate» 1/ 3 as complex as the fabrication of bipolar ICs (TTL, ECL, etc.) Less space on a chip (Small)» Do not use the IC resistor elements that take up so much of chip area» Suited for complex ICs such as microprocessor and memory chips TTL mw per gate Consumes very little power CMOS nw per gate MOS ICs are faster than 74, 74LS, and 74ALS TTL Disadvantage» 74AS TTL family is still as fast as the best MOS(but much greater power dissipation) Susceptibility to static-electricity damage The MOSFET» TTL devices are used in education (more durable for laboratory experimentation) 2 types of MOSFET Closed Open TTL 74AS : 1.7 ns CMOS 74AVC : 1.9~2.0 ns ECL 0.3 ns * Comparison -Fig. 8-8: TTL NAND -Fig. 8-21: NMOS Inverter -Fig. 8-23: CMOS NAND» Depletion MOSFET» Enhancement MOSFET : MOS digital ICs use enhancement MOSFETs exclusively

30 8-30 FET On Condition Schematic symbols for enhancement MOSFETs : Fig N-channel/P-channel : Gate, Drain, Source Basic MOSFET Switch N-channel MOSFET switching state : Fig. 8-20» OFF state : V GS = 0 Volt (R OFF = = open circuit)» ON state : V GS = + 5 Volt (R ON = 1 k ) : acts as load resistor Threshold voltage (V T ) 1.5 V : V GS -1.5V(P), V GS +1.5V(N) N- and P-channel switching characteristics : Tab. 8-8» Bias Voltage V DD : opposite polarity Drain is connected to V DD (N), Source is connected to V DD (P) P-channel MOSFET switching state : Fig Complementary MOS(CMOS) Logic + - Three categories : N-MOS, P-MOS, CMOS N-MOS» Uses only N- channel enhancement MOSFETs P-MOS» Uses only P- channel enhancement MOSFETs CMOS (Complementary MOS) : Sec. 8-9» Uses both P- and N- channel devices» - Complexity of the IC fabrication (lower packing density)» + High speed and Low power V DD GND - + GND V DD

31 8-31 CMOS Inverter : Fig V IN = + V DD : V OUT = 0 V» R OFF (Q1 = OFF) = 10 10» R ON (Q2 = ON) = 1 k V IN = 0 V : V OUT = + V DD» R ON (Q1 = ON) = 1 k» R OFF (Q2 = OFF) = CMOS NAND gate : Fig Both A = B = HIGH, X = LOW» Q1 = Q3 = OFF, Q2 = Q4 = ON A B X LOW LOW HIGH LOW HIGH HIGH HIGH LOW HIGH HIGH HIGH LOW CMOS NOR gate : Fig Both A = B = LOW, X = HIGH» Q1 = Q3 = ON, Q2 = Q4 = OFF A B X LOW LOW HIGH LOW HIGH LOW HIGH LOW LOW HIGH HIGH LOW

32 8-32 NAND gate NOR gate 1 off off 0 on 0 0 on on 1 1 on off off

33 8-33 CMOS Flip-Flops Fig. 5-6 Two CMOS NOR gates or NAND gates can be cross-coupled Fig Additional gating circuitry (Edge detector/pulse steering) is used : Fig. 5-25(p. 229) 8-9 CMOS Series Characteristics Compared with TTL Slower Lower power Better noise margin Greater supply voltage range Higher fan-out More dense Replacement Rules for Different Families/Series Pin-compatible» pin configuration must be same (pin 7 = GND, pin 14 = Vcc) Functionally equivalent» logic function must be same (6 D F/F with positive edge clock) Electrically compatible» two ICs can be connected directly to each other (without taking any special measures to ensure proper operation)

34 / series Oldest series (RCA) Very low power dissipation 3 to 15 V power- supply voltages Very slow Very low output current capability Not pin-compatible with any TTL series Not electrically-compatible with any TTL series 74C series Pin-compatible and functionally equivalent to TTL with same number Performance much like 4000 series 74HC/ HCT (high- speed CMOS) 10 times faster than 74C series Pin-compatible and functionally equivalent to TTL with same number 74HCT devices electrically compatible with TTL 74HC devices not electrically compatible with TTL

35 AC/ ACT (advanced CMOS) Functionally equivalent to TTL Not pin-compatible with TTL 74AC not electrically compatible with TTL 74ACT is electrically compatible with TTL Faster than HC series Device numbering different : 5 digit number (beginning with the digits 11)» 74AC11004 = 74HC04» 74ACT11293 = 74HCT293 74AHC (advanced high-speed CMOS) Newest series Three times faster than HC series Direct replacement for HC series BiCMOS logic (Bipolar + CMOS) Low-power of CMOS (75 % reduction over 74F family) + High-speed of Bipolar Pin-compatible with TTL and standard 5 V logic 74ABT : Advanced BiCMOS (second generation of BiCMOS)» high speed and 3.3 V low voltage

36 8-36 Power- supply voltage (V DD ) 4000/ and 74C : from 3 to 15 V 74HC/HCT, 74AHC/74AHCT and 74AC/ACT : from 2 to 6 V Logic Voltage Levels : Tab. 8-9 Voltage Levels of CMOS Logic» V OL is very close to 0 V» V OH is very close to 5 V 74ACT, 74AHCT and 74HCT» Electrically compatible with TTL Noise Margins CMOS devices have greater noise margins than TTL» High-state noise margin : V NH = V OH (min) - V IH (min) = = 1.4 v 74HC» Low-state noise margin : V NL = V IL (max) - V OL (max) = = 0.9 v 74HC Power Dissipation Low power dissipation in static state (not changing)» Typically 2. 5 nw per gate with V DD = 5 V Standard TTL 0.4 v Refer to next slide

37 8-37 Low power dissipation because of large resistances : Fig. 8-22» V IN = 0 V R ON (Q1) = 1 k, R OFF (Q2) = : always OFF MOSFET in the current path between V DD and GND I D = 0. 5 na : leakage current from V DD supply ( 5 V / = 0.5 na ) P D = 5 V x 0. 5 na = 2. 5 nw P D increases with Frequency : Fig Current spike : Each time a output switches from LOW to HIGH (same as Fig. 8-18)» this is due mainly to the charging current of the load capacitance» a transient charging current (I D ) must be supplied by V DD As switching frequency increases, P D will increase in proportion to the frequency» at higher frequencies, CMOS begins to lose its advantage over other logic families» at frequency near 2 to 3 MHz, CMOS gate will have the same average P D as a 74LS gate Fan-out - Gate output drives a total C LOAD of N X 5 pf : Fig. 8-26» capacitance load will increase the output switching time (proportion to the # of load N)» typically N = 50 fan-out for low frequency operation ( 1 MHz)» fan-out would have to be less for higher-frequency operation Switching Speed 4000 series NAND : t pd = 50 ns at V DD = 5 V» large R OUT and C LOAD (5 pf) serve to increase switch time Time-constant 증가» R OUT N-MOS 100 K fig.8-20 > CMOS (P-MOS) 1 K fig : CMOS speed up 74HC/ HCT series NAND : t pd = 8 ns

38 AC/ ACT series NAND : t pd = 4.7 ns 74AHC series NAND : t pd = 4.3 ns Unused inputs Never leave unconnected» Unconnected CMOS input is susceptible to noise and static charges Both P-channel and N-channel MOSFETs in the conductive state» Resulting in increased power dissipation and possible overheating Tied either to a fixed voltage level (GND or V DD ) or to another input Static Sensitivity Static charge damage breaks down thin oxide film s dielectric insulation Precautions to protect from ESD (ElectroStatic Discharge) 1) Connect the chassis of all test instruments, soldering-iron tips, and your work bench to earth ground 2) Connect yourself to earth ground with a special wrist strap 3) Keep ICs in conductive foam or aluminum foil 4) Avoid touching IC pins, and insert the IC into the circuit immediately after removing it from the protective carrier 5) Place shorting straps across the edge connectors of PC boards when the boards are being carried or transported 6) Do not leave any unused IC inputs unconnected, because open inputs tend to pick up stray static charges

39 8-39 Latch-Up 원인 :» Unavoidable existence of parasitic (unwanted) PNP and NPN transistors embedded in the substrate of MOS ICs» These parasitic transistors on a CMOS chip are triggered into conduction.» Latch-up can be triggered by high-voltage spikes or ringing at the device inputs and outputs» Device s maximum voltage ratings are exceeded (surge from power supply) 증상 : Turn permanently ON (Latch-Up)» Large current may flow and Destroy the IC 해결책 :» Modern CMOS ICs are designed with protection circuitry (to prevent Latch-up)» Well regulated power supply» Clamping diode can be connected externally to protect against such transients - industrial environments where high-voltage/high-current load(motor, relay, ) - refer to Fig. 8-12(b) and Fig. 8-40(d) : clamp the overshoot(+)/undershoot(-)» Unused inputs must be connected to GND or V DD due to Line RLC and Delay time

40 Low-Voltage Technology Low-Voltage Technology의필요성 Increase the Chip Density Valuable for battery operated equipment» Increase the overall chip power dissipation Raise the chip temperature above the maximum level allowed for reliable operation 해결책 : Chip operated at lower voltage level (1.2 ~ 3.5 V instead of 5 V) CMOS Family 74LVC, 74ALVC, 74LV, 74AVC, 74CBT, 74GTLP, 74TVC BiCMOS Family 74LVT, 74ALVT, 74ALB, 74VME Example of Texas Instrument : Tab Logic Family Life Cycle : Fig Open-collector/Open-drain Outputs Wired OR / Wired AND : connecting output together Connect the outputs of two or more logic gates 장점 : 출력단의 AND 또는 OR gate의수를줄일수있다.

41 8-41 Connecting CMOS Outputs Together : Fig Pull-up and Pull-down resistance would be the same ( 1 K ) Voltage on the common wire will be about half the supply voltage ( V OUT = V DD / 2 ) This voltage is in the indeterminate range and unacceptable for driving a CMOS input Connecting TTL totem pole Outputs Together : Fig Suppose that the Gate A output = HIGH and the Gate B output = LOW» One gate output is trying to go LOW while another gate output is trying to go HIGH Very low resistance load on Q3A ( 130 ) will draw a far greater current than rated to handle ( I OH = I OL : as high as 50 ma) Overheating and Device failure Open-Collector/Open-Drain Outputs Open-Collector TTL : Fig. 8-30(a)» Eliminate the Q3, D1, R4 : refer to Fig. 8-8 Rp = 5 V / 16 ma 3.1 K * Rated Standard TTL Current I OH = 0.4 ma, I OL = 16 ma Conventional CMOS/Totem-pole TTL outputs should not be tied together» Output : taken at Q4 s collector (Open = Unconnected)» External pull-up register Rp (= 4.7 ~10 K ) should be connected : Fig. 8-30(b) HIGH (= Q4 OFF) : V OH 5V LOW (= Q4 ON ) : V OL 0.4 V Open-Drain CMOS : Fig. 8-22» Remove the active pull-up transistor(output : taken at the drain of Pull-down TR) Refer to Fig. 8-38

42 8-42 Wired-AND Connection Wired-AND operation using open collector/drain gates : Fig. 8-31» Devices with OC/OD Outputs can be connected together safely» Dotted AND gate symbol eliminates the need for an actual AND gate» 단점 : much slower switching speed pull-up TR (Q3) to change up load capacitance rapidly(but no pull-up TR in OC/OD circuit) OC/OD circuits should not be used where speed is a principal consideration Open-Collector Buffer/Drivers Buffer, Driver or Buffer/Driver» Greater output current and/or voltage capability than an ordinary logic circuit Open-Collector buffer/driver IC : 7406 (Fig. 8-32, 8-33)» contain 6 INVERTER» sink up to 40 ma in the LOW state ; I OL = 8-20 ma in Totem pole» handle output voltage up to 30 V Output TR can be connected to a voltage greater than 5 V 예제 1) Drive a high-current, high-voltage load : Fig. 8-32» Q = 1 Output TR = ON 7406 output = LOW Output TR sinks the 25 ma of lamp current, LAMP = ON» Q = 0 Output TR = OFF 7406 output = Open Output TR turns off, no path for current, LAMP = OFF

43 8-43 예제 2) Drive a LED indicator(oc)/relay(od) : Fig. 8-33(a),(b)» Q = 1 Output TR = ON 7406 output = LOW Output TR provide a current path to ground, forward biased, LED/Relay = ON» Q = 0 Output TR = OFF 7406 output = Open 8-12 Tristate Logic Outputs Output TR turns off, no path for current, LED/Relay = OFF (a) Rs = 330 : LED 에흐르는전류 (Is) 제한, (b) D = 역기전력에의한 Reverse Current 방지 Tristate : A third type of TTL/CMOS output configuration Three possible output states : HIGH, LOW, High-Impedance» High-impedance (= Hi-Z) both transistor are turned off in the totem-pole arrangement output terminal is an open or floating (neither a LOW not a HIGH) Utilize the high-speed operation of the totem-pole arrangement Permit outputs to be connected together Tristate INVERTER Obtained by modifying the basic totem-pole circuit» 1) Enabled State ( OE = 1) : Fig. 8-35(a),(b) Output = Inverse of logic input A» 2) Disabled State ( OE = 0 ) : Fig. 8-35(c) Output = Hi-Z ( both TR OFF ) 1) Totem-pole 2) Open-collector/Drain 3) Tristate

44 8-44 Advantage of Tristate Outputs can be connected together (paralleled) without sacrificing switching speed.» When Enabled, Totem-pole outputs have a high-speed characteristic 주의사항 : Only one of output should be enabled at one time (Fig. 8-37)» 2 Output contention Fig and Current damage Fig Tristate Buffers Tristate noninverting buffers : Fig. 8-36» Control the passage of a logic signal from input to output» Two commonly used tristate buffer ICs : 74LS125, 74LS126 Differ only in the active state of ENABLE input ( E) Contain four noninverting tristate buffers (14 pin) Tristate buffers used to connect several signals to a common bus : Fig. 8-37» Transmit any one of A, B, and C signals over the bus line to other circuits by enabling the appropriate buffer» No more than one output should be enabled at one time : Only signal B is enabled Bus Contention : A signal on bus is a combination of more than one signal (Fig. 8-38) Tristate ICs : 74LS374 (Octal D-type FF with tristate output) 8-bit register made up of D-type FFs Outputs are connected to tristate buffers Refer to Fig. 8-28

45 74LS Active LOW

46 High-speed Bus Interface Logic Bus wire distance 4 inches Viewed as a transmission line Have inductance, capacitance, and resistance ( line impedance ) Transmission Line Theory Travel time down the wire : Delay time Reflected wave : Echoes Ringing : Line RLC and Delay time 5 Bus Termination Techniques Resistance Termination : Fig. 8-40(a)» Terminated with about 50 ( line impedance )» Not feasible : require too much current to maintain logic level voltages across such a low resistance Resistance/Capacitance Termination : Fig. 8-40(b)» Block the DC current when the line is not changing» But just same as resistor when the line is changing( = pulse ) Voltage Divider Termination : Fig. 8-40(c)» With resistances larger than the line impedance : reduce reflections» But with hundreds of bus lines : make heavy load on the power supply *Capacitor AC: Passing DC: Blocking

47 8-47 Diode Termination : Fig. 8-40(d)» Simply clips off or clamp the overshoot/undershoot of the ringing Series Resistance Termination : Fig. 8-40(e)» At the source, slows down the switching speed None of above methods are ideal IC manufacturers are designing new series of logic circuits that overcome many of these problems Texas Instruments Bus Interface Logic Series BTL(Backplane Transceiver Logic)» Specially designed to drive the relatively long busses that connect modules of a large digital system GTL(Gunning Transceiver Logic)» More suitable for high-speed busses within a single circuit board or between boards in small enclosures like a personal computer case» Voltage swing : 0.4 v / 1.2 v lower than TTL or CMOS» The bus used in the Pentium : GTL+ GTL Plus (= GTLP) by Fairchild LVDS(Low-Voltage Differential signaling)» Use two wires for each signal» Responds to the difference between two wires

48 ECL Digital IC Family ECL (Emitter-Coupled Logic) ECL operates on the principle of current switching Forward Bias V 가증가하면서 Off 에서 On 된후, 다시 Forward Bias V 가감소하면서 On 에서 Off 되는시간» TTL operates on the principle of voltage switching in the saturated mode Voltage switching speed is limited by the storage delay time ECL increases overall switching speed by preventing transistor saturation ECL is referred to as current-mode logic (CML) Basic ECL Circuit : Fig Supply voltage : V EE and V BB» produce an fixed current I E (remains around 3 ma in normal operation) Two logic levels» -1.7 V: logic 0 for ECL» -0.8 V: logic 1 for ECL I E flows through either Q2 or Q1 depending on V IN» V IN = 0 ( -1.7 V ) : Q2 = ON, Q1 = OFF ( I E 가 Q1 으로흐르지않고 Q2 로흐름 ) Vc1 = 0 V Vc2 = V: R2 의전압강하 = 300 x 3 ma (I E ) = -0.9 V» V IN = 1 ( -0.8 V ) : Q2 = OFF, Q1 = ON ( I E 가 Q2 로흐르지않고 Q1 으로흐름 ) Vc1 = V: R1 의전압강하 = 300 x 3 ma (I E ) = -0.9 V Vc2 = 0 V

49 Fig (a) Basic ECL Circuit (b) with addition of emitter followers ma * 1 K -1.7 v Logic v Logic 1 off on on off V E (Q1) = -5.2 I E * R3 = -5.2 (- 3) = V 0 : V V B (Q1) = V IN = 1 : V 0 : -2.2 (- 1.7) = -0.5 V OFF V BE (Q1) = 1 : -2.2 (- 0.8) = -1.4 V ON * 전위차 : V > -0.5 V -0.9 V V C1 V C2 = 0 V = 300 Ω X 3 ma = 0.9 V -1.7 v Logic 0 off on -0.8 V -1.7 V Logic 0 * ECL Inverter Circuit : Fig. 8-41(b) Emitter follower addition : Q3 / Q4 0 V -0.8 V -0.8 V Logic 1 V OUT1 V OUT2 = 0 + ( 0.8 ) = -0.8 V = ( 0.8 ) = -1.7 V

50 8-50 Vc1 and Vc2 are the complements of each other Output voltage levels are not the same as input voltage level Input = -1.7 V Output (Vc2) = -0.9 V V C1 +V BE» 해결책 : Fig. 8-41(b) addition of emitter follower Emitter follower subtracts 0.8 V from Vc1 and Vc2 : Vc1-0.8 V : 0 V+( V) = V (logic 1), (- 0.9 V)+ (- 0.8 V) =-1.7 V (logic 0) Emitter follower provides a very low output impedance ( 7 ) for large fan-out and fast charging of load capacitance Emitter follower produces two complementary output : V OUT1 = V IN, V OUT2 = V IN ECL OR/NOR Gate : Fig Basic circuit (Fig. 8-41) can be expanded to more than one input by paralleling transistor (Q1 and Q3) ECL characteristics Transistors never saturate» Very high switching speed ( ~ 1 ns ) Logic levels» -0.8 V for logical 1» -1.7 V for logical 0 Low noise margins ( ~ 250 mv)» Unreliable for use in heavy industrial environment

51 8-51 Generates normal output and its complement output» Eliminate the need for INVERTER Fan- out around mw power dissipation» Higher than with other logic families No noise spikes» Current switching ECL comparison with other logic families : Tab High speed (short propagation delay) : high clock rate High power dissipation Low noise margin Disadvantage of ECL Not a wide range of general-purpose logic devices» only special purpose ICs : high-speed data transmission, high-speed memory, highspeed arithmetic units Relatively low noise margins and high power dissipation 2 Negative power supply voltage ( V EE and V BB ) Difficult to use ECL devices with TTL or CMOS ICs» Logic levels are not compatible with other logic families

52 CMOS Transmission Gate(Bilateral Switch) CMOS Bilateral Switch : Fig Pass signals in both directions» CONTROL = HIGH : Both MOSFET = ON (Switch = closed)» CONTROL = LOW : Both MOSFET = OFF (Switch = open) Input can be either digital or analog signals 4016/74HC4016 Quad bilateral switch : Fig. 8-44» Independently controlled : CONT A, CONT B, CONT C, CONT D» Bi-directional : IN/OUT A, OUT/IN A Exam. 8-12) Describe the operation of the circuit of Fig OUTPUT SELECT = HIGH : upper s/w = open, lower s/w = closed (Y = V IN ) OUTPUT SELECT = LOW : upper s/w = closed, lower s/w = open (X = V IN ) 4316/74HC4316 : second power supply ( -V EE ), V OUT = from - V EE to + V DD» - V EE = 0 V V OUT = 0 ~ + V DD» - V EE = - X V V OUT = - V EE ~ + V DD = - X ~ + V DD

53 IC Interfacing Interface Connecting the output(s) of one circuit or system to the input(s) of another circuit or system Interfacing Logic ICs : Fig. 8-46» (a) no interface is needed (direct connect) : H is high enough, and L is low enough» (b) interface circuit is required : H is not high enough, or L is not low enough Input / Output currents with a supply voltage of 5 V : Tab Different families have different characteristics» Checking the device data sheets for values of input and output current/voltage parameters Interfacing 5 V TTL and CMOS : Fig no problem in low output 1) CMOS input current requirement : No problem» TTL output current (74LS : I OH = 0.4 ma) > CMOS input current (4000B : I IH = 1 A) Refer to Tab. 8-9» TTL output voltage (74LS : V OH = 2.4 V) < CMOS input voltage (4000B : V IH = 3.5 V)» Pull-up register : Fig * Low state current / voltage : No problem TTL output to rise to approximately 5 V * High state current : No problem 1) voltage : Problem 2) 2) CMOS input voltage requirement : Problem Refer to Tab. 8-12

54 8-54 Voltage requirements Driver Load V OH (min) > V IH (min) + V NH V OL (max) + V NL < V IL (max) Current requirements Driver Load I OH (max) > I IH Total sum I OL (max) > I IL Total sum V OL

55 8-55 CMOS Driving TTL CMOS Driving TTL in the HIGH State : Fig. 8-48(a)» CMOS output voltage(4000b : V OH = 4.95 V) > TTL input voltage (74LS : V IH = 2.0 V) No problem in the HIGH state Refer to Tab Refer to Tab. 8-9 min» CMOS output current(4000b : I OH = 0.4 ma) > TTL input current (74LS : I IH = 20 A) No problem in the HIGH state CMOS Driving TTL in the LOW State : Fig. 8-48(b)» CMOS output voltage(4000b : V OL = 0.05 V) < TTL input voltage (74LS : V IL = 0.8 V) No problem in the LOW state max» CMOS output current(4000b : I OL = 0.4 ma) = TTL input current (74LS : I IL = 0.4 ma) No problem in driving a single TTL load * A CMOS driver cannot supply enough current to the TTL load.» 따라서 1 개이상의 74LS 를구동하려면 74LS125 Buffer IC 사용 : Fig. 8-49(a) 4000B (I OL = 0.4 ma) can not drive even one input of 74 (I IL = 1.6 ma), and 74AS (I IL = 0.5 ma)» 또는 the load is divided up among multiple 4001 parts: Fig. 8-49(b) 4001B CMOS (I OL = 0.4 ma) can drive four 74ALS TTL (I IL = 100 ua)

56 8-56 HIGH state voltage / current : No problem Low state voltage : No problem Low state current : Problem Exam. 8-13) A 74HC output is driving inputs. Is this a good design?. I OL = 4 ma (74HC), I IL = 1.6 ma (7406) 1.6 ma x 3 = 4.8 ma, too much load current Exam. 8-14) A 4001B is driving 3 74LS inputs. Is this a well-designed circuit? I OL = 0.4 ma (4001B), I IL = 0.4 ma (74LS) : fan-out = 1 개 0.4 ma x 3= 1.2 ma, too much load current 8-17 Mixed-Voltage Interfacing Low-voltage outputs driving high-voltage loads Using open drain with pullup : 74LVC07 Fig. 8-50(a) Using a voltage-level translator : 74AVC1T45 Fig. 8-50(b) High-voltage outputs driving low-voltage loads Using 5 V tolerant inputs as buffer : 74LVC07A Fig Analog Voltage Comparators Analog Voltage Comparator : LM339 OP. Amp. Output = HIGH : + voltage input > - voltage input Output = LOW : - voltage input > + voltage input

57 8-57 Exam. 8-15) Design a circuit to interface the temperature sensor to the digital circuit. - The digital system alarm must sound when the temperature exceeds 100 F - The output voltage of LM34 temperature sensor goes up 10 mv per degree F Voltage output of the LM34 at 100 F = 100 F X 10 mv/ F = 1 V Vref = - voltage input Choose a bias current = 500 A, 따라서 R = 5 V / 500 A = 10 K Voltage divider 1 V : 4 V = 2 K : 8 K, Fig Troubleshooting Logic Pulser : Fig Logic pulser generates a short-duration pulse by pressing a pushbutton Logic pulser senses the existing voltage level at the node and produces a voltage pulse in the opposite direction» if node = LOW : produce a narrow positive-going pulse» if node = HIGH : produce a narrow negative-going pulse Logic pulser has a very low output impedance (2 or less), so that it can overcome the NAND gate s output and can change the voltage at the node. Logic pulser can not produce a voltage pulse at a node that is shorted directly to ground or Vcc. Using Logic Pulser and Probe to Test a Circuit : Fig Logic pulser manually injects a pulse into a circuit Logic probe monitors the circuit s response Logic pulser is applied to the circuit node without disconnecting the output of NAND gate almost shorted circuit to Vcc or GND

58 8-58 Finding Shorted Nodes Press the logic pulser button (when you touch a logic pulser and a logic probe to the same node)» if the probe = constant LOW and Pulse LED not flash : Fig. 8-54(a) the node is shorted to ground» if the probe = constant HIGH and Pulse LED not flash : Fig. 8-54(b) the node is shorted to Vcc

59 Characteristics of an FPGA Consider the electrical and timing characteristics for the Altera Cyclone II family of devices. A subcategory of PLD devices referred to as field programmable gate arrays (FPGAs). Power-Supply Voltage Two different power-supply voltages must be applied to a Cyclone II chip. V CCINT provides power for the internal logic of the chip. The nominal value is 1.2 V A separate supply voltage, V CCIO, will power the input and output buffers of the Cyclone chips. This value will be dependent on the desired output logic level(3.3/2.5/1.8/1.5 V) Logic Voltage Levels Cyclone devices support a variety of input/output standards that gives flexibility in system design Altera Cyclone II characteristics using general-purpose I/O standards: Tab. 8-13

60 8-60 Power Dissipation The Cyclone II devices use CMOS, so power consumption will be low power will be dependent on voltage level, frequencies & I/O signal loads. The Quartus II software has two tools to estimate the amount the power usage for an application.» The PowerPlay Early Power Estimator is typically used during the early stages of design.» The PowerPlay Power Analyzer is often used with sample test vectors, for more accurate estimate. Maximum Input Voltage and Output Current Ratings The Max. DC Input Voltage : 4.6 V Each output pin can sink up to 40mA / source up to 25 ma Switching Speed The speed of an application will be dependent upon the application and how it is implemented in the programmable device : Tab Cyclone II chips are available in three different speed grades ( 6, 7, and 8 )