THE IEEE802.11b standard 2.4-GHz band wireless LAN

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1 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver Tadashi Maeda, Member, IEEE, Noriaki Matsuno, Shinichi Hori, Tomoyuki Yamase, Member, IEEE, Takashi Tokairin, Kiyoshi Yanagisawa, Hitoshi Yano, Robert Walkington, Keiichi Numata, Nobuhide Yoshida, Yuji Takahashi, and Hikaru Hida, Member, IEEE Abstract This paper describes a m CMOS direct-conversion dual-band triple-mode wireless LAN transceiver. The transceiver has a concurrent dual-band low-noise amplifier for low power consumption with a low noise figure, a single widely tunable low-pass filter based on a triode-biased MOSFET transconductor for multi-mode operation with low power consumption, a DC-offset compensation circuit with an adaptive activating feedback loop to achieve a fast response time with low power consumption, and a 61-based low-phase-noise fractional-n frequency synthesizer with a switched-resonator voltage controlled oscillator to cover the entire frequency range for the IEEE WLAN standards. The transceiver covers both and GHz and has extremely low power consumption (78 ma in receive mode, 76 ma in transmit mode both at 2.4/5.2 GHz). A system noise figure of 3.5/4.2 db, a sensitivity of 93/ 94 dbm for a 6-Mb/s OFDM signal, and an error vector magnitude of 3.2/3.4% were obtained at 2.4/5.2 GHz, respectively. Index Terms Complementary metal-oxide semiconductor (CMOS) transceiver, dual-band, frequency synthesizer, IEEE a/b/g, low-noise amplifier (LNA), low-pass filter (LPF), orthogonal frequency division multiplexing (OFDM), triple-mode, voltage controlled oscillator (VCO), wireless LAN (WLAN). I. INTRODUCTION THE IEEE802.11b standard 2.4-GHz band wireless LAN (WLAN) has been extensively incorporated into batterydriven mobile devices, such as cell phones and PDAs, and is used throughout the world in corporate offices, at hot spots such as in airports and railway stations, and also in home networks. Recently, even faster 11a (5-GHz band) and 11g (2.4-GHz band) standard WLAN products based on orthogonal frequency division multiplexing (OFDM) have been released, raising expectations for further market expansion. In contrast to 2.4-GHz band WLAN, which uses the same frequency band as microwave ovens and medical equipment, 5-GHz band WLAN represented by the 11a standard causes little radio interference and can be used at a speed sufficiently high to transmit high-definition TV signals. Although dual-band CMOS transceivers used in IEEE a/b/g WLAN systems have been extensively developed [1] [5], demands for even lower power consumption and multi-standard transceiving have been increasing for portable Manuscript received February 24, 2006; revised July 10, The authors are with the System Devices Research Laboratories, NEC Corporation, Kawasaki, Kanagawa , Japan ( t-maeda@da.jp.nec. com). Digital Object Identifier /JSSC Fig. 1. Transceiver block diagram. applications like future multi-functional cellular phones with a longer battery life. Using the conventional dual-band architecture, which has a separate radio-frequency (RF) front-end for each frequency band, increases the footprint. Moreover, achieving a higher data rate by means of higher order modulation, a wider bandwidth, space-time diversity, and so on requires a lower phase noise and/or a higher signal-to-noise ratio. This paper describes a direct-conversion dual-band triplemode WLAN CMOS transceiver with a low noise figure and low power consumption. Section II describes the transmitter and receiver architectures. Section III describes the circuit implementation, particularly the key technical features for achieving: 1) a concurrent-conjugate-matching dual-band, low-noise amplifier (LNA) for low power consumption with a low noise figure; 2) a single, widely tunable, low-pass filter (LPF) based on an adaptive DC-current-control circuit, triode-biased MOSFET (ADTM) transconductor for multi-mode operation with low power consumption; 3) a DC-offset compensation circuit with an adaptive activating feedback loop (AAFL) to achieve a fast response time with low power consumption; and 4) a -based low-phase-noise fractional-n frequency synthesizer with a switched resonator, voltage-controlled oscillator (VCO) to cover the entire frequency range for the IEEE WLAN standards. Section IV presents some of the measured results, and Section V concludes the paper with a brief summary /$ IEEE

2 2482 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006 Fig. 2. Schematic diagram of dual-band LNA. II. ARCHITECTURE As shown in Fig. 1, both the receiver and transmitter use direct conversion and have fully differential signal paths. The receive path consists of a concurrent dual-band LNA followed by a direct down conversion mixer (MIX) and an analog base-band block. The base-band block consists of two programmable gain amplifiers (PGAs) with fast DC-offset compensation circuits, fourth-order Butterworth LPFs based on adaptive DC-current control, and a triode-biased (ADTM) transconductor. A previously reported 5-GHz band LNA topology [6] was modified and used to implement the dual-band design. A concurrent dual-band matching scheme is used to provide dual-band operation without increasing the circuit area. The 2.4- and 5-GHz band signals are amplified by simply changing the capacitor combination of the LNA matching circuit, which does not increase the chip area. Since low insertion-loss passive switches are commercially available, RF filters and off-chip passive switches combination can be used to avoid interference without significantly increasing noise figure. The signal is then directly down-converted to base-band signals through a pair of mixer and amplified by the PGA with a fast DC-offset cancellation loop. The base-band signals are low-pass filtered with a widely tunable LPF designed for multiple-channel-bandwidth systems (such as those compliant with the latest Japanese standard and with channel bandwidths of 5, 10, and 20 MHz). To reduce the effect of flicker noise, all the analog base-band circuits use pmos transistors as input devices. This is because flicker noise in pmos transistors is typically one to two orders of magnitude lower than that in nmos transistors. Finally, the signal is converted into a digital bit stream by a 10-bit 80-MHz analog-to-digital converter (ADC) of our companion base-band chip. The transmit path is composed of low-pass filters, doublebalanced modulators (MODs), and separate driver amplifiers (DAs) with envelope detectors for the 2.4- and 5-GHz bands, respectively. The DAs convert the differential signals into single-ended ones for use with off-chip power amplifiers (PAs). Using offchip high-efficiency PAs leads to a reduction in overall system power. The base-band signal from the 10-bit 80-MHz digital-toanalog converter (DAC) of the companion base-band chip is low-pass filtered by the LPFs, which are identical to those in the receive path, and up-converted to RF signals through corresponding single-sideband doubly balanced mixers. Due to the direct-conversion scheme of the transceiver, the fractional-n frequency synthesizer has to generate the in-phase and quadrature local oscillator (LO) signals for the 2.4- and 5-GHz bands at the same frequency as the transmitter and/or receiver signal carriers. A conventional configuration, in general, has a single-band VCO with a frequency two-thirds that of the 5-GHz LO to avoid pulling by the transmitter circuit [7], and the desired frequencies are generated using many dividers and/or mixers. This configuration thus consumes much power and has a narrow frequency tuning range. Our transceiver has a dual-band VCO with an oscillation frequency twice that of the desired LO frequency. This configuration generates the desired I/Q signals by using only one divider and does not require additional mixers, selectors, and/or dividers. The dual-band VCO, however, should be capable of wide- and high-frequency oscillation to cover the entire WLAN frequency range. The oscillation frequency is 9.8 to 11.9 GHz for the 5-GHz band and 4.8 to 5.0 GHz for the 2.4-GHz band. A switched resonator with a back-gate impedance-controlled MOS switch reduces parasitic capacitance, which interferes with the required performance. Moreover, to achieve a low-phase-noise local signal even at narrow frequency bandwidths of 5, 10, and 20 MHz, a -based frequency synthesizer architecture is used. III. CIRCUIT IMPLEMENTATION A. Receiver The dual-band LNA consists of a fully balanced, two-stage cascaded amplifier (LNA1, LNA2) with a concurrent-conju-

3 MAEDA et al.: A LOW-POWER DUAL-BAND TRIPLE-MODE WLAN CMOS TRANSCEIVER 2483 Fig. 3. Simulated results for LNA1 with constant NF circles in terms of source impedance. gate-matching circuit, a dual-band LC resonator switch, and an attenuator (Fig. 2). In the first stage LNA (LNA1), wide-frequency-band characteristics are achieved by using a low-pass input-matching circuit; high linearity with high common-mode noise immunity is achieved by using a tail resonator. Fig. 3 shows simulated constant noise figure (NF) circles at 2.48 and 5.2 GHz in terms of source impedance, where the source impedance seen from LNA1 was swept from 2.4 through 5.95 GHz. This figure shows that a NF below 2.5 db can be obtained in the 2.4- and 5-GHz bands. The two circles are large enough for small increments of NF. This means that variations in matching network impedance due to component tolerances in production will not degrade the NF drastically. At high input power, LNA2 turns off by means of the dual-band LC resonator passive switch and the signal bypasses through the attenuator, thus this leads to large third-order input-referred intercept (IIP3). The switch configuration copes with the low-impedance state created by the input and output capacitances of LNA2 when it is in the off state. When LNA2 turns off in the 5-GHz band, switches S1, S2, S3, and S4 are on, and S5, S6, S7, and S8 are off. The inductances for L5 L6 and L7 L8 were chosen to resonate with input capacitances and output capacitances of the LNA2 at the 5-GHz band, respectively. The result is high impedance for the LNA2 input and output. In the 2.4-GHz band, switches S1, S2, S3, and S4 are off, and S5, S6, S7, and S8 are on. This results in resonance for the parallel-connected inductors and capacitors (L1 L4, C1 C4) and in a stable high impedance state. Consequently, the signal is not transmitted to LNA2 in the off state for either band. Under this condition, LNA total power consumption is small by turning off LNA2. At low input power levels, a large power gain is required to achieve a low receiver NF for both the 2.4- and 5-GHz bands. Under this condition, all switches (S1 S8) are off. The output-matching circuits of LNA1 are parallel resonant circuits of Lo1-Co1 and Lo2-Co2; the input-matching circuits of LNA2 are series resonant circuits of L1-Ci1, and L2-Ci2. Here, Co1 and Co2 are the parasitic capacitances for the LNA1 Fig. 4. Simulated constant available-gain circles at 2.4 and 5.2 GHz in terms of LNA1 output impedance. output nodes, Ci1 and Ci2 are the parasitic capacitances for the LNA2 input nodes. When the parameters of the parallel- and series-connected LC circuits are set at the following equations: The reactance of the LNA1 output matching circuit and that of the LNA2 input matching circuit have the same value with opposite signs at the both frequencies, where and are the angular frequencies of 2.4 and 5.2 GHz, respectively, is the inductance of Lo1 and Lo2, is the output capacitance of LNA1, is the inductance of L1 and L2, and is the input capacitance of LNA2. Thus, the impedances of the two bands are matched by using this configuration without any other components. Since there is no active device between LNA1 and LNA2, this configuration minimizes noise figure [6]. Although the linearity of the receiver under this condition is dominated by the IIP3 of LNA2, LNA2 does not consume large amounts of power to achieve high IIP3. This is because the output power under these conditions is low. Fig. 4 shows a Smith chart with the loci of these matching circuit impedances against frequency and the constant available-gain circles at 2.4 and 5.2 GHz in terms of LNA1 output impedance. It shows that this circuit has conjugate matching at 2.4 and 5 GHz. The chart also indicates that variations in the matching network impedance do not drastically degrade the gain. The down-conversion mixer has a common-gate configuration (Fig. 5), which operates as a passive mixer and thus yields a high IIP3. Phase and gain mismatch are minimized by having the I/Q signal paths share a current source. Each PGA has folded configuration with source-degeneration pmos, as shown in Fig. 6. This configuration can increase linearity because of small stacking transistors. The gain is controlled by changing the resistor combination between the differential signal nodes. The 7-bit digital signal controls the resister

4 2484 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006 Fig. 5. Schematic circuit diagram of down-conversion mixer. Fig. 8. Schematic circuit diagram of widely tunable fourth-order Butterworth low-pass filter. Fig. 6. Schematic circuit diagram of programmable gain amplifier. Fig. 9. Schematic circuit diagram of ADTM transconductor. Fig. 7. Schematic circuit diagram of DC offset cancellation circuit. combination of each PGA; this can achieve 66-dB tuning with a gain step of 1 db. The static DC offset of the PGA input signal is compensated for by using a high-pass filter with a cut-off frequency of 150 khz (Fig. 7). The high-pass filter consists of MIM capacitor C1 and pmos (Q1, Q2). The Q1 and Q2 operate not only as a high-resistance resistor but also as a bias circuit for PGA. The dynamic DC offset is compensated for by using an AAFL consisting of an offset voltage detecting circuit and a tri-state buffer (Fig. 7). When the PGA output voltage exceeds the upper limit of the input-referred P-1 db for the following circuit, the offset voltage detecting circuit activates the feedback loop. That is, the tri-state buffer output is set to low so that the node voltage rapidly decreases. When the DC level exceeds the lower limit, the node voltage increases quickly. Since the PGA has a low- pass characteristic, the response of the PGA output signal is slow compared with that of the input signal. This causes an overshoot response of the loop, which minimizes the residual DC offset. Fast response with negligible power consumption is achieved since the feedback loop is activated only when the output signal exceeds the input referred P-1 db for the following circuit. Fig. 8 shows a schematic diagram of a widely tunable fourth-order Butterworth low-pass filter consisting of two bi-quad filters with a cascade connection. The filter employs newly developed adaptive DC-current-control triode-biased MOSFET transconductor (ADTM transconductor) core for wide frequency tuning and high linearity. In the transconductor core, shown in Fig. 9, the output signal of the cascode amplifier, which is composed of Q1, Q2, and current source CS0, is fed back to the Q1 drain through Q3, so that Q1 operates under constant drain-to-source bias conditions in the triode region. The dc current and transconductance of this circuit are determined by those of Q1: where is the input voltage to the gate, is the threshold voltage, and is the factor. These equations indicate that has linear dependence on under constant. This results in high linearity. Although the large is required at high, the adaptive DC-current-control circuit controls current CS1 and CS2 so as to compensate for the excess DC-current

5 MAEDA et al.: A LOW-POWER DUAL-BAND TRIPLE-MODE WLAN CMOS TRANSCEIVER 2485 Fig. 11. Schematic circuit diagram for envelope detectors. Fig. 10. Schematic circuit diagram of a parallel configuration ADTM transconductor. of current mirror circuit (Q3 and Q4) even under a high-gm condition. This is because the current mirror circuit operating in the saturation region does not need a large DC current. The transconductor is incorporated into the filter as a parallel configuration that operates in the balance mode (Fig. 10). This provides constant differential transconductance. The drain current signal of Q5 has the same magnitude and opposite polarity as that of Q3n because of the mirror circuit comprising Q6n, Q7n, and Q5. Thus, the desired differential signals from Q4 and Q5 are in-phase, that is, amplified, while the undesired commonmode signals caused by the nonlinearity are out-of-phase, that is, cancelled out. This leads to high linearity for a large input signal. The simulated tuning range of the fourth-order Butterworth low-pass filter was from 2 to 12 MHz. B. Transmitter The baseband I/Q signals in the transmitter chain are generated by 10-bit 80-MHz DACs in a companion digital baseband chip. The transmit baseband LPFs are identical to the ones used in the receiver. After reconstruction filtering, the modulated signal is up-converted into each RF frequency band by single-sideband doubly balanced mixers. The differential signal is subsequently converted into a single-ended one and further amplified by DAs. Off-chip power amplifiers are used to conserve overall system power. LO leakage in a direct-conversion transmitter occurs at the center of the RF signal frequency band. It is not possible to eliminate this with an RF filter. Although LO leakage and/or I/Q mismatches can be caused by various imbalances and mismatches both in the RF domain and baseband, they can be compensated for by applying a baseband DC offset, a phase-offset and a gain-offset. An active feedback system can correct most of these errors by measuring the RF constellation under a known test signal and using a linear correlator, commonly placed in the digital domain of the transceiver, to correct the offsets. Fig. 11 shows a schematic of the envelope detector, which are placed in each transmitter path followed by a low-pass filter and common drain output buffer to compensate for LO leakage and I/Q mismatches. The detector Fig. 12. Schematic block diagram of 61-based dual-band low-phase-noise fractional-n frequency synthesizer. consists of a resistor-loaded inverter in which a MOSFET has been pre-biased immediately below the threshold voltage, thus the circuit behaves as Class-B amplifier. The sensitivity to transistor corner variations is reduced by using current mirror biasing. The low-pass filter has a 20-MHz cutoff frequency and 48-dB suppression. C. Phase-Locked Loop (PLL) The -based dual-band low-phase-noise fractional-n frequency synthesizer consists of a dual-band VCO with a digitally controlled MIM capacitor bank, a divide-by-two circuit generating quadrature LO signals, an LO buffer, a pulse-swallowed dual-modulus divider, a third-order modulator, a chargepump (CP) with a cascode current mirror circuit, and a secondorder off-chip loop filter (LF) (Fig. 12). The dual-band VCO has a switched resonator with a back-gate impedance controlled MOS switch (Fig. 13). The resonator consists of tapped inductors with pmos switches and a 5-bit weighted digitally controlled MIM capacitor array. At high frequencies ( GHz), unused turns of the inductors are shorted by the pmos switches, reducing the inductance. When the switches are in off state, the inductance is large and the VCO oscillates at low frequencies. Since the back-gate impedance of the pmos switches in the off state is set high

6 2486 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006 Fig. 14. Simulated carrier-to-noise ratio for 61 modulator. Fig. 13. Schematic circuit diagram for dual-band VCO. by disconnecting the n-well from the, this configuration reduces the drain-to-substrate parasitic capacitance in the off state. The circuit can thus match two different tuning ranges and achieve a wide tuning range with a compact layout. The VCO gain is reduced without sacrificing the tuning range by dividing both frequency ranges into a total of 22 bands; a band is selected by changing the combination of capacitors in the MIM capacitor bank. Continuous frequency tuning within each band is achieved by using accumulation-mode nmos varactors. The frequency band is selected as follows. When the loop filter output voltage exceeds the VCO tuning range, the digital controller selects the appropriate frequency band by changing the capacitor combination. The controller also sets the loop filter voltage to the middle of the tuning voltage range and synchronizes the swallow counter output to the reference signal. This prevents unwanted ripples in the loop filter voltage and leads to high-speed frequency-band selection. The nmos switches in the capacitor bank have a configuration similar to that of the tapped inductor. This configuration reduces the drain-to-substrate parasitic capacitance in the off state to half, so this VCO configuration enables high-frequency oscillation with low phase noise. Since the fractional-n synthesizer permits operation with a high-frequency reference, the division ratio of the phase-locked loop can be set lower to achieve low in-band phase noise. However, fractional operation introduces quantization noise and the spurious signal. The PLL noise due to the modulator as a function of the modulator order is given by [9] Fig. 15. Die photograph of transceiver. pling frequency, is the offset frequency, is the modulator order, is the charge pump gain, is the VCO gain, and is the transfer function for the loop filter. is given by, and where is the synthesizer closed loop transfer function, is the spectrum of the quantization noise, is the sam- Fig. 14 shows the simulated carrier-to-noise ratio (CNR) for the modulator as a function of the modulator order; a 40-MHz reference clock was used as the sampling clock for the modulator, and the cutoff frequency of the loop filter was set to 300 khz. The third-order configuration is best because it results in the lowest noise characteristics within the desired offset frequency band. Since the main cause of the spurious signal in the PLL is the nonlinearity of the charge pump, a cascode current mirror configuration is used in the charge-pump circuit (Fig. 12). This circuit enlarges the output impedance of

7 MAEDA et al.: A LOW-POWER DUAL-BAND TRIPLE-MODE WLAN CMOS TRANSCEIVER 2487 Fig. 16. Total receiver gain and receiver noise figure as a function of baseband output frequency at (a) 2.4 and (b) 5.2 GHz. Fig. 18. Input-output characteristics of receiver path in maximum and minimum gain modes at (a) 2.4 and (b) 5.2 GHz. Fig. 17. Noise figure as a function of LO frequency at 2.4 and 5.2 GHz. the current source, thereby reducing the sourcing and sinking current mismatch. This reduces the level of the spurious signal. D. Power Consumption The simulated power consumption in each building block is as follows. In the receive path, RF front end including LNA and MIX consumes 20 ma, the analog baseband block including PGAs and LPFs consumes 14 ma. The power consumption of the analog baseband in transmit path is 10 ma, and that of the RF block including MOD and DAs is 40 ma. The power consumption of the PLL is 22 ma. The local buffer consumes 20 ma in Rx mode, and 8 ma in Tx mode. IV. MEASURED RESULTS The transceiver was fabricated using a m one-poly sixmetal (1P6M) CMOS process. A die photograph of the transceiver is shown in Fig. 15. The die was 4.2 by 4.1 mm. The total receiver gain and receiver noise figure at 2.4 and 5.2 GHz are plotted in Fig. 16(a) and (b) as functions of the baseband output frequency. Noise figures of 3.5 and 4.2 db were obtained at 2.4 and 5.2 GHz, respectively. These values are comparable to the lowest values reported to date for dual-band transceivers [1] [8]. As shown in Fig. 16, the maximum gain for the total receive path was 75 db for both frequencies. The total gain was controlled with a 1-dB gain step from 8 to 75 db. The figure Fig. 19. Transient responses of DC-offset cancellation circuit, including PGA, with (a) positive and (b) negative DC offsets. also shows that the cutoff frequency for the 5-GHz band can be tuned from 2.5 to 10 MHz, so the transceiver can support multiple-channel bandwidth systems. The small increase in the noise figure at 5 MHz mode was caused by the noise of feedback circuit in LPF. The receive path current consumption was 78 ma at high gain mode for both frequency bands. Fig. 17 shows the noise figure as a function of the local oscillator frequency for the 2.4- and 5-GHz bands at the maximum gain. The noise figure deviation was small, within 0.1 db for GHz, and 0.65 db for GHz. The input-output

8 2488 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006 Fig. 20. LO phase noise characteristics at (a) 2.4 and (b) 5.2 GHz. TABLE I SUMMARY OF TRANSCEIVER PERFORMANCE Fig QAM transmission constellation at 2.4 and 5.2 GHz. characteristics of the receive path in the maximum and minimum gain modes for the 2.4- and 5-GHz bands are plotted in Fig. 18(a) and (b). For the 2.4-GHz band, the local frequency was 2.48 GHz, and two-tone frequencies are depicted. The IIP3 was 7 dbm and 5 dbm for the maximum and minimum gain modes, respectively. For the 5-GHz band, the local frequency was 5.24 GHz, and two-tone frequencies are again depicted. The IIP3 was 5 and 21 dbm for the maximum and minimum gain modes, respectively. The dynamic performance of the DC-offset cancellation loop was measured by applying a sinusoidal signal superimposed on a step signal. Fig. 19(a) and (b) shows the transient responses of the loop with positive and negative DC offsets, respectively. The vertical axis is the voltage difference from the input referred P-1 db for the ADTM-LPF; the step voltage was 300 mv. The positive and negative DC-offset settling times were 0.05 and 0.08 s, respectively, and the loop had no serious overshooting. Fig. 20(a) and (b) plot the LO phase noise characteristics at 2.4 and 5.2 GHz, respectively; the bandwidth of the loop filter was set at 300 khz. The phase noise was 95 dbc/hz at a 100-kHz offset frequency for both frequencies. At a 1-MHz offset, a phase noise of 110 dbc/hz was obtained for both frequencies. The integrated rms phase errors within the signal bandwidth of 1.7 degree and 1.87 degree were obtained at 2.4 and 5.2 GHz, respectively. The spurious signal of the PLL was less than 66 dbc. In 6-Mb/s mode, sensitivities of 93 and 94 dbm were obtained at 2.4 and 5.2 GHz, respectively. In 36-Mb/s mode, the receiver achieved a sensitivity of 80 dbm for both frequencies. These sensitivities do not include the balun loss which was used in this measurement. Fig. 21 plots the 64 QAM transmit constellations for output frequencies of 2.4 and 5.2 GHz. The error vector magnitudes were 3.2 and 3.4% at 2.4 and 5.2 GHz, respectively; the output power was 10 dbm. Current consumption was 76 ma at a supply voltage of 1.8 V. The measured transceiver performance is summarized in Table I. V. CONCLUSION The developed transceiver supports worldwide dual-band WLAN systems with frequency ranges of 2.4 to 2.5 GHz and 4.9 to 5.95 GHz, and channel bandwidth ranges of 5 to 24 MHz. The receiver noise figures were 3.5 and 4.2 db, respectively, at a maximum gain of 75 db. The receiver IIP3 in maximum gain mode was 5 and 21 dbm at 2.4 and 5.2 GHz, respectively. The EVMs of the transmit signal were 3.2 and 3.4%, respectively. The current consumption was 78 ma for the receive path and 76 ma for the transmit path. ACKNOWLEDGMENT The authors are grateful to Mr. Takuji Mochizuki, Mr. Masaho Mineo, Dr. Shinichi Tanaka, and Dr. Naotaka Sumihiro for their valuable comments and continuous encouragement throughout this work.

9 MAEDA et al.: A LOW-POWER DUAL-BAND TRIPLE-MODE WLAN CMOS TRANSCEIVER 2489 REFERENCES [1] R. Ahola et al., A single-chip CMOS transceiver for a/b/g wireless LANs, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp , Dec [2] M. Zargari et al., A single-chip dual-band tri-mode CMOS transceiver for IEEE a/b/g wireless LAN, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp , Dec [3] K. Vavelidis et al., A dual-band GHz, GHz 0.18 m CMOS transceiver for a/b/g wireless LAN, IEEE J. Solid- State Circuits, vol. 39, no. 7, pp , Jul [4] L. Perraud et al., A direct-conversion CMOS transceiver for the a/b/g WLAN standard utilizing a Cartesian feedback transmitter, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp , Dec [5] Z. Xu et al., A compact dual-band direct-conversion CMOS transceiver for a/b/g WLAN, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2005, pp [6] T. Maeda et al., A low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidth of 5 20 MHz, IEEE J. Solid-State Circuits, vol. 41, no. 2, pp , Feb [7] A. Behzad et al., A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE a wireless LAN standard, IEEE J. Solid-State Circuits, vol. 38, no. 12, pp , Dec [8] A. Behzad et al., A GHz direct-conversion CMOS transceiver for IEEE a wireless LAN, in RFIC Symp. Dig. Papers, 2004, pp [9] T. A. D. Riley et al., Delta-sigma modulation in fractional-n frequency synthesis, IEEE J. Solid-State Circuits, vol. 28, no. 5, pp , May Tomoyuki Yamase (M 05) received the B.S. degree in electrical engineering from Michigan State University, Lansing, in He joined NEC Corporation in 2002 and has been developing RF CMOS circuits in the Ultra High Speed Device Research Laboratory of the System Devices Research Laboratories. Mr. Yamase is a member of the IEEE Solid-State Circuits Society. Takashi Tokairin received the B.E. and M.E. degrees in electronic engineering from Tohoku University, Sendai, Japan, in 2001 and 2003, respectively. He joined NEC Corporation in 2003 and has been researching and developing RF CMOS circuits in the System Devices Research Laboratory. Mr. Tokairin is a member of the Institute of Electronics, Information and Communication Engineers. Tadashi Maeda (M 05) received the B.E. and M.E. degrees in electronics engineering from the Toyohashi University of Technology, Toyohashi, Japan, in 1981 and 1983, respectively, and the D.E. degree in electronic engineering from the University of Tokyo, Tokyo, Japan, in In 1983, he joined NEC Corporation, where he researched and developed GaAs digital LSIs. Since 1999, he has developed RF CMOS circuits as a principal researcher in NEC s System Devices Research Laboratories. Dr. Maeda is a member of the International Solid-State Circuits Conference Wireless Communication Subcommittee, the IEEE Solid-State Circuits Society, and the Institute of Electronics, Information and Communication Engineers. Kiyoshi Yanagisawa received the B.E. and M.E. degrees in information science from Tohoku University, Sendai, Japan, in 1998 and 2000, respectively. He joined NEC Corporation in 2004 and has been researching and developing mixed-signal CMOS circuits in the System Devices Research Laboratory. Noriaki Matsuno received the B.E. and M.E. degrees in electrical engineering from Nagoya University, Nagoya, Japan, in 1991 and 1993, respectively. He joined NEC s Microelectronics Research Laboratories in 1993, where he researched and developed GaAs FET devices for high-speed digital LSIs. From 1995 to 1999, he researched and developed power MOSFETs and power MOS MMICs. From 1999 to 2003, he worked on device design, modeling, and simulations for SiGe HBTs. Since 2001, he has been working on the development of RF CMOS circuits. He is now a principal researcher in NEC s System Devices Research Laboratories. Mr. Matsuno is a member of the Institute of Electronics, Information and Communication Engineers. Engineers of Japan. Hitoshi Yano received the B.E. and M.E. degrees in electrical engineering from Hokkaido University, Sapporo, Japan, in 1985 and 1987, respectively. He joined NEC s Microelectronics Research Laboratories in From 1987 to 1994, he researched and developed GaAs FET devices, especially for development of two-dimensional device simulation technology. Since 1994, he has been designing GaAs heterojunction MMICs and CMOS MMICs. Mr. Yano is a member of the Institute of Electronics, Information and Communication Shinichi Hori received the B.E. degree in mechanics and the M.E. degree in electronics from the University of Tokyo, Tokyo, Japan, in 1998 and 2000, respectively. He joined NEC Corporation in 2000 and has been researching and developing RF CMOS circuits in the System Devices Research Laboratory. Mr. Hori is a member of the Institute of Electronics, Information and Communication Engineers. Robert Walkington received the B.Eng., M.Res., and Ph.D. degrees in electronic and electrical engineering from University College London, London, U.K., in 1998, 1999, and 2002, respectively. His Ph.D. work, in collaboration with Nokia Networks, U.K., was in the area of noise-shaping fractional-n frequency synthesizers. In 2002, he joined NEC s System Device Research Laboratories, where he has worked on the design of RF and mixed-signal CMOS circuits and integrated transceiver systems. His current research interests include system/circuit level co-optimization and broadband reconfigurable RFIC design.

10 2490 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006 Keiichi Numata received the B.E. and M.E. degrees in electrical engineering from Hokkaido University, Sapporo, Japan, in 1990 and 1992, respectively. In 1992, he joined NEC Corporation, where he researched and developed GaAs digital LSIs. Since 1999, he has been developing antenna switch ICs and RF CMOS circuits. He is now a principal researcher in the System Devices Research Laboratories. Yuji Takahashi received the B.E. and M.E. degrees in electrical engineering from Kobe University, Kobe, Japan, in 1991 and 1993, respectively. He joined NEC s System Devices Research Laboratory in 1993 and has been researching and developing RF and high-speed ICs for wireless communication. Mr. Takahashi is a member of the Institute of Electronics, Information, and Communication Engineers of Japan. Nobuhide Yoshida received the B.E. and M.E. degrees in electrical engineering from Keio University, Tokyo, Japan, in 1992 and 1994, respectively. He joined NEC s Microelectronics Research Laboratories in 1994, where he researched and developed GaAs digital LSIs. Since 2002, he has been developing RF CMOS circuits in the System Device Research Laboratories. Mr. Yoshida is a member of the Institute of Electronics, Information and Communication Engineers. Hikaru Hida (M 92) received the B.E. and M.E. degrees in electronics from Osaka University, Osaka, Japan, in 1980 and 1982, respectively, and the D.E. degree from the University of Tokyo, Tokyo, Japan, in He joined NEC Corporation in 1982 and is now a Senior Manager in the System Devices Research Laboratories. He has helped develop high-speed GaAs heterojunction FETs, analog and digital LSIs, and cutting-edge technologies for Si CMOS e-dram ASICs. His current interest is the research and development of RF-CMOS LSI core designs and GaAs MMIC/RF modules for mobile, WLAN, and WPAN applications, as well as that of high-speed CMOS SERDES and Gb/s GaAs and InP ICs for optical communications. Dr. Hida is a member of the IEEE Solid-State Circuits Society.