Enabling Power-Efficient Designs With III-V Heterojunction Tunnel FETs

Transcription

1 Enabling Power-Efficient Designs With III-V Heterojunction Tunnel FETs Moon S. Kim, Huichu Liu, Karthik Swaminathan, Xueqing Li, Suman Datta, and Vijaykrishnan Narayanan The Pennsylvania State University Oct 21, 2014

2 Why TFET? CMOS Scaling Challenge 3.0 Delay (us) 1.6 VCC and VT (V) V T V CC Slowdown of V CC scaling V Year Non-Scalability of V T 1.0 V V CC (V) V T K. Swaminathan et al, IEEE Micro H. Jeon Trans on Instrument and Measurement Slide 2

3 Why TFET? CMOS Scaling Challenge Subthreshold Swing (SS), I ON, and Leakage I OFF V DD S A. M. Ionescu, H. Riel, Nature A. M. Ionescu, IEDM short course Device: off on Due to 60 mv/dec CMOS SS limit, reducing V T (so as to reduce VDD for lower power) increases the leakage power significantly; With a lower SS, Tunnel FETs can operate at a lower VDD and lower power. Slide 3

4 Emerging Tunnel FETs (TFETs) Deway et al., IEDM 11 Mohata et al., VLSI 12 K. Moselund et al., IBM Mo High-k Pd (gate) N+ In 0.9 Ga 0.1 As (drain) i-in 0.9 Ga 0.1 As (channel) ILD Xing et al., IEDM 12 Rooyackers et al., IEDM nm P+ GaAs 0.18 Sb 0.82 (source) Bijesh R. et al., IEDM 13 A. M. Ionescu, IEDM short course Slide 4

5 III-V GaSb-InAs Heterojunction TFET (HTFET) HTFET: High I on and low SS achieved in n- and p- TFET with electrostatic improvement. Non-steep subthreshold slope is mainly due to the trap assisted tunneling (TAT) of the source/channel interface states. Further improvement on material interface is required. V. Narayanan, ISLPED Slide 5

6 Drain Current, log(id) III-V GaSb-InAs Heterojunction TFET (HTFET) HTFET Structure and Operation Essentially a gated reverse-biased p-i-n tunnel diode with asymmetrical source/drain doping; Band-to-Band tunneling (BTBT) induced from the sub-thermal switching leads to <60mV/dec SS, more abrupt ON-OFF transition compared to CMOS. Source Sub-60 mv/decade Gate Channel Drain I ON 60 mv/decade I OFF Gate Voltage, V G L. Chang IEEE Proceeding 2010; A. Seabaugh et al, IEEE Proc., Nov 2010 Slide 6

7 Modeling HTFET: Device to Architecture Verilog-A Device Model DC Validation TCAD Model Calibration Circuit & Architecture Design Transient Validation Slide 7

8 I DS (A/um) GaSb-InAs TFET Characteristics IDS (ua/um) DS = 0.4 V HTFET CMOS 30 mv/decade 60 mv/decade V GS (V) 0.8 IDS (ua/um) GS = 0.4 V High R O HTFET CMOS V DS (V) 0.8 Key Features Observed Steep-slope with High I low V CC High saturated small-signal R O Uni-directional Tunneling Negative differential resistance (NDR) NDR H. Liu et al, ISLPED13 B. Sedighi et al, A CNN-Inspired Mixed Signal Processor Based on Tunnel Transistors, DATE 2015, submitted Slide 8

9 GaSb-InAs TFET Characteristics (cont.) Example of Switch Design Considerations D Q LK D LK Reset Reset Q Reset Reset Type 2. Transmission based Si FinFET DFF Discharging path D Q Additional switch for bidirectional conduction Reset Reset Type 1. C 2 MOS DFF Type 2. Transmission based HTFET DFF Slide 9

10 GaSb-InAs TFET Characteristics (cont.) Capacitance versus gate voltage Suppressed capacitance (low voltage) Enhanced Miller effect (full voltage) VIN, VOUT (mv) V IN HTFET FO1 INV1 V OUT Enhanced Miller Cap Effect Time (ps) S. Mookerjea et al., EDL H. Liu et al., Tunnel FET RF rectifier design for energy harvesting applications, JETCAS 2014 Slide 10

11 GaSb-InAs TFET Characteristics (cont.) g m,htfet /g m,cmos f T (GHz) g m,htfet /g m,cmos Gain of g m R O f T CMOS HTFET Gain of g m R O HTFET CMOS HTFET CMOS 10 I DS (ua/um) I DS (ua/um) I DS (ua/um) The g m, HTFET is significantly larger than g m,cmos at a low current. With larger small-signal Ro, the intrinsic gain is further improved. HTFET has >300 GHz while CMOS shows higher f T at a higher current. The peak f T at a lower current makes HTFET attractive for low-power applications. B. Sedighi et al., Analog Circuit Design Using Tunnel-FETs, TCAS-I, to be published Slide 11

12 GaSb-InAs TFET Characteristics (cont.) Flicker noise is based on carrier number fluctuation The shot noise is modeled similar to tunnel diode The thermal noise model is similar to the Si-FinFET thermal model R. Pandey, et al., Electrical Noise in Heterojunction Interband Tunnel FETs, TED, Feb 2014 K. K. Hung, et al., A physics-based MOSFET noise model for circuit simulators, TED, May Slide 12

13 GaSb-InAs TFET Characteristics (cont.) [Hz -1 ] S id /i d 2 [Hz -1 ] Tunnel FET Flicker Noise (interface traps) TFET flicker noise highly depends on the spreading of the tunneled carriers in the channel (L ), which is independent of the channel-length (L g ) TFET Drain Current Flicker Noise Power Analytical Model: Bijesh, R., et al, DRC Rahul, P., et al, TED S id /i d x x10-8 T=77K V DS =0.5V 1.0x x10-9 1/f V DS =0.5V Measured: Scatter Analytical Model: Line B=1.46x10 6 V/cm T=77K B=4x10 6 V/cm Heteroj-TFET Homoj-TFET I DS [ A/ m] Heteroj-TFET Homoj-TFET Measurements T=300K Frequency [Hz] Slide 13

14 GaSb-InAs TFET Characteristics (cont.) Overall Electrical Noise: HTFETs vs Si FinFETs A larger noise of HTFET at low I D is due to the smaller tunneling length of carriers. HTFET noise reduces faster is due to faster carrier density increase. Competitive device noise Lower input-referred noise for HTFET with high gains Ref: Rahul, P., et al, TED Slide 14

15 HTFET Standard Cell Library Standard Cell Library Design Flow Enables quick evaluation of large-scale digital circuits. Behavioral Verilog System Designs (i.e., Arithmetic logics, Accelerators, Registers, etc.) Device: 20nm TFET [1] TFET Verilog-A models Architecture level Designs TFET Cell Library Synthesis Lookup tables Architecture Evaluation Existing Core Models (Ivybridge, UltraSparc) Modification of circuit designs: Due to uni-directional conduction of TFET, some circuits (i.e., MUX, DFF, Etc.) have been modified to retain the discharge path. Modification of design for cells Spice Simulations Optimization (timing and power) Generate Power and timing tables Architecture Simulation (Sniper, Gem5, GEMS) Timing + Power with Wire Models (McPAT) K. Swaminathan et al, DAC2014. Technology library database (*.db) System Evaluation Slide 15

16 Potential Design Space By TFETs Ultra Low power Energy Harvesting, Wearable Computing Architectural Innovation Heterogeneous multicores Simple/complex pipelined processors High Performance Computing Low power/ Embedded Systems Mobile/Tablet Processors Thermal-aware design Hotspots Domain-specific accelerators P 1 Q 1 - X + P 2 - X Q 2 3D Stacking Slide 16

17 Digital Benchmarking: Tunnel FET vs. CMOS V DD = 0.5 V unless indicated Lower energy than HP CMOS 0.2 V Lower delay than LP CMOS preferred corner 0.09 V Nikonov and Young, IEEE Proc Device simulations Estimated performance D. Nikonov and I. Young, Overview of beyond-cmos devices and a uniform methodology for their benchmarking, Proc. IEEE, 2013 Slide 17

18 Euclidean Distance Computation P 1 Q 1 P 2 Q 2 P 3 HTFET accelerators outperform a range of CMOS designs 6X energy reduction over iso-voltage CMOS design 30% less energy than iso-performance CMOS design Q 3 P 4 Q 4 P 63 Q 63 P 64 Q 64 Ref: K. Swaminathan et al, DATE Slide 18

19 Normalized Speedup CMOS-TFET Heterogeneous Multicores CMOS has higher peak high VDD TFET Processor is cooler Maximize performance using CMOS-TFET heterogeneous multicores Device replacement Dynamic task map Static power partition Dyn. task map Dyn. power partition Best-Base Baseline Hetero-Simple Hetero-DynWork Hetero-Auto Many TFET cores Few CMOS cores applu apsi equake gafort swim wupwise Average K. Swaminathan et al, ISCA Slide 19

20 Normalized Speedup TFET in 3D Stacked Multicore Systems Peak performance (thermal and yield constrained) Best CMOS perf Best TFET perf Relative performance of a 64-core CMOS and HTFET 3D stacked system, normalized to a single core CMOS performance. 18% speedup obtained by using HTFET cores over CMOS cores. Heterogeneous 3D stacked CMOS-HTFET multicore system can result in even higher speedups K. Swaminathan et al, ISCA Slide 20

21 Emerging System Design Using HTFET (H. Liu et al., ISLPED 13, JETCAS14) Increase the harvested power Reduce the power consumption Slide 21

22 High-Efficiency HTFET Rectifier Steep-Slope Features: Lower threshold voltage and resistive loss Uni-diretional Conduction: Lower leakage current from output to input H. Liu et al., Tunnel FET RF rectifier design for energy harvesting applications, JETCAS 2014 Slide 22

23 High-Efficiency HTFET Switched- Capacitor DC-DC Converter X V IN M1 M2 X Y Y M3 M4 Biasing Biasing C L V OUT R L V IN M1 M2 X Φ B Φ A M3 M4 V OUT C P C P φ A φ B Nonoverlapping phase driver Φ A Φ B Simplified phase generator (a) Conventional design (b) Proposed design (c) Efficiency Steep-Slope Features Lower threshold voltage and resistive loss Uni-diretional Current Conduction Lower leakage current from output to input Lower power by simplified phase generator Novel topology of doubling output gate control for lower resistive loss U. Heo et al., A high-efficiency switched-capacitance HTFET charge pump for low-input-voltage applications, VLSI Design 2015 Slide 23

24 Supply Current [ A] H. Liu., et al, ISLPED 14. Low-Noise HTFET Neural Amplifier Motivation: Low-Noise Amplifier for Neural Signal Recording Key Design Points: High gain Low input-referred noise Low power Nurmikko et al. Listening to Brain Microcircuits for Interfacing With External World, 2010 IEEE Proceeding. Steep-Slope Tunnel FET Neural Amplifier NEF=10 [4] [8] [9] HTFET Neural [6] Amplifier [this work] NEF=1 Si FinFET Neural Amplifier [this work] NEF CMOS,min v in,rms / BW [ V rms / Hz] [4] UU@JSSC 03 [6] UW@T.BCAS 12 [8] EPFL@EMBC 12 [9] MIT@T.BCAS 07 Slide 24

25 ENOBs ENOBs [bit] [bit] FoM FoM [fj/conversion-step] [fj/conversion-step] FoM [fj/conversion-step] Energy [kt] ENOBs ENOBs [bit] [bit] ENOBs ENOBs [bit] [bit] ENOBs [bit] ENOBs [bit] ENOBs ENOBs [bit] [bit] ENOBs [bit] SNDR SNDR [db] [db] Energy [kt] SAR: most digitized V REF 6bit Low-Power HTFET SAR ADC Analog Input V DD V REF MUX 6bit Successive External Approximation Register Comparator 8 fc 6bit 8 8 Binary Ideal Ideal HTFET HTFET 6bit Binary Decoder HTFET Ideal 7 HTFET Ideal Si Si Si FinFET HTFET Si Si Si FinFET 7 7 Si 7 7 Ideal Si Si FinFET 5.5 Si 6 Si FinFET Si Si FinFET Input 4 Frequencies [khz] Input Frequencies 0.5 [V] 0.5 [khz] Supply Voltages [V] Supply 0.4 [V] 6 Voltages [V] Supply Voltages [V] Supply Voltages [V] Supply Voltages [V] [V] Supply Voltages [V] [V] A/D Converter Survey Data 10 8 HTFET Enables Noise Limit 10 6 Energy Reduction Technology Limit E 10 4 Class_A ADCs ADCs E min ADCs SNDR [db] V 0.40 V V E Class-A 0.50V 0.40V 0.30V HTFET ADC Si FinFET ADC Emin SNDR [db] M. Kim., et al, TED 2014 Slide 25

26 Summary Promising Beyond-CMOS candidate Technology scaling has forced us to plan for the Post-CMOS era HTFET can complement, or replace CMOS enabling new design spaces Key devices features Steep-slope switching, Uni-directional current conduction, High small-signal R O in saturation, high g m /I ds, high f T at low current, Negative differential resistance (NDR), Competitive noise performance Parallelism and 3D design further improves performance Beneficial device features in analog/rf circuits design Amplifier Current-mode logic RF transceiver Rectifier DC-DC converter A/D converter Energy harvesting Power management Future work Device fabrication, modeling, circuit & system design and evaluations Slide 26

27 Contact Info Thanks Q&A Xueqing Li: Vijaykrishnan Narayanan: Suman Datta: Huichu Liu: Moon Seok Kim: Karthik Swaminathan: Slide 27