ΙΑΛΕΞΗ 11: Low Power Architectures

Transcription

1 ΗΜΥ 656 ΠΡΟΧΩΡΗΜΕΝΗ ΑΡΧΙΤΕΚΤΟΝΙΚΗ ΗΛΕΚΤΡΟΝΙΚΩΝ ΥΠΟΛΟΓΙΣΤΩΝ Εαρινό Εξάμηνο 2007 ΙΑΛΕΞΗ 11: Low Power Architectures ΧΑΡΗΣ ΘΕΟΧΑΡΙ ΗΣ Ack: Mary Jane Irwin, N. Vijaykrishnan Penn State University

2 Why worry about power? Power Dissipation Lead microprocessors power continues to increase 100 Power (Watts) P6 Pentium Year Power delivery and dissipation will be prohibitive Source: Borkar, De Intel

3 Why worry about power? Chip Power Density Sun s Surface Power Density (W/cm2) Nuclear Reactor Hot Plate Rocket Nozzle P6 Pentium chips might become hot Year Source: Borkar, De Intel

4 Chip Power Density Distribution Power Map On-Die Temperature Heat Flux (W/cm2) Temperature (C) Power density is not uniformly distributed; max junction temperature is determined by hot-spots Silicon is not a good heat conductor Impacts packaging, w.r.t. cooling and packaging costs Impacts reliability lifetime reduces by half for every 10ºC increase in temperature

5 Why worry about power? Machine Room Design Most data centers today cannot support the power and cooling requirements of a large number of new systems. Roger Schmidt, IBM Most data centers have a capacity of 40 to 70 W/ft 2 They will need to support 500 W/ft 2 in the next few years Large servers IBM z900 (single rack) 9.2 kw IBM p690 (single rack) 12.5 kw IBM p kw (1915 W/ft 2 )

6 Machine Room Cooling Implications If the trend continues a 200,000 ft 2 center could require 100 Megawatts of power Add 60MW for mechanical room support 160 MW is 16% of the output of a typical nuclear power plant Yearly electricity costs would exceed $100M Also cooling water resource and waste issues Physical size 14.5 sq ft Floor load size 36 sq ft Cooling size 190 sq ft (8% floor utilization) Source: E. Kronstadt, IBM Service size 25 sq ft

7 Why worry about power? The Environment EPA estimates that 20% of electricity generated is consumed by desktop computers Dedicated nuclear reactors for data centers??

8 Why worry about power? Battery Size/Weight 50 Rechargable Lithium Battery (40+ lbs) Nominal Capacity (W-hr/lb) Ni-Metal Hydride Nickel-Cadmium Year Expected battery lifetime increase over the next 5 years: 30 to 40% From Rabaey,, 1995

9 Why worry about power? Standby Power Drain leakage will increase as V T decreases to maintain noise margins and meet frequency demands, leading to excessive battery draining standby power consumption. 50% Year Power supply V dd (V) Threshold V T (V) KW and phones leaky! 40% 1.7KW Standby Power 30% 20% 10% 12W 88W 400W 0% Source: Borkar, De Intel

10 Power and Energy Figures of Merit Power consumption in Watts determines battery life in hours Peak power determines power ground wiring designs sets packaging limits impacts signal noise margin and reliability analysis Energy efficiency in Joules rate at which power is consumed over time Energy = power * delay Joules = Watts * seconds lower energy number means less power to perform a computation at the same frequency

11 Power versus Energy Watts Power is height of curve Lower power design could simply be slower Approach 1 Approach 2 Watts time Energy is area under curve Two approaches require the same energy Approach 1 Approach 2 time

12 PDP and EDP Power-delay product (PDP) = P av * t p = (C L V DD2 )/2 PDP is the average energy consumed per switching event (Watts * sec = Joule) lower power design could simply be a slower design Energy-delay product (EDP) = PDP * t p = P av * t p 2 EDP is the average energy consumed multiplied by the computation time required takes into account that one can trade increased delay for lower energy/operation (e.g., via supply voltage scaling that increases delay, but decreases energy consumption) E n e r g y - D elay (norm alized) energy-delay energy delay allows one to understand tradeoffs better Vdd (V)

13 better Understanding Tradeoffs Which design is the best (fastest, coolest, both)? Energy b Lower EDP c a d 1/Delay better

14 CMOS Energy & Power Equations E = C L V DD 2 P t sc V DD I peak P 0/1 1/0 + V DD I leak f = P * f clock P = C L V DD2 f + t sc V DD I peak f + V DD I leak Dynamic power Short-circuit power Leakage power

15 Dynamic Power Consumption Vdd Vin Vout C L Energy/transition = C L * V DD 2 * P 0 1 f 0 1 P dyn = Energy/transition * f = C L * V DD 2 * P 0 1 * f P dyn = C EFF * V DD2 * f where C EFF = P 0 1 C L Not a function of transistor sizes! Data dependent - a function of switching activity!

16 Lowering Dynamic Power Capacitance: Function of fan-out, wire length, transistor sizes Supply voltage: Has been dropping with successive generations P dyn =C L V DD2 P 0 1 f Activity factor: How often, on average, do wires switch? Clock frequency: Increasing

17 Short Circuit Power Consumption Vin I sc Vout C L Finite slope of the input signal causes a direct current path between V DD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting.

18 Short Circuit Currents Determinates E sc = t sc V DD I peak P 0 1 P sc = t sc V DD I peak f 0 1 Duration and slope of the input signal, t sc I peak determined by the saturation current of the P and N transistors which depend on their sizes, process technology, temperature, etc. strong function of the ratio between input and output slopes - a function of C L

19 Impact of C L on P sc I sc 0 I sc I max Vin Vout Vin Vout C L C L Large capacitive load Small capacitive load Output fall time significantly larger than input rise time. Output fall time substantially smaller than the input rise time.

20 I peak as a Function of C L x C L = 20 ff When load capacitance is small, I peak is large. 1.5 I peak (A) x time (sec) C L = 100 ff C L = 500 ff Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals - slope engineering. 500 psec input slope

21 P sc as a Function of Rise/Fall Times V DD = 3.3 V When load capacitance is small (t sin /t sout > 2 for V DD > 2V) the power is dominated by P sc 4 P normalized V DD = 2.5 V V DD = 1.5V If V DD < V Tn + V Tp then P sc is eliminated since both devices are never on at the same time. 0 2 t sin /t sout 4 W/L p = μm/0.25 μm W/L n = μm/0.25 μm C L = 30 ff normalized wrt zero input rise-time dissipation

22 Leakage (Static) Power Consumption V DD I leakage Vout Drain junction leakage Gate leakage Subthreshold current Sub-threshold current is the dominant factor. All increase exponentially with temperature!

23 Leakage Current Mechanisms Source I 7 I 8 Polysilicon Gate p substrate Bulk (Body) Gate oxide Drain n+ I n+ 2 I 3 I 6 I 5 I 4 I 1 I 1 I 2 I 3 I 4 I 5 I 6 I 7 I 8 p-n junction reverse bias current (drain junction) weak inversion (subthreshold current) DIBL GIDL punchthrough narrow width effect gate oxide tunneling (gate leakage) hot carrier injection

24 Leakage as a Function of V T Continued scaling of supply voltage and the subsequent scaling of threshold voltage will make subthreshold conduction a dominate component of power dissipation ID (A ) 10-7 VT=0.4V VT=0.1V An 90mV/decade V T roll-off - so each 255mV increase in V T gives 3 orders of magnitude reduction in leakage (but adversely affects performance) VGS (V)

25 Exponential Increase in Leakage Currents I leakage (na/μm) Temp(C) From De,1999

26 CMOS Energy & Power Equations E = C L V DD 2 P t sc V DD I peak P 0/1 1/0 + V DD I leak f = P * f clock P = C L V DD2 f + t sc V DD I peak f + V DD I leak Dynamic power (~90% today and decreasing relatively) Short-circuit power (~8% today and decreasing absolutely) Leakage power (~2% today and increasing)

27 Power and Energy Design Space Constant Throughput/Latency Variable Throughput/Latency Energy Design Time Non-active Modules Run Time Active (Dynamic) Leakage (Standby) Logic design Reduced V dd TSizing Multi-V dd Multi-V T Stack effect Pin ordering Clock Gating Sleep Transistors Multi-V dd Variable V T Input control DFS, DVS (Dynamic Freq, Voltage Scaling) Variable V T

28 Power and Energy Design Space Constant Throughput/Latency Variable Throughput/Latency Energy Design Time Non-active Modules Run Time Active (Dynamic) Leakage (Standby) Logic design Reduced V dd TSizing Multi-V dd Multi-V T Stack effect Pin ordering Clock Gating Sleep Transistors Multi-V dd Variable V T Input control DFS, DVS (Dynamic Freq, Voltage Scaling) Variable V T

29 Dynamic Power as a Function of V DD Decreasing the V DD decreases dynamic energy consumption (quadratically) But, increases gate delay (decreases performance) t p(normalized) V DD (V) Determine the critical path(s) at design time and use high V DD for the transistors on those paths for speed. Use a lower V DD on the other gates, especially those that drive large capacitances (as this yields the largest energy benefits).

30 Multiple V DD Considerations How many V DD? Two is becoming common Many chips already have two supplies (one for core and one for I/O) When combining multiple supplies, level converters are required whenever a module at the lower supply drives a gate at the higher supply (step-up) If a gate supplied with V DDL drives a gate at V DDH, the PMOS never turns off V DDH - The cross-coupled PMOS transistors do the level conversion - The NMOS transistor operate on a V out reduced supply VDDL V in Level converters are not needed for a step-down change in voltage Overhead of level converters can be mitigated by doing conversions at register boundaries and embedding the level conversion inside the flipflop (see Figure 11.47)

31 Dual-Supply Inside a Logic Block Minimum energy consumption is achieved if all logic paths are critical (have the same delay) Clustered voltage-scaling Each path starts with V DDH and switches to V DDL (gray logic gates) when delay slack is available Level conversion is done in the flipflops at the end of the paths

32 Power and Energy Design Space Constant Throughput/Latency Variable Throughput/Latency Energy Design Time Non-active Modules Run Time Active (Dynamic) Leakage (Standby) Logic design Reduced V dd TSizing Multi-V dd Multi-V T Stack effect Pin ordering Clock Gating Sleep Transistors Multi-V dd Variable V T Input control DFS, DVS (Dynamic Freq, Voltage Scaling) Variable V T

33 Stack Effect Subthreshold leakage is a function of the circuit topology and the value of the inputs V T = V T0 + γ( -2φ F + V SB - -2φ F ) where V T0 is the threshold voltage at V SB = 0; V SB is the sourcebulk (substrate) voltage; γ is the body-effect coefficient A B V X I SUB A A B V X B Out 0 0 V T ln(1+n) V GS =V BS = -V X V GS =V BS =0 1 0 V DD -V T V GS =V BS = V SG =V SB =0 Leakage is least when A = B = 0 Leakage reduction due to stacked transistors is called the stack effect

34 Short Channel Factors and Stack Effect In short-channel devices, the subthreshold leakage current depends on V GS,V BS and V DS. The V T of a short-channel device decreases with increasing V DS due to DIBL (drain-induced barrier loading). Typical values for DIBL are 20 to 150mV change in V T per voltage change in V DS so the stack effect is even more significant for short-channel devices. V X reduces the drain-source voltage of the top nfet, increasing its V T and lowering its leakage even more For our 0.25 micron technology, V X settles to ~100mV in steady state so V BS = -100mV and V DS = V DD -100mV which is 20 times smaller than the leakage of a device with V BS = 0mV and V DS = V DD

35 Leakage as a Function of Design Time V T Reducing the V T increases the subthreshold leakage current (exponentially) 90mV reduction in V T increases leakage by an order of magnitude ID (A ) But, reducing V T decreases gate delay (increases performance) VGS (V) VT=0.4V VT=0.1V Determine the critical path(s) at design time and use low V T devices on the transistors on those paths for speed. Use a high V T on the other logic for leakage control. A careful assignment of V T s can reduce the leakage by as much as 80%

36 Dual-Thresholds Inside a Logic Block Minimum energy consumption is achieved if all logic paths are critical (have the same delay) Use lower threshold on timing-critical paths Assignment can be done on a per gate or transistor basis; no clustering of the logic is needed No level converters are needed

37 Power and Energy Design Space Constant Throughput/Latency Variable Throughput/Latency Energy Design Time Non-active Modules Run Time Active (Dynamic) Leakage (Standby) Logic design Reduced V dd TSizing Multi-V dd Multi-V T Stack effect Pin ordering Clock Gating Sleep Transistors Multi-V dd Variable V T Input control DFS, DVS (Dynamic Freq, Voltage Scaling) Variable V T

38 Reducing Power and Energy of Memories Active power in memory of m columns and n rows P = V DD I DD where I DD = I array + I decode + I periphery = [mi act + m(n-1)i hld ] + [(n+m)c DE V int f] + [C PT V int f+ I DCP ] As expected, it is proportional to the size of the memory and is typically dominated by the array Partition the memory array into multiple smaller banks so that only the addressed bank is activated improves speed and lowers power - word line and bit line capacitances are reduced - number of bit cells activated reduced At some point the delay and power overhead associated with the bank decoding circuit dominates (2 to 8 banks typical)

39 Divided Word Line Divide RAM cells in each row into blocks where the cells in each block are accessed by a local word line (LWL) Row block WL i Local decoder WL i+1 LWL i LD RAM cell LWL i+1 BL j BL j+1 BL j+m LD BSL Block select line Only the memory cells in the activated block have their bit line pairs driven improves speed (by decreasing word line capacitance) lowers power dissipation (by decreasing the number of BL pairs activated)

40 Bit Line Segmentation Divide RAM cells in each column into blocks where each block has its own local bit line (LBL) - only the memory cells in the activated block present a load on the bit line lowers power dissipation (by decreasing bit line capacitance) - e.g., from more than 1pF for a 16Kb DRAM to ~200fF for a 64Mbit DRAM SWL i,j Switch to isolate segment SWL i+n,j LBL i,j WL i Row decoder logic also identifies the segment (SWL) Has minimal effect on performance BL j LBL i+n,j

41 Glitch Reduction by Pipelining Glitches depend on the logic depth of the circuit - gates deeper in the logic network are more prone to glitching arrival times of the gate inputs are more spread due to delay imbalances usually affected more by primary input switching Reduce logic depth by adding pipeline registers additional energy used by the clock and pipeline registers Fetch Decode Execute Memory WriteBack PC Instruction MAR I$ D$ MDR pipeline stage isolation register clk

42 Power and Energy Design Space Constant Throughput/Latency Variable Throughput/Latency Energy Design Time Non-active Modules Run Time Active (Dynamic) Leakage (Standby) Logic design Reduced V dd TSizing Multi-V dd Multi-V T Stack effect Pin ordering Clock Gating Sleep Transistors Multi-V dd Variable V T Input control DFS, DVS (Dynamic Freq, Voltage Scaling) Variable V T

43 Clock Gating Most popular method for power reduction of clock signals and functional units Gate off clock to idle functional units e.g., floating point units need logic to generate disable signal - increases complexity of control logic - consumes power - timing critical to avoid clock glitches at OR gate output additional gate delay on clock signal - gating OR gate can replace a buffer in the clock distribution tree clock R e g disable Functional unit

44 Clock Gating in a Pipelined Datapath For idle units (e.g., floating point units in Exec stage, WB stage for instructions with no write back operation) Fetch Decode Execute Memory WriteBack PC Instruction MAR I$ D$ MDR clk No FP No WB

45 Power and Energy Design Space Constant Throughput/Latency Variable Throughput/Latency Energy Design Time Non-active Modules Run Time Active (Dynamic) Leakage (Standby) Logic design Reduced V dd TSizing Multi-V dd Multi-V T Stack effect Pin ordering Clock Gating Sleep Transistors Multi-V dd Variable V T Input control DFS, DVS (Dynamic Freq, Voltage Scaling) Variable V T

46 Dynamic Frequency and Voltage Scaling Always run at the lowest supply voltage that meets the timing constraints DFS (dynamic frequency scaling) saves only power (e.g., Intel s SpeedStep) DVS (dynamic voltage scaling) + DFS saves both energy and power (e.g., Transmeta s LongRun) A DVS+DFS system requires the following A programmable clock generator (PLL) - PLL from 200MHz 700MHz in increments of 33MHz A supply regulation loop that sets the minimum V DD necessary for operation at the desired frequency - 32 levels of V DD from 1.1V to 1.6V An operating system that sets the required frequency + supply voltage to meet the task completion deadlines - heavier load ramp up V DD, when stable speed up clock - lighter load slow down clock, when PLL locks onto new rate, ramp down V DD

47 Dynamic Thermal Management (DTM) An example of DVS + DFS in action Trigger mechanism: onchip temperature sensors Based on differential voltage change across two diodes of different sizes Usually requires more than one sensor Hysteresis and delay are problems When to begin responding? Trigger level set too high means higher packaging costs Trigger level set too low means frequent triggering and loss in performance Choose trigger level to exploit difference between average and worst case power

48 DTM Initiation and Response Mechanisms Operating system or micro-architectural initiation mechanism? Hardware support can reduce the performance penalty by 20-30% Response mechanism DVS+DFS Incurs some delay since there is a OS context switch needed to set the new level of DVS + DFS Increasing the trigger level reduces the frequency of context switching to set DVS + DFS The use of a thermal window (100Kcycles+) can help to smooth short thermal spikes

49 DTM Activation and Deactivation Cycle temperature Cooling capacity without DTM Cooling capacity with DTM DTM trigger level savings Trigger Reached Turn Response On Check Temp Check Temp Turn Response Off Initiation Delay Response Delay Policy Delay Shutoff Delay Initiation Delay OS interrupt/handler Response Delay Invocation time (adjust clock, V DD ) Policy Delay Number of cycles engaged Shutoff Delay Disabling time (re-adjust clock, V DD )

50 Power and Energy Design Space Constant Throughput/Latency Variable Throughput/Latency Energy Design Time Non-active Modules Run Time Active (Dynamic) Leakage (Standby) Logic design Reduced V dd TSizing Multi-V dd Multi-V T Stack effect Pin ordering Clock Gating Sleep Transistors Multi-V dd Variable V T Input control DFS, DVS (Dynamic Freq, Voltage Scaling) Variable V T

51 Speculated Power of a 15mm μp Power (Watts) Power (Watts) μ, 15mm die, 2V 0% 0% 0% 0% 1% 1% 1% 2% 3% Temp (C) 90 Leakage Active Leakage 0.13μ, 15mm die. 1V Active 26% 1% 2% 3% 5% 8% 11% 15% 20% Temp (C) Power (Watts) Power (Watts) μ, 15mm die, 1.4V Active 0% 0% 1% 1% 2% 3% 5% 7% 9% 40 6% μ, 15mm die, 0.7V Leakage Temp (C) 41% 49% 56% 33% 26% 19% 9% 14% Leakage Active Temp (C)

52 V T (V) Review: Variable V T at Run Time Reducing the V T increases the sub-threshold leakage current (exponentially) V T = V T0 + γ( -2φ F + V SB - -2φ F ) where V T0 is the threshold voltage at V SB = 0, V SB is the sourcebulk (substrate) voltage, γ is the body-effect coefficient But, reducing V T decreases gate delay (increases performance) For an n-channel device, the substrate is normally tied to ground (V SB = 0) A negative bias on V SB causes V T to increase Adjusting the substrate bias at run time is called adaptive bodybiasing (ABB) or dynamic threshold scaling (DTS) - Requires a triple well fab process V SB (V)

53 DTS DTS can accomplish a variety of goals Lower the leakage in standby mode by increasing V T to its maximum value Compensate for threshold variations across the chip during normal operation Throttle the throughput (by increasing V T ) to lower both the active and leakage power based on performance requirements V SB,p V SB,n Substrate biasing can be implemented on a complete chip, on a block-by-block basis, or on a cell-by-cell basis. Per-cell granularity of substrate biasing has an area cost Unfortunately, the effectiveness of DTS is decreasing with technology scaling due to inherently lower bodyeffect factors

54 Power and Energy Design Space Constant Throughput/Latency Variable Throughput/Latency Energy Design Time Non-active Modules Run Time Active (Dynamic) Leakage (Standby) Logic design Reduced V dd TSizing Multi-V dd Multi-V T Stack effect Pin ordering Clock Gating Sleep Transistors Multi-V dd Variable V T Input control DFS, DVS (Dynamic Freq, Voltage Scaling) Variable V T

55 Reducing Power in Standby (Sleep) Mode For idle components, all power dissipation is due to leakage Can reduce leakage by DTS V DD Or can reduce leakage by gating the supply rails when the circuit is in sleep mode in normal mode, sleep = 1 and the sleep transistors must present as small a resistance as possible (via sizing) in sleep mode, sleep = 0, the transistor stack effect reduces leakage by orders of magnitude!sleep sleep Virtual V DD Virtual GND Or can eliminate leakage by switching off the power supply (but lose the memory state)

56 Reducing Standby Power in Memories Leakage in memory arrays is becoming a major issue leakage increase from 0.18μm to 0.13 μm is a factor of almost 7 Techniques to control memory array leakage turn off unused banks by switching off the power supply apply DTS to non-active cells (maintains state) - memory cannot be accessed at speed when running on the lower V T exploit transistor stacking (maintains state) lower the supply voltage (maintains state) - memory cannot be access when running on the lower supply I leakage (A) 0.13 μm V DD

57 Leakage Controlled SRAM Cell Alternatives Cell Leakage Bit line leakage 1 0 Gate control Virtual GND Asymmetric SRAM Cell Gated-GND SRAM Cell!drowsy V DD (1V) V DD Low (.3V) drowsy Cell state preserved Hardware versus software control of mode Drowsy SRAM Cell

58 Leakage Controlled SRAM Savings and Costs C 25 Qcritical in fc for 1 -> 0 flips Leakage energy/cycle (pj*10^3) C T a-0 a-1 Drsy... Gtd GND 0 6T asram-0 asram-1 Gated GND Drowsy bits, 70 nm, 1 ns cycle

59 Leakage Controlled Cache Microarchitecture Global Set Set: drowsy Reset: active row decoder word line drivers word line!q Q Reset 0.3V (drowsy) 1V (active) power line SRAMs word line wordline gate to prevent accessing drowsy lines

60 Hardware Controlled Drowsy Cache Put cache lines into a low-power mode periodically independent of the access history Periodic global set counter (~4000 cycles has good E-D trade-off) asserts drowsy signal - don t need counters/predictor states for each line Leakage Dynamic Drowsy Leakage Dynamic Regular I$ Drowsy I$ Cache energy reduction standby energy by 71% to 76% total energy by 54% to 58% Run time increase 0.41%

61 Next Lecture Modern Microprocessors and Systems Case Studies The CELL Processor Architecture The IBM Blue Gene/L System Architecture