On Reducing Leakage Energy

Transcription

1 On Reducing Leakage Energy Mary Jane Irwin Computer Science and Engineering Pennsylvania State University October 2002

2 Acknowledgements The emc^2 team at Penn State University Professors: Vijay Narayanan, Mahmut Kandemir, Anand Sivasubramaniam Recent Ph.D. graduates: Rita Chen (Sun Microsystems), Wu Ye (AMCC), Yan Zhang (Arraycom, Inc.), David Duarte (Intel) Current Ph.D. students: Hyun-Suk Kim, Victor Delaluz, Ismail Kadayif, Soontae Kim, Guangyu Chen, Byung-Tae Kang, Lin Li, Jie Hu, Wei Zhang, Sudhanva Gurumurthi, Guilin Chen, Vijay Degalahal, Jooheng Lee, Greg Link, YuhFang Tsai The DARPA/MARCO GSRC team Jan Rabaey and Bora Nikolic, UC Berkeley Giovanni demicheli, Stanford David Blaauw, UMichigan Anantha Chandrakasan (MIT)

3 Leakage Power A Design Limiter? V DD and V T Drain Leakage Power 50% 8KW 40% 1.7KW 30% 400W 20% 12W 88W 10% 0% nd phones leaky! Power (Watts) Of Intel Parts Pentium P chips might become hot

4 CMOS Energy & Power Equations E = C L V DD 2 P t sc V DD I peak P V DD I leakage f 0 1 = P 0 1 * f clock P = C L V DD2 f t sc V DD I peak f V DD I leakage Dynamic power Short-circuit power Leakage power

5 Leakage (Static) Power Consumption V DD I leakage Vout Drain junction leakage Gate leakage Sub-threshold current All increase exponentially with temperature!

6 Leakage as a Function of V T Continued scaling of V DD and the subsequent scaling of V T will make sub-threshold conduction a dominate component of power dissipation ID (A) VGS (V) VT=0.4V VT=0.1V

7 Leakage as a Function of Temperature I leakage (na/µm) Temp(C) From De,1999

8 Power and Energy Design Space Energy Active Leakage Constant Throughput/Latency Design Time Logic Design Reduced V dd Sizing Multi-V dd + Multi-V T Non-active Modules Clock Gating Sleep Transistors Multi-V dd Variable V T Variable Throughput/Latency Run Time DFS, DVS (Dynamic Freq, Voltage Scaling) + Variable V T

9 Optimization: From Circuits to Software Power Modeling and Prediction Tools Systems Software Microarchitecture Circuits

10 Power and Energy Design Space Energy Active Leakage Constant Throughput/Latency Design Time Logic Design Reduced V DD Sizing Multi-V DD + Multi-V T Non-active Modules Clock Gating Sleep Transistors Multi-V DD Variable V T Variable Throughput/Latency Run Time DFS, DVS (Dynamic Freq, Voltage Scaling) + Variable V T

11 Dynamic Power as a Function of Device Size Device sizing affects dynamic energy consumption gain is largest for networks with large overall effective fanouts (F = C L /C g,1 ) The optimal gate sizing factor (f) for dynamic energy is smaller than the one for performance, especially for large F s e.g., for F=20, f opt (energy) = 3.53 while f opt (performance) = 4.47 If energy is a concern avoid oversizing beyond the optimal normalized energy F=1 F= f F=5 F=10 F=20 From Nikolic, UCB

12 Dynamic Power as a Function of V DD Decreasing the V DD decreases dynamic energy consumption (quadratically) But, increases gate delay (decreases performance) t p(normalized ) V DD (V) Determine the critical path(s) at design time and use high V DD for the transistors on those paths for speed. Use a lower V DD on the other logic to reduce dynamic energy consumption.

13 Leakage as a Function of V T Reducing the V T increases the subthreshold leakage current (exponentially) But, reducing V T decreases gate delay (increases performance) ID (A) VGS (V) VT=0.4V VT=0.1V Determine the critical path(s) at design time and use low V T devices on the transistors on those paths for speed. Use a high V T on the other logic for leakage control.

14 Dual Supplies, Sizing, Dual Thresholds Which of these optimizations should be done first? Apply sizing first, then 2 nd V T to dual-v DD design Exploratory evaluation on a general logic block (targeting active energy before leakage): Leakage power reduced almost 4x Active energy reduced by 50% From Nikolic, UCB

15 Power and Energy Design Space Energy Active Leakage Constant Throughput/Latency Design Time Logic Design Reduced V DD Sizing Multi-V DD + Multi-V T Non-active Modules Clock Gating Sleep Transistors Multi-V DD Variable V T Variable Throughput/Latency Run Time DFS, DVS (Dynamic Freq, Voltage Scaling) + Variable V T

16 Dynamic Frequency and Voltage Scaling Intel s SpeedStep Hardware that steps down the clock frequency (dynamic frequency scaling DFS) when the user unplugs from AC power PLL from 650MHz 500MHz CPU stalls during SpeedStep adjustment Transmeta LongRun Hardware that applies both DFS and DVS (dynamic supply voltage scaling) 32 levels of V DD from 1.1V to 1.6V PLL from 200MHz 700MHz in increments of 33MHz Triggered when CPU load change is detected by software heavier load ramp up V DD, when stable speed up clock lighter load slow down clock, when PLL locks onto new rate, ramp down V DD CPU stalls only during PLL relock (< 20 microsec)

17 V T (V) The Body-Effect on V T V T = V T0 + γ( -2φ F + V SB - -2φ F ) where V T0 is the threshold voltage at V SB = 0 V SB is the source-bulk (substrate) voltage γ is the body-effect coefficient For an n-channel device, the substrate is normally tied to ground A negative bias causes V T to increase from 0.45V to 0.85V Adjusting the substrate bias at run-time is called adaptive body-biasing (ABB) V SB (V)

18 Simultaneous DVS and Variable V T What is the optimal trade-off between V DD scaling and adaptive bodybiasing (variable V T ) to reduce total power (both static and dynamic) assuming variable processor throughput? Utilization V DD Optimal V DD and V SB for the xmms-mp3 Benchmark Freq V SB Time From Blaauw, UMich For a Crusoe processor with variable frequency (300 to 600MHz) using a custom performance-setting algorithm Voltage

19 Simultaneous DVS and Variable V T Gains 1.0E-08 Total Energy 1.0E E-10 Freq Scaling DVS Only DVS and ABB SPICE 74% improvement 54% improvement 1.0E E E+10 Frequency 1.0E+09 From Blaauw, UMich

20 Power and Energy Design Space Energy Active Leakage Constant Throughput/Latency Design Time Logic Design Reduced V DD Sizing Multi-V DD + Multi-V T Non-active Modules Clock Gating Sleep Transistors Multi-V DD Variable V T Variable Throughput/Latency Run Time DFS, DVS (Dynamic Freq, Voltage Scaling) + Variable V T

21 Leakage in Memories Leakage in memories is becoming a major issue For some applications, the entire memory can be put into a drowsy state (that retains the data while significantly reducing leakage current) when the system is idle by lowering the supply voltage stby V dd Low SRAM V dd E.g., lowering a 1V supply to 190mV reduces leakage power by 8x but incurs a wake-up time of 9ns For some applications, unused portions of the memory can be turned off (by setting the supply voltage to GND) Assumes a multi-banked memory microarchitecture

22 GC Controlled SRAM Bank Turn Off OFF 0 V dd 0 V dd 0 V dd 0 V dd SRAM Bank 1 SRAM Bank 2 SRAM Bank 3 SRAM Bank 4 T=0 OFF OFF OFF OFF Live Garbage T=50 A B C D E F G T=100 A B C D E F G Energy wasted T=200 A C D OFF G GC

23 Impact of GC Frequency Heap Energy Earlier detection of of banks containing only garbage base -More memory accesses -More CPU operations -Longer execution time Crypto Kvideo Kwml Scheduler More frequent GC

24 Leakage in Caches On-chip caches are responsible for 15%~20% of the total chip power Leakage power approaches 50% of the total cache power for 70nm technology (according to projections based on the 70nm BPTM) So cache leakage control is a must Normalized leakage power ºC 75 ºC 50 ºC 25 ºC Minimum gate length (µm) 0.05

25 Leakage Controlled SRAM Cells Cell Leakage Asymmetric SRAM cell Cell state preserved Leakage control inherent in circuit design Can be set to optimize the storing-0 state (a-0) or storing-1 state (a-1) Bit line leakage 1 0

26 Leakage Controlled SRAM Cells, con t Gated-GND SRAM cell Cell state preserved Leakage control dependent on state of Gate Control line Usually set by hardware counters, one per cache line Gate Control Virtual Ground

27 Leakage Controlled SRAM Cells, con t Drowsy SRAM cell Cell state preserved Leakage control dependent on state of drowsy line Can be set by the hardware or software!drowsy V dd (1V) V dd Low (.3V) drowsy

28 Leakage Controlled SRAM Cells Comparison C 75 C Leakage energy/cycle in pj*10^3 a-0 6T Gtd... a-1 0 Drs... For 256 bits, 70 nm, 1 ns cycle

29 eakage Controlled Cache Microarchitecture Set1 Set0 PSR: Power Status Register PSR!B1 B1!B0B0 row decoder word line drivers word line reset V dd Off (0V) V dd Low (0.3V) power line SRAMs word line V dd (1V) wordline gate to prevent accessing drowsy lines

30 Hardware Controlled Drowsy Cache Periodically put entire cache into a low-power state independent of the access history of the cache lines Need a hardware global counter (~4000 cycles has good E-D trade-off) to assert the drowsy signal Leakage Dynamic Drowsy Leakage Dynamic Cache energy reduction standby energy by 71% to 76% total energy by 54% to 58% Run time increase 0.41% (0.84%) for awake tag (drowsy tag) Regular D$ Drowsy D$ From Blaauw, UMich

31 Compiler Controlled Drowsy Cache Loop Body-I Loop Body-III In VLIW cores, the compiler can control instruction execution order Compiler can insert turnoff instructions at the loop granularity level conservative optimistic Loop Body-II statedestroying hardware Kill conservative compiler Strategy I optimistic compiler Strategy II statepreserving Drowsy Strategy III

32 Energy Savings Comparison Strategy I Strategy II Strategy III Hybrid Kill-2K Drowsy-2K Kill-4K Drowsy-4K vpenta Normalized Energy (w.r.t. Strategy I) 129.com... mpeg2dec rawdaudio

33 Relative Performance Strategy I has little chance to turn-off instructions early and incurs large overhead because it is state-destroying Strategy II can detect idleness quickly but incurs large overhead because it is state-destroying Strategy III gains from quick turn-off and because it is state-preserving Hybrid: Strategy II + Strategy III When exiting a loop, if it is not going to be accessed again (Loop Body-III), its cache lines are turned off If the loop will be visited again (Loop Body-I and Body-II), the cache lines are placed into leakage control mode using the state-preserving mechanism Fixed period schemes (e.g., Drowsy) work well for loops with long execution time (e.g., vpenta)

34 Impact of Compiler Optimizations Many compiler optimizations can modify the instruction execution order leading to a significantly different energy picture Thus, one should develop energy-aware compilation strategies that take advantage of the underlying cache microarchitecture Four frequently-used loop transformation strategies are: Loop fission (distribution) Loop fusion Loop tiling Loop unrolling

35 Example of Loop Distribution Loop Body-I Loop Body-II Loop Body-I Loop Body-II Header Loop Body- I Loop Body- II Header Loop Body- I Header Loop Body- II A code fragment with a loop A distributed version of the code fragment The I$ layout for the original code fragment The I$ layout for the distributed version

36 Impact of Compiler Optimizations Energy Strategy I Strategy II Strategy III Kill-2K Drowsy-2K Kill-4K Drowsy-4K original distributed tiled All values are normalized wrt to the case without power management.

37 Power and Energy Design Space Energy Active Leakage Constant Throughput/Latency Design Time Logic Design Reduced V DD Sizing Multi-V DD + Multi-V T Non-active Modules Clock Gating Sleep Transistors Multi-V DD Variable V T Variable Throughput/Latency Run Time DFS, DVS (Dynamic Freq, Voltage Scaling) + Variable V T

38 Multi-V DD Augmented VLIW Architecture I$ Predecoder Register File LD/ST Unit D$ Branch Unit E 1, P 1 IALU0 IALU1 MULT FPALU E 2, P 2 E 3, P 3 E 4, P 4 P 1 > P 2 > P 3 > P 4 E 1 > E 2 > E 3 > E 4

39 Exploiting Slack VLIW CPU functional units (FUs) often cannot be completely utilized due to lack of available instructions using the FU data dependence relations between instructions Initial instruction schedule IALU0 IALU1 MULT FPALU Dynamic energy management Data dependencies When slack exists, use the version of the FU that uses less energy Similar to DVS except may be able to absorb all or most of the performance hit

40 Reducing both Dynamic and Leakage Energy Enable sleep transistor E 1, C 1 IALU0 IALU1 MULT FPALU IALU0 IALU1 MULT FPALU Leakage E 2, C 2 IALU0 IALU1 MULT FPALU IALU0 IALU1 MULT FPALU More Leakage

41 Energy Savings from VLIW Exploiting Slack cordic idea paraffins rawcaudio ijpeg Energy Savings (%) Multi-Vdd Sleep trans Both 3 supply voltages and basic block schedule

42 Power Prediction and Optimization Tools Trimaran C program IMPACT ELCOR Technology Parameters Machine Description DineroIII Cache Simulator Energy Profiler Simulator ELCOR Core energy Memory energy Module access statistics

43 Tradeoffs in Slack Management (a) three supply voltages (b) two supply voltages Total Energy (pj) Total Energy (pj) k (k is the slack duration) k original dynamic leakage original dynamic leakage For r = 0.1 (the leakage reduction factor)

44 Reliability area speed/area speed speed/power speed/power/reliability power low power reliable ultra-low power 1970 s 1980 s 1990 s 2000 s

45 Soft Errors in Leakage Controlled SRAMs As feature size decreases, the charge stored at each node decreases (due to a lower node capacitance and lower V dd ) Q critical (the charge necessary to cause a bit flip) decreases leading to an increase in the soft error rate (SER) (circuit errors caused due to excess charge carriers induced by radiation) T Qcritical in fc for 1 -> 0 flips asram-0 asram-1 Gated GND Qcritical in fc for 0 -> 1 flips Drowsy T asram-0 asram-1 Drowsy... Q critical has an exponential effect on SER Gated GND Layout influences number of errors due to a strike

46 Conclusions Handling the leakage problem Requires an integrated approach spanning circuits to microarchitectures to software Energy optimizations can result in reliability problems Soft errors Substrate noise due to power modes Future focus must be on reliable power-efficient systems Visit for relevant documents