Low Cost Analog Multiplier AD633

Transcription

1 FATURS -quadrant multiplication Low cost, 8-lead SOIC and PDIP packages Complete no external components required Laser-trimmed accuracy and stability Total error within % of full scale Differential high impedance X and Y inputs High impedance unity-gain summing input Laser-trimmed 0 V scaling reference APPLICATIONS Multiplication, division, squaring Modulation/demodulation, phase detection Voltage-controlled amplifiers/attenuators/filters Low Cost Analog Multiplier AD FUNCTIONAL BLOCK DIAGRAM X X Y Y 0V Figure. A W Z GNRAL DSCRIPTION The AD is a functionally complete, four-quadrant, analog multiplier. It includes high impedance, differential X and Y inputs, and a high impedance summing input (Z). The low impedance output voltage is a nominal 0 V full scale provided by a buried Zener. The AD is the first product to offer these features in modestly priced 8-lead PDIP and SOIC packages. The AD is laser calibrated to a guaranteed total accuracy of % of full scale. Nonlinearity for the Y input is typically less than 0.% and noise referred to the output is typically less than 00 μv rms in a 0 Hz to 0 khz bandwidth. A MHz bandwidth, 0 V/μs slew rate, and the ability to drive capacitive loads make the AD useful in a wide variety of applications where simplicity and cost are key concerns. The versatility of the AD is not compromised by its simplicity. The Z input provides access to the output buffer amplifier, enabling the user to sum the outputs of two or more multipliers, increase the multiplier gain, convert the output voltage to a current, and configure a variety of applications. The AD is available in 8-lead PDIP and SOIC packages. It is specified to operate over the 0 C to 70 C commercial temperature range (J Grade) or the 0 C to +85 C industrial temperature range (A Grade). PRODUCT HIGHLIGHTS. The AD is a complete four-quadrant multiplier offered in low cost 8-lead SOIC and PDIP packages. The result is a product that is cost effective and easy to apply.. No external components or expensive user calibration are required to apply the AD.. Monolithic construction and laser calibration make the device stable and reliable.. High (0 MΩ) input resistances make signal source loading negligible. 5. Power supply voltages can range from ±8 V to ±8 V. The internal scaling voltage is generated by a stable Zener diode; multiplier accuracy is essentially supply insensitive. Rev. I Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 90, Norwood, MA 00-90, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 AD TABL OF CONTNTS Features... Applications... Functional Block Diagram... General Description... Product Highlights... Revision History... Specifications... Absolute Maximum Ratings... Thermal Resistance... SD Caution... Pin Configurations and Function Descriptions... 5 Typical Performance Characteristics... Functional Description... 7 rror Sources... 7 Applications Information...8 Multiplier Connections...8 Squaring and Frequency Doubling...8 Generating Inverse Functions...8 Variable Scale Factor...9 Current Output...9 Linear Amplitude Modulator...9 Voltage-Controlled, Low-Pass and High-Pass Filters...9 Voltage-Controlled Quadrature Oscillator... 0 Automatic Gain Control (AGC) Amplifiers... 0 Outline Dimensions... Ordering Guide... 5 RVISION HISTORY / Rev. H to Rev. I Changes to Figure... Changes to Figure... 5 Changes to Generating Inverse Functions Section... 8 Changes to Figure Added valuation Board Section and Figure to Figure 9, Renumbered Sequentially... Changes to Ordering Guide... 5 / Rev. G to Rev. H Changes to Figure, Deleted Figure... Added Figure, Figure, Table, Table Deleted Figure 9, Renumbered Subsequent Figures... Changes to Figure /0 Rev. F to Rev. G Changes to quation... Changes to quation 5 and Figure... 7 Changes to Figure /09 Rev. to Rev. F Changes to Format... Universal Changes to Figure... 9 Updated Outline Dimensions... Changes to Ordering Guide... 0/0 Rev. D to Rev. dits to Title of 8-Lead Plastic SOIC Package (RN-8)... dits to Ordering Guide... Change to Figure... 7 Updated Outline Dimensions... 8 Rev. I Page of

3 AD SPCIFICATIONS TA = 5 C, VS = ±5 V, RL kω. Table. ADJ, ADA Parameter Conditions Min Typ Max Unit TRANSFR FUNCTION ( X X)( Y Y) W = + Z 0 V MULTIPLIR PRFORMANC Total rror 0 V X, Y +0 V ± ± % full scale TMIN to TMAX ± % full scale Scale Voltage rror SF = 0.00 V nominal ±0.5% % full scale Supply Rejection VS = ± V to ± V ±0.0 % full scale Nonlinearity, X X = ±0 V, Y = +0 V ±0. ± % full scale Nonlinearity, Y Y = ±0 V, X = +0 V ±0. ±0. % full scale X Feedthrough Y nulled, X = ±0 V ±0. ± % full scale Y Feedthrough X nulled, Y = ±0 V ±0. ±0. % full scale Output Offset Voltage ±5 ±50 mv DYNAMICS Small Signal Bandwidth VO = 0. V rms MHz Slew Rate VO = 0 V p-p 0 V/µs Settling Time to % ΔVO = 0 V µs OUTPUT NOIS Spectral Density 0.8 µv/ Hz Wideband Noise f = 0 Hz to 5 MHz mv rms f = 0 Hz to 0 khz 90 µv rms OUTPUT Output Voltage Swing ± V Short Circuit Current RL = 0 Ω 0 0 ma INPUT AMPLIFIRS Signal Voltage Range Differential ±0 V Common mode ±0 V Offset Voltage (X, Y) ±5 ±0 mv CMRR (X, Y) VCM = ±0 V, f = 50 Hz 0 80 db Bias Current (X, Y, Z) µa Differential Resistance 0 MΩ POWR SUPPLY Supply Voltage Rated Performance ±5 V Operating Range ±8 ±8 V Supply Current Quiescent ma This specification was tested on all production units at electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed; however, only this specification was tested on all production units. Rev. I Page of

4 AD ABSOLUT MAXIMUM RATINGS Table. Parameter Rating Supply Voltage ±8 V Internal Power Dissipation 500 mw Input Voltages ±8 V Output Short-Circuit Duration Indefinite Storage Temperature Range 5 C to +50 C Operating Temperature Range ADJ 0 C to 70 C ADA 0 C to +85 C Lead Temperature (Soldering, 0 sec) 00 C SD Rating 000 V For supply voltages less than ±8 V, the absolute maximum input voltage is equal to the supply voltage. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. xposure to absolute maximum rating conditions for extended periods may affect device reliability. THRMAL RSISTANC θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table. Package Type θja Unit 8-Lead PDIP 90 C/W 8-Lead SOIC 55 C/W SD CAUTION Rev. I Page of

5 AD PIN CONFIGURATIONS AND FUNCTION DSCRIPTIONS X 8 +V S Y 8 X X Y 0V A 7 W Z Y V S 0V A 7 X +V S Y 5 V S Z 5 W ADJN/ADAN ADJR/ADAR (X X)(Y Y) W = + Z 0V (X X)(Y Y) W = + Z 0V Figure. 8-Lead PDIP Figure. 8-Lead SOIC Table. 8-Lead PDIP Pin Function Descriptions Pin No. Mnemonic Description X X Multiplicand Noninverting Input X X Multiplicand Inverting Input Y Y Multiplicand Noninverting Input Y Y Multiplicand Inverting Input 5 VS Negative Supply Rail Z Summing Input 7 W Product Output 8 +VS Positive Supply Rail Table 5. 8-Lead SOIC Pin Function Descriptions Pin No. Mnemonic Description Y Y Multiplicand Noninverting Input Y Y Multiplicand Inverting Input VS Negative Supply Rail Z Summing Input 5 W Product Output +VS Positive Supply Rail 7 X X Multiplicand Noninverting Input 8 X X Multiplicand Inverting Input Rev. I Page 5 of

6 AD TYPICAL PRFORMANC CHARACTRISTICS 0dB = 0.V rms, R L = kω 00 0 C L = 000pF 90 OUTPUT RSPONS (db) 0 0 C L = 0dB 0 0k 00k M 0M FRQUNCY (Hz) NORMAL CONNCTION CMRR (db) TYPICAL FOR X, Y INPUTS 0 00 k 0k 00k M FRQUNCY (Hz) Figure. Frequency Response Figure 7. CMRR vs. Frequency BIAS CURRNT (na) NOIS SPCTRAL DNSITY (µv/ Hz) TMPRATUR ( C) k 0k 00k FRQUNCY (Hz) Figure 5. Input Bias Current vs. Temperature (X, Y, or Z Inputs) Figure 8. Noise Spectral Density vs. Frequency k PAK POSITIV OR NGATIV SIGNAL (V) OUTPUT, R L kω 0 ALL INPUTS PAK POSITIV OR NGATIV SUPPLY (V) Figure. Input and Output Signal Ranges vs. Supply Voltages PAK-TO-PAK FDTHROUGH (mv) Y-FDTHROUGH 00 X-FDTHROUGH k 0k 00k M 0M FRQUNCY (Hz) Figure 9. AC Feedthrough vs. Frequency Rev. I Page of

7 FUNCTIONAL DSCRIPTION The AD is a low cost multiplier comprising a translinear core, a buried Zener reference, and a unity-gain connected output amplifier with an accessible summing node. Figure shows the functional block diagram. The differential X and Y inputs are converted to differential currents by voltage-tocurrent converters. The product of these currents is generated by the multiplying core. A buried Zener reference provides an overall scale factor of 0 V. The sum of (X Y)/0 + Z is then applied to the output amplifier. The amplifier summing node Z allows the user to add two or more multiplier outputs, convert the output voltage to a current, and configure various analog computational functions. Inspection of the block diagram shows the overall transfer function is ( X X)( Y Y) W = + Z 0 V () AD RROR SOURCS Multiplier errors consist primarily of input and output offsets, scale factor error, and nonlinearity in the multiplying core. The input and output offsets can be eliminated by using the optional trim of Figure 0. This scheme reduces the net error to scale factor errors (gain error) and an irreducible nonlinearity component in the multiplying core. The X and Y nonlinearities are typically 0.% and 0.% of full scale, respectively. Scale factor error is typically 0.5% of full scale. The high impedance Z input should always reference the ground point of the driven system, particularly if it is remote. Likewise, the differential X and Y inputs should reference their respective grounds to realize the full accuracy of the AD. 50kΩ +V S 00kΩ kω ±50mV TO APPROPRIAT INPUT TRMINAL (FOR XAMPL, X, Y, Z) V S Figure 0. Optional Offset Trim Configuration Rev. I Page 7 of

8 AD APPLICATIONS INFORMATION The AD is well suited for such applications as modulation and demodulation, automatic gain control, power measurement, voltage-controlled amplifiers, and frequency doublers. These applications show the pin connections for the ADJN (8-lead PDIP), which differs from the ADJR (8-lead SOIC). MULTIPLIR CONNCTIONS Figure shows the basic connections for multiplication. The X and Y inputs normally have their negative nodes grounded, but they are fully differential, and in many applications, the grounded inputs may be reversed (to facilitate interfacing with signals of a particular polarity while achieving some desired output polarity), or both may be driven. X INPUT Y INPUT + + X X W 7 ADJN Y Z Y +5V 0.µF (X X)(Y Y) W = 0V OPTIONAL SUMMING INPUT, Z 0.µF 5V Figure. Basic Multiplier Connections SQUARING AND FRQUNCY DOUBLING As is shown in Figure, squaring of an input signal,, is achieved simply by connecting the X and Y inputs in parallel to produce an output of /0 V. The input can have either polarity, but the output is positive. However, the output polarity can be reversed by interchanging the X or Y inputs. The Z input can be used to add a further signal to the output. X X W 7 ADJN Y Z Y +5V 5V 0.µF 0.µF Figure. Connections for Squaring W = 0V When the input is a sine wave sin ωt, this squarer behaves as a frequency doubler, because sin t cos t 0 V 0 V quation shows a dc term at the output that varies strongly with the amplitude of the input,. This can be avoided using the connections shown in Figure, where an RC network is used to generate two signals whose product has no dc term. It uses the identity cos θ sin θ sin θ () Z () R C X X W 7 ADJN Y Z Y +5V 0.µF 0.µF R kω 5V Figure. Bounceless Frequency Doubler R kω W = 0V At ωo = /CR, the X input leads the input signal by 5 (and is attenuated by ), and the Y input lags the X input by 5 (and is also attenuated by ). Because the X and Y inputs are 90 out of phase, the response of the circuit is (satisfying quation ) W sin 0t 5 sin 0t 5 0 V sin t 0 0 V () which has no dc component. Resistors R and R are included to restore the output amplitude to 0 V for an input amplitude of 0 V. The amplitude of the output is only a weak function of frequency; the output amplitude is 0.5% too low at ω = 0.9 ω0 and ω0 =. ω0. GNRATING INVRS FUNCTIONS Inverse functions of multiplication, such as division and square rooting, can be implemented by placing a multiplier in the feedback loop of an op amp. Figure shows how to implement square rooting with the transfer function for the condition < 0. The N8 diode is required to prevent latchup, which can occur in such applications if the input were to change polarity, even momentarily. W 0 V (5) < 0V 0kΩ +5V 7 AD7 0.µF 0.µF 0kΩ X 5V W = Figure. Connections for Square Rooting V 0.µF X W 7 ADJN N8 Y Z 5V Y 0.µF 0V) Rev. I Page 8 of

9 Likewise, Figure 5 shows how to implement a divider using a multiplier in a feedback loop. The transfer function for the divider is ( ) W = 0 V () R 0kΩ X +5V 0.µF 7 AD7 0.µF 5V X R 0kΩ X X W 7 ADJN Y Z Y Figure 5. Connections for Division +5V 0.µF 5V 0.µF W' = 0V X VARIABL SCAL FACTOR In some instances, it may be desirable to use a scaling voltage other than 0 V. The connections shown in Figure increase the gain of the system by the ratio (R + R)/R. This ratio is limited to 00 in practical applications. The summing input, S, can be used to add an additional signal to the output, or it can be grounded. X INPUT Y INPUT + + X X W 7 ADJN Y Z Y +5V 0.µF 0.µF 5V S (X X)(Y Y) W = R + R + S R 0V R kω R, R 00kΩ R Figure. Connections for Variable Scale Factor CURRNT OUTPUT The voltage output of the AD can be converted to a current output by the addition of a resistor, R, between the W and Z pins of the AD as shown in Figure 7. X INPUT Y INPUT + + X X W 7 ADJN Y Z Y +5V R 5V 0.µF 0.µF Figure 7. Current Output Connections I O = (X X)(Y Y) R 0V kω R 00kΩ AD This arrangement forms the basis of voltage-controlled integrators and oscillators as is shown later in this section. The transfer function of this circuit has the form ( X X)( Y Y) I O = (7) R 0 V LINAR AMPLITUD MODULATOR The AD can be used as a linear amplitude modulator with no external components. Figure 8 shows the circuit. The carrier and modulation inputs to the AD are multiplied to produce a double sideband signal. The carrier signal is fed forward to the Z input of the AD where it is summed with the double sideband signal to produce a double sideband with the carrier output. MODULATION INPUT ± M CARRIR INPUT C sin ωt + X X W 7 ADJN Y Z Y +5V 5V 0.µF 0.µF W = Figure 8. Linear Amplitude Modulator + M 0V C sin ωt VOLTAG-CONTROLLD, LOW-PASS AND HIGH- PASS FILTRS Figure 9 shows a single multiplier used to build a voltagecontrolled, low-pass filter. The voltage at Output A is a result of filtering, S. The break frequency is modulated by C, the control input. The break frequency, f, equals C f = (8) 0 V π ( ) RC and the roll-off is db per octave. This output, which is at a high impedance point, may need to be buffered. CONTROL INPUT C SIGNAL INPUT S X X W 7 ADJN Y Z Y +5V 5V 0.µF 0.µF db/octav OUTPUT A db f f 0 f OUTPUT B + T P OUTPUT B = + T P R OUTPUT A = + T P C T = = R W C 0 T = = W C R C Figure 9. Voltage-Controlled, Low-Pass Filter The voltage at Output B, the direct output of the AD, has the same response up to frequency f, the natural breakpoint of RC filter, and then levels off to a constant attenuation of f/f = C/0. f = (9) π RC Rev. I Page 9 of

10 AD For example, if R = 8 kω and C = 0.00 µf, then Output A has a pole at frequencies from 00 Hz to 0 khz for C ranging from 00 mv to 0 V. Output B has an additional 0 at 0 khz (and can be loaded because it is the low impedance output of the multiplier). The circuit can be changed to a high-pass filter Z interchanging the resistor and capacitor as shown in Figure 0. CONTROL INPUT C SIGNAL INPUT S X X W 7 ADJN Y Z Y +5V 5V 0.µF 0.µF db 0 f f f OUTPUT B +db/octav OUTPUT A C OUTPUT A R OUTPUT B Figure 0. Voltage-Controlled, High-Pass Filter VOLTAG-CONTROLLD QUADRATUR OSCILLATOR Figure shows two multipliers being used to form integrators with controllable time constants in second-order differential equation feedback loop. R and R5 provide controlled current output operation. The currents are integrated in capacitors C and C, and the resulting voltages at high impedance are applied to the X inputs of the next AD. The frequency control input, C, connected to the Y inputs, varies the integrator gains with a calibration of 00 Hz/V. The accuracy is limited by the Y input offsets. The practical tuning range of this circuit is 00:. C (proportional to C and C), R, and R provide regenerative feedback to start and maintain oscillation. The diode bridge, D through D (N9s), and Zener diode D5 provide economical temperature stabilization and amplitude stabilization at ±8.5 V by degenerative damping. The output from the second integrator (0 V sin ωt) has the lowest distortion. AUTOMATIC GAIN CONTROL (AGC) AMPLIFIRS Figure shows an AGC circuit that uses an rms-to-dc converter to measure the amplitude of the output waveform. The AD and A, ½ of an AD7 dual op amp, form a voltage-controlled amplifier. The rms-to-dc converter, an AD7, measures the rms value of the output signal. Its output drives A, an integrator/comparator whose output controls the gain of the voltage-controlled amplifier. The N8 diode prevents the output of A from going negative. R8, a 50 kω variable resistor, sets the output level of the circuit. Feedback around the loop forces the voltages at the inverting and noninverting inputs of A to be equal, thus the AGC. D5 N5 D N9 D N9 D N9 D N9 +5V (0V) cos ωt R kω C X X W 7 ADJN Y Z Y 5V 0.µF 0.µF R kω C 0.0µF X X W 7 ADJN Y Z Y +5V 5V 0.µF 0.µF C 0.0µF R kω R 0kΩ (0V) sin ωt R5 kω C 0.0µF f = C 0V = khz Figure. Voltage-Controlled Quadrature Oscillator Rev. I Page 0 of

11 AD R kω R 0kΩ R 0kΩ AGC THRSHOLD ADJUSTMNT +5V +5V 0.µF X X W 7 ADJN Y Z 0.µF 8 / AD7 A C µf R5 0kΩ R kω OUT Y 0.µF C C COMMON 8 +5V 0.µF C 0.µF C 0.0µF R0 0kΩ 5V 0.µF 5V V IN +V S AD7 C F OUTPUT V S 7 C AV 5 R9 0kΩ N8 7 A 0.µF / AD7 5 +5V C µf R8 50kΩ OUTPUT LVL ADJUST 5V Figure. Connections for Use in Automatic Gain Control Circuit Rev. I Page of

12 AD VALUATION BOARD The evaluation board of the AD enables simple bench-top experimenting to be performed with easy control of the AD. Built-in flexibility allows convenient configuration to accommodate most operating configurations. Figure is a photograph of the AD evaluation board. Figure. Component Side Copper Figure. AD valuation Board Any dual-polarity power supply capable of providing 0 ma or greater is all that is required, in addition to whatever test equipment the user wishes to perform the intended tests. Referring to the schematic in Figure 0, inputs to the multiplier are differential and dc-coupled. Three-position slide switches enhance flexibility by enabling the multiplier inputs to be connected to an active signal source, to ground, or to a test loop connected directly to the device pin for direct measurements, such as bias current. Inputs may be connected single ended or differentially, but must have a dc path to ground for bias current. If an input source s impedance is non-zero, an equal value impedance must be connected to the opposite polarity input to avoid introducing additional offset voltage. The AD-VALZ can be configured for multiplier or divider operation by switch S. Refer to Figure 5 for divider circuit connections. Figure through Figure 7 are the signal, power, and groundplane artworks, and Figure 8 shows the component and circuit side silkscreen. Figure 9 shows the assembly Figure 5. Circuit Side Copper Figure. Inner Layer Ground Plane Rev. I Page of

13 + AD Figure 7. Inner Layer Power Plane Figure 9. AD-VALZ Assembly Figure 8. Component Side Silk Screen +V GND V G G G G G5 G C5 0µF 5V + C 0µF 5V +V V Y_IN TST Y_IN Z_IN NUMRATOR IN GND IN GND V S TST IN GND TST C 0.µF SL_Y SL_Y SL_Z D M Y_TP Z_TP NOM_TP FUNCT() NOTS. Z TO HAV DUAL FOOTPRINT FOR SOLDR MOUNT OR THRUHOL SOCKT. Y_TP Y Y Z X X 8 7 ADARZ V S +V S Z W 5 X_TP FUNCT() SL_X X_TP SL_X +V C 0.µF R D 0kΩ M X_IN IN GND TST X_IN (DNOM) IN GND TST R 0kΩ Figure 0. Schematic of the AD valuation Board 7 R 00Ω C 0.µF C 0.µF D M MULTIPLICATION: [(X-X)(Y-Y)/0V] + Z DIVISION: 0V (NUM/DNOM) FUNCT() OUT OUT_TP Rev. I Page of

14 AD OUTLIN DIMNSIONS 0.00 (0.) 0.5 (9.7) 0.55 (9.0) 0.0 (5.) MAX 0.50 (.8) 0.0 (.0) 0.5 (.9) 0.0 (0.5) 0.08 (0.) 0.0 (0.) (.5) BSC (7.) 0.50 (.5) 0.0 (.0) 0.05 (0.8) MIN SATING PLAN (0.) MIN 0.00 (.5) MAX 0.05 (0.8) GAUG PLAN 0.5 (8.) 0.0 (7.87) 0.00 (7.) 0.0 (0.9) MAX 0.95 (.95) 0.0 (.0) 0.5 (.9) 0.0 (0.) 0.00 (0.5) (0.0) (.78) 0.00 (.5) 0.05 (.) COMPLIANT TO JDC STANDARDS MS-00 CONTROLLING DIMNSIONS AR IN INCHS; MILLIMTR DIMNSIONS (IN PARNTHSS) AR ROUNDD-OFF INCH QUIVALNTS FOR RFRNC ONLY AND AR NOT APPROPRIAT FOR US IN DSIGN. CORNR LADS MAY B CONFIGURD AS WHOL OR HALF LADS. Figure. 8-Lead Plastic Dual-in-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) 0700-A 5.00 (0.98).80 (0.890).00 (0.57).80 (0.97) (0.) 5.80 (0.8) 0.5 (0.0098) 0.0 (0.000) COPLANARITY 0.0 SATING PLAN.7 (0.0500) BSC.75 (0.088).5 (0.05) 0.5 (0.00) 0. (0.0) (0.0098) 0.7 (0.007) 0.50 (0.09) 0.5 (0.0099).7 (0.0500) 0.0 (0.057) 5 COMPLIANT TO JDC STANDARDS MS-0-AA CONTROLLING DIMNSIONS AR IN MILLIMTRS; INCH DIMNSIONS (IN PARNTHSS) AR ROUNDD-OFF MILLIMTR QUIVALNTS FOR RFRNC ONLY AND AR NOT APPROPRIAT FOR US IN DSIGN. Figure. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 007-A Rev. I Page of

15 AD ORDRING GUID Model Temperature Range Package Description Package Option ADANZ 0 C to +85 C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8 ADARZ 0 C to +85 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADARZ-R7 0 C to +85 C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8 ADARZ-RL 0 C to +85 C 8-Lead Standard Small Outline Package [SOIC_N], " Tape and Reel R-8 ADJN 0 C to 70 C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8 ADJNZ 0 C to 70 C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8 ADJR 0 C to 70 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADJR-RL 0 C to 70 C 8-Lead Standard Small Outline Package [SOIC_N], " Tape and Reel R-8 ADJR-RL7 0 C to 70 C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8 ADJRZ 0 C to 70 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADJRZ-R7 0 C to 70 C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8 ADJRZ-RL 0 C to 70 C 8-Lead Standard Small Outline Package [SOIC_N], " Tape and Reel R-8 AD-VALZ valuation Board Z = RoHS Compliant Part. Rev. I Page 5 of

16 AD NOTS 0 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /(I) Rev. I Page of