A SCALABLE SYSTEM ARCHITECTURE FOR HIGH-THROUGHPUT TURBO-DECODERS. Michael J. Thul, Frank Gilbert, Timo Vogt,Gerd Kreiselmaier, Norbert Wehn

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1 A SCALAE SYSTEM ARCHITECTURE FOR HIGHTHROUGHPUT TURBODECODERS Michael J. Thul, Frank Gilber, Timo Vog,Gerd Kreiselmaier, Norber Wehn Microelecronic Sysem Design Research Group Universiy of Kaiserslauern, ErwinSchrödingerSraße Kaiserslauern, Germany hul, gilber, vog, kreiselmaier, ABSTRACT The need for higher daa raes is ever rising as wireless communicaion sandards move from he hird o he fourh generaion. TurboCodes are he prevalen channel codes for wireless sysems due o heir excellen forward error correcion capabiliy. So far research has mainly focused on componens of high hroughpu Turbos. To he bes of our knowledge, no complee Turbo sysem has been argeed. his paper we explore he Turbo design space anew, boh under sysem design and deepsubmicron implemenaion aspecs. Our approach incorporaes all levels of design, from I/O behavior down o floorplaning and deepsubmicron effecs in synhesis and inerconnec. Is scalabiliy allows o derive opimized archiecures ailored o he given hroughpu and arge echnology. We presen a design example for a 6MBi/s 3GPP complian Turbo synhezised on a.8µm sandard cell library.. INTRODUCTION TurboCodes, proposed in 993 [2], are among he mos advanced channel coding echniques, as hey show ousanding error correcion capabiliy. As applicaions for wireless sysems creae demand for more and more daa o be ransferred, high hroughpu connecions become a necessiy. Thus TurboCodes, already par of oday s 3GPP wireless communicaion sandard [8], will be used for higher hroughpus in he fuure. TurboEncoders are sraigh forward o implemen, whereas he design of a Turbos is a challenging and complex ask. For high hroughpu, highly parallelized decoder archiecures are needed. Turbos consis of componen decoders which exchange informaion ieraively. Beween ieraions, his informaion is reordered following an inerleaving scheme. Previous work has mainly focused on he parallelizaion of he componen decoders, namely he commonly used maximumaposeriori (MAP) [3]. The inerleaving, however, has only been sudied recenly for parallelizaion []. Up o now archiecural decisions for parallelizaion have mainly focused on merics for memory demand, arihmeic complexiy and hroughpu. The resuling high hroughpu decoderarchiecures are complex designs wih millions of gaes. Implemening hese archiecures in deepsubmicron echnologies will lead o iming closure, clock skew, and global inerconnec problems. Therefore high hroughpu Turbo sysems mus be designed wih special focus on inerconnec and using saeofhear synhesis mehodologies. his work we focus on parallelizaion and pariioning for minimized communicaion, synchronizaion, global inerconnec and conrol. To avoid iming closure problems, no pariion exceeds a size of K gaes [7]. The globally asynchronous, locally synchronous paradigm is applied [] where applicable. his paper, we consider he complee Turbo sysem wih I/O, componen decoders and inerleaving nework. 2. TURBOCODES Forward error correcion is enabled by inroducing pariy bis. TurboCodes, he original informaion ( x s ), denoed as sysemaic informaion, is ransmied ogeher wih he pariy informaion ( x p x 2p ). For he Third Generaion Parnership Projec (3GPP) [8], he encoder consiss of wo recursive sysemaic convoluional (RSC) encoders wih consrain lengh K 4, which can also be inerpreed as 8 sae finie sae machines. One RSC encoder works on he block of informaion in is original, he oher one in an inerleaved sequence, see Figure a). On he receiver side a corresponding componen decoder for each of hem exiss. The MAP has been recognized as he componen decoder of choice as i is superior o he SofOupu Vierbi Algorihm (SOVA) in erms of communicaions performance and implemenaion scalabiliy [].

2 RSC2 y s y s in y p y 2p in Λ Λ 2 z 2 in z INT RSC RSC2 a) x s x p x 2p Puncurer Puncurer x s x p x 2p y p MAP Λ DE INT z 2 in y 2p in INT y s y s in b) z MAP2 DE Λ 2 Fig.. TurboEncoder and Turbo The sofoupu of each componen decoder ( Λ) is modified o reflec only is own confidence ( z) in he received informaion bi of being sen eiher as or. These confidences are exchanged beween he decoders o bias heir nex esimaions ieraively (see Figure b)). During his exchange, he produced informaion is inerleaved following he same scheme as in he encoder. The exchange coninues unil a sop crierion, see [4], is fulfilled. The las sofoupu is no modified and becomes he sofoupu of he Turbo ( Λ 2 ). Is sign represens he decision and is magniude he confidence of he Turbo in i. 3. THE MAP ALGORITHM Given he received samples of sysemaic and pariy bis (channel values)for he whole block (y N, where N is he block lengh), he MAP algorihm compues he probabiliy for each bi o have been sen as d k or d k. The logarihmic likelihood raio (LLR) of hese probabiliies is he sofoupu, denoed as: Λ k log Pr d k y N Pr d k y N Equaion can be expressed using hree probabiliies, which refer o he encoder saes Sk m, where k N and m m 8 : The branch k k merics γm m d k is he probabiliy ha a ransiion beween Sk m and Sm k has aken place. I is derived from he received signals, he apriori informaion given by he previous decoder, he code srucure and he assumpion of d k or d k, for deails see [5]. From hese branch merics he probabiliy α k m ha he encoder reached sae Sm k given he iniial sae and he received sequence yk, is compued hrough a forward recursion: α k m α k m m k k γm m Performing a backward recursion yields he probabiliy β k m ha he encoder has reached he (known) final sae given () he sae Sm k and he remainder of he received sequence y N k : β k m β k k k m γm m m αs and βs are boh called sae merics. Equaion can be rewrien as: Λ k log m m αk m βm k k k γm m d k m m α k m βm k k k γm m d k The original probabiliy based formulaion as presened here involves a lo of muliplicaions and has hus been pored o he logarihmic domain o become he LogMAP Algorihm [5]: Muliplicaions urn ino addiions and addiions ino maximum selecions wih addiional correcion erms. Arihmeic complexiy can furher be reduced by omiing he correcion erm (MaxLogMAP Algorihm) which leads o a sligh loss in communicaions performance (abou. db). LogMAP and MaxLogMAP algorihm are common pracice in saeofhear implemenaions. Obviously, only one se of sae merics, eiher αs or βs has o be sored during he recursions, as he LLR can be compued in parallel o he second recursion. Figure 2, he recursions associaed wih his sorage are depiced wih slim lines. Thick lines indicae recursions wih combined LLR calculaion. Figure 2 a) shows he original sequence of compuaions also know as serial MAP (SMAP): Firs a forward recursion over he whole block of lengh wih sorage of he inermediae sae merics α, second he backward recursion, saring a he end of he block, where he produced βs are immediae consumed by he LLR calculaion. The huge sorage requiremens for saemerics, proporional o he area spanned by he recursions, and he high laency can be couneraced hrough windowing echniques. Windowing allows o loosen he dependency beween subblocks of size : I is sufficien o perform a recursion on a cerain number AL of proceeding bis (acquisiion) o obain sufficienly accurae values on window borders [3]. Also know as he Jacobian logarihm, see [5] for deails. (2)

3 PSfrag replacemens AL a) No Windowing b) Single Sided Acquisiion (SMAP) AL c) SMAP wih hree recursion unis d) Double Sided Acquisiion (PMAP) Fig. 2. Windowing Schemes for he MAP Algorihm e) PMAP, Acquisiion Minimized (Example) Figure 2 shows wo variaions on windowed SMAP: fully serial compuaion of he recursions and he acquisiion in b), and heir parallel compuaion in c). We assume implemenaions wih recursion unis which can handle eiher forward, backward or acquisiion phases. For Figure 2b) only one recursion uni is used sequenially, whereas hree unis work in parallel in Figure 2c). Saring acquisiion on several poins of he block allows o process independen subblocks, which leads o he parallel MAP (PMAP), Figure 2d), allowing o rade off hardware for laency. Various arrangemens of he processing order (and direcion) are possible. We choose he seup depiced in Figure 2e), comparable o he double flow in [6]. I minimizes he acquisiions, which ranslae o compuaional overhead, and i minimizes he need o exchange daa beween windows. The field of window processing seup has already been sufficienly explored, for insance in [2, 6]. 4. RELATED WORK A horough compilaion of MAP decoder opimizaions can be found in [2] and is references. To give some examples: MAP decoder processing scheme opimizaions are presened [6, 3], implemenaion issues of MAP decoders are discussed in [, 4]. High hroughpu MAP decoders have already been presened in [3, 3]. The second imporan building block, he inerleaver, has only been addressed recenly by [, 9] and wih a differen approach in [4]. I/O and inerface issues have, o he bes of our knowledge, no been considered a all ye. Though a lo of Turbo designs exis, each of hem is a singular soluion and he auhors are no aware of any work on scalable highhroughpu Turbo archiecures. 5. NEW APPROACH Efficiency of archiecures, modeled for example by Efficiency Throughpu Area Energy Task has long been he only meric for design space exploraion. erconnec, communicaion and feasibiliy of synhesis based approaches in deepsubmicron echnologies, however, are keys issues for implemenaion, which limi he design space significanly. Saeofhear synhesis ools can synhesize up o K gaes fla [7]. Thus complex designs mus be composed of blocks wih his size limiaion. Toplevelrouing complexiy, which leads o imeclosure problems [] has o be reduced by minimizing communicaion beween he building blocks. Our new approach is o design synhesizable mosly independen subblocks of less han K gaes wih minimized global communicaion. Global communicaion is replaced by local communicaion hrough appropriae subblock design. 6. PARALLELIZATION LAYERS We focus on he Turbo level (see Figure 3), in which we idenified hree disinc archiecural layers: he I/O inerface layer, he componen decoder layer and he inerleaver nework layer. They are presened in deail in he following secions. 6.. I/O erface Layer The oal ime for processing a block is I D O, wih I O and D he imes for inpus, oupu, and decod (3)

4 PSfrag replacemens Sysem Level Recursionuni Level Turbo Level Turbo DaaTransfer (I/O) MAP erleaver Nework MAP Level Windows Window Level Recursions ACS Unis Recursion Level Recursion Unis Fig. 3. Parallelizaion Layers of Turbo Sysems (Exrac) g replacemens 7 Ieraions SMAP ing. Assuming ha each phase can be sped up by a facor N x hrough appropriae parallelizaion, he processing ime can be denoed as I Ni cycle, O N o cycle, and 2 I C D N D cycle, wih I he number of ieraions, he block lengh, and C a consan overhead facor beween and.5. Thus he sysem hroughpu T S is T S Ni cycle 2 I C N D cycle N o cycle 2 I C f cycle (4) N i No N D The saring poin of opimizaions is a serial MAP wih N I N O N D, which is no parallelizaion, see Figure 4a). Decoding ime is he dominan facor, bu maximizing he parallelism of he decoder core alone (Figure 4b)), however, leads only o T 2 f cycle for N D. See Figure 5a), where ieraions and an overhead facor PSfrag of replacemens erface erface erface erface erface T inpu Ou Ou T IO Ou Ou Ou T IO Ou Ou Ou Ou T inpu Toupu Ou Ou d) PMAP wih PSfrag replacemens parallelized concurren IO Ou a) 7 Ieraions SMAP Ou Fig. 4. I/O vs. parallelizaion I:Sequenial pu Oupu Ou II: Sequenial pu/oupu Toupu b) PMAP c) PMAP wih concurren IO e) concurren PMAP / IO C 2 are assumed (Experimens on realisic scenarios yielded C 8). As soon as D I O Amdahl s Law applies and decreasing D does no significanly improve sysem hroughpu. I and O boh occur in he denominaor, hence he limiaion o 2 f cycle. Combining he inpu and oupu phases o perform concurren in and oupu comes a no exra cos: The inpu memories (channel values) are filled, while he oupu memories (LLR) are read. No conflics occur and Equaion 4 becomes: T ConcurrenIO 2 I C f cycle (5) N IO N D see also Figure 4c) and Figure 5a). The hroughpu, how Relaive Throughpu I II III III: Concurren pu/oupu/ Relaive Throughpu PMAP alone PMAP; concurren I/O N D : Parallelizaion 2 P D a) III: Concurren pu/oupu/ II: Sequenial pu/oupu I:Sequenial pu Oupu 2 P IO b) Fig. 5. Throughpu depending on parallelizaion levels and degrees 3 III II I

5 ever, sill sauraes quickly wih increasing N D, see Figure 5a). Two counermeasures are possible: parallelized I/O and performing I/O and decoding concurrenly. Parallelized I/O is ransferring N IO daa packes per cycle in parallel, see Figure 4d). For his, N IO imes more I/Opors and N IO imes broader busses are needed. The memories, however, are hardly effeced as only he aspec raio of RAMs changes. The hroughpu can no longer be depiced by a simple plo. Figure 5b) shows a wodimensional hroughpu funcion. Concurren decoding and I/O, see Figure 4e), leads o a demand for an addiional se of I/O RAMs. One se for I/O and he oher for decoding. As he I/O RAMs make up 8% of he oal area, we would pay a major area penaly. On he oher hand, assuming IO D, relaive hroughpu becomes a linear funcion of N D, see Figure 5b). Which parallelizaions is chosen is highly dependen on he applicaion Componen Layer High hroughpu MAPdecoders can be build by using muliple MAPdecoder unis or by parallelizing he MAPdecoder iself on various levels (see Figure 3). We refer o decoder parallelizaion as presened in [2, 3]. On he componen decoder level he daa block is separaed in se of subblocks, called windows, allowing muliple windows o be decoded in parallel (see Figure 2). On he window level a window requires a recursion for acquisiion and subsequenly a firs and a second recursion for producing forward and backward pah merics. These recursions are he eniies on ha level and may be carried ou in a pipeline fashion or folded ono he same hardware. The recursions hemselves may be processed by a pipeline of recursion unis, also called saemeric unis, on he recursion level or folded ono one uni. The las level of parallelizaion we wan o consider here is he recursionuni level. I deermines he number of saemerics which are updaed per cycle. Noe ha his and all lower levels of parallelizaion (as menioned in [2]) are commonly fully parallelized, which is calculaing all saes of an 8sae 3GPP TurboCode in parallel on dedicaed hardware per sae using parallel arihmeic unis erleaver Nework Layer erleaving is scrambling he processing order o break up neighborhoodrelaions. I is essenial for he performance of TurboCodes. erleaver and deinerleaver ables conain oneoone mappings of source addresses o desinaion addresses. (A 3GPP complian able, for example, conains up o 54 enries.) One LLR has o be read for every LLR produced. Is only one LLR produced per imesep (SMAP), inerleaving can be performed on he fly hrough indirec addressing. Type of Unis # of Area Area Area Unis [mm 2 ] [# of Raio gaes] [%] I/ODaa RAM K 6.4 erleaver RAM K 2.9 BranchMeric RAM.4 3K.3 SaeMeric RAM.248 2K 7.9 SaeMeric Uni.7 6K 2.3 LLRCalculaion Uni.36 K 4.3 erface/conrol.9 7K 2.9 Toal Area K Table. 3GPP complian SMAP a 33MHz, 3.8MBi/s a 6 TurboIeraions Parallel archiecures, however, produce more han one (N D ) LLRs per imesep.thus, muliple LLRs have o be read and wrien concurrenly. Pariioning he LLR memory ino N D disinc RAMs can ensure ha no read conflics occur. Wrie conflics can eiher be avoided hrough careful inerleaver design respecing he given Turbo archiecure, as in [4], or handled hrough he design of advanced LLR disribuion neworks. We chose he laer alernaive; i is he only one allowing o build sandard complian Turbo sysems. Due o space limiaions, we refer o our previous publicaions: [] we inroduced a concurren inerleaving archiecure o solve he wrie conflics. [9] we opimized his archiecure following he same approach as in his paper: small local eniies wih minimum inerconnec and communicaion. The resul is a ringinerleaverboleneckbreaker (RIBB) archiecure where nodes, each associaed wih a producer of one LLR/cycle, are conneced in a ring srucure wih buffers beween hem. These nodes deermine locally where he incoming LLRs have o go o: lead hem o he local RAM, or forward hem o he nex node. See [9] for deails. 7. SCALAE ARCHITECTURE Implemenaion of scalable archiecures requires he selecion of appropriae levels of parallelizaion from a large design space. For his, we analyze a SMAP based Turbo implemenaion according o Figure 2b), windowed serial MAP wih one recursion uni, o idenify opimizaion poenial. From he synhesis resuls presened in Table wo conclusions can be drawn immediaely: Firs, more han 8% of he area in Table is dedicaed o inpu and oupu RAMs. Thus parallelizaion of he decoder iself only affecs 2% of he oal area and mus be more efficien (according o Equaion 3) han duplicaion of complee Turbos. Second, using muliple, dedi

6 IF SMAP uni IBB IF PSfrag replacemens Fig. 6. Sample Floorplan for eigh SubBlocks caed saemeric unis for acquisiion, forward and backward recursion increases he oal area only slighly. Ye i improves hroughpu by a facor of a leas wo, compare Figure 2b) and c) and see also []. Using dedicaed unis for each ask also increases he maximum clock frequency as muliplexers for hardware sharing are removed from he criical pah. To increase he MAPdecoder hroughpu furher, here are wo alernaives: unroll and pipeline he recursions (parallelizaion on he window level) or decode muliple windows in parallel (parallelizaion on he componen decoder level). On his level no only archiecural efficiency, bu also he maximum module size of K gaes for synhesis mus be aken ino accoun. Unrolling and pipelining he recursions, as in [3, 2, 3], resuls in a large number of recursion unis. Even wih maximum hardware folding, hese archiecures are oo large o be implemened in a K gaes module and can no be used in a sraigh forward synhesis based approach. We herefore parallelize on he componen decoder level. A double windowing scheme is employed: The inpu daa is pariioned ino subblocks according o he opimized PMAP scheme in Figure 2e), where one window ranslaes o one subblock. Each subblock is associaed wih one componen decoder. This minimizes communicaion and synchronizaion of adjacen componen decoders for acquisiion and saemeric exchange. The subblocks are sill large and he SMAP scheme of Figure 2c) is employed by each decoder o process is own subblock. Thus we process muliple subblocks in parallel each wih a dedicaed SMAPuni. This allows us even o inegrae one SMAPuni and he associaed inerleavingnode (RIBB) wihin he same K gaes module. Figure 6 shows he overall archiecure of an 8SMAP implemenaion. The ineviable highhroughpu communicaion for inerleaving is reduced o poinopoin communicaion of RIBBcells, as in [9]. This archiecure allows a regular floorplan where communicaion among he SMAPunis is limied o adjacen cells. Wirelengh, herefore, is independen of he number of cells. Global communicaion is limied o he laencyinsensiive disribuion of inpu and oupu daa. 8. RESULTS We developed a synheziable VHDL model wih fully parameerizable quanizaion, normalizaion, MaxLogMAP or LogMAP selecion, window lengh, acquisiion lengh, maximum block lengh, and number of SMAP unis in he componen decoder. Moreover, differen inerleaver neworks can be plugged in easily. Currenly, he ringconneced inerleaving nework is used; more advanced opologies are under developmen. The model implemens a 3GPP sandard [8] complian Turbo, ye wih scalable hroughpu. Communicaions performance has been evaluaed using a 3GPP complian downlink simulaion chain (saic cases, mulipahs cases, ec.). The model has been synhesized on a.8µm sandard cell library using Synopsys Design Compiler. Table 2 presens he synhesis resuls for various archiecure derivaes. Timing and area are exraced using he worscase library, while energy consumpion is derived wih he bescase library. For our design example of 6 MBi/s, we assume ha he precision of he LogMAP algorihm and 6 Turbo ieraions are needed. A maximum clock frequency of 66MHz is feasible, abou 2MHz if MaxLogMAP would be sufficien. Even wih concurren I/O and decoding, he argeed hroughpu can no be achieved wih N D 4 as he decoding ime D is sill oo long. For N D 8, no furher speedup is needed. N D 6, however, is he mos ineresing one, as 6MBi/s can be achieved in principle using eiher I/O parallelizaion or concurren I/O and decoding. Table 2 shows ha, from he feasible soluions, a Turbo wih N D 6 SMAP unis and an I/O parallelizaion of N IO 2 is he mos efficien. Noe, however, ha no lowpower echniques, like clockgaing or volage scaling, are considered in hese exploraions ye.

7 Parallel SMAP Unis N D Parallel I/O N IO 2 con. I/O 2 Area per SMAPUni[mm 2 ] I/ORAM local RAM Logic Area per RIBBCell[mm 2 ] erleaverram local Buffer NA Logic NA erface/crl.[mm 2 ] Toal Area [mm 2 ] Energy per Block [mj] Throughpu [MBi/s] Efficiency (norm.) Table 2. Implemenaion Resuls, 66MHz Clock Frequency and 6 TurboIeraions 9. CONCLUSION We combine, o he bes of our knowledge for he firs ime, he design space exploraion of high hroughpu Turbos wih saeofhear synhesis mehodologies. The appropriae levels of parallelism are idenified, allowing o derive, for a given hroughpu, he mos efficien archiecure implemenable using curren design ools and echnologies. Our synhesis resuls for 3GPP sandard complian highhroughpu Turbos demonsrae our approach. Fuure work will focus on furher improving he inerleaving nework and on closer inegraion of deepsubmicron place and roue aspecs.. REFERENCES [] L. Benini and G. D. Micheli. Neworks on Chips: A New SoC Paradigm. IEEE Compuer, 35():7 78, Jan. 22. [2] C. Berrou, A. Glavieux, and P. Thiimajshima. Near Shannon Limi ErrorCorrecing Coding and Decoding: Turbo Codes. Proc. 993 ernaional Conference on Communicaions (ICC 93), pages 64 7, Geneva, Swizerland, May 993. [3] H. Dawid, G. Gehnen, and H. Meyr. MAP Channel Decoding: Algorihm and VLSI Archiecure. VLSI Signal Processing VI, pages IEEE, 993. [4] A. Giuliei, L. van der Perre, and M. Srum. Parallel urbo decoding inerleavers: avoiding collisions in accesses o sorage elemens. Elecronics Leers, 38(5): , Feb. 22. [5] P. Roberson, P. Hoeher, and E. Villebrun. Opimal and SubOpimal Maximum a Poseriori Algorihms Suiable for Turbo Decoding. European Transacions on Telecommunicaions (ETT), 8(2):9 25, March April 997. [6] C. Schurgers, M. Engels, and F. Cahoor. Energy Efficien Daa Transfer and Sorage Organizaion for a MAP Turbo Module. Proc. 999 ernaional Symposium on Low Power Elecronics and Design (ISLPED 99), pages 76 8, San Diego, California, USA, Aug [7] D. Sylveser and K. Keuzer. Rehinking DeepSubmicron Circui Design. IEEE Compuer, 32():25 33, 999. [8] Third Generaion Parnership Projec. 3GPP home page. [9] M. J. Thul, F. Gilber, and N. Wehn. Opimized Concurren erleaving for HighSpeed TurboDecoding. Proc. 9h IEEE ernaional Conference on Elecronics, Circuis and Sysems ICECS 22, Dubrovnik, Croaia, 22. o appear. [] M. J. Thul, N. Wehn, and L. P. Rao. Enabling HighSpeed TurboDecoding Through Concurren erleaving. Proc. 22 IEEE ernaional Symposium on Circuis and Sysems (ISCAS 2), Phoenix, Arizona, USA, May 22. [] J. Vog, K. Koora, A. Finger, and G. Feweis. Comparison of Differen Turbo Realizaions for IMT2. Proc. 999 Global Telecommunicaions Conference (Globecom 99), volume 5, pages , Rio de Janeiro, Brazil, Dec [2] A. Worm. Implemenaion Issues of Turbos. PhD hesis, siue of Microelecronic Sysems, Deparmen of Elecrical Engineering and formaion Technology, Universiy of Kaiserslauern, 2. ISBN [3] A. Worm, H. Lamm, and N. Wehn. Design of LowPower HighSpeed Maximum a Poseriori Archiecures. Proc. Design, Auomaion and Tes in Europe (DATE ), pages , Munich, Germany, Mar. 2. [4] A. Worm, H. Michel, F. Gilber, G. Kreiselmaier, M. J. Thul, and N. Wehn. Advanced Implemenaion Issues of Turbo s. Proc. 2nd ernaional Symposium on Turbo Codes & Relaed Topics, pages , Bres, France, Sep. 2.