Triple-Channel Digital Isolators ADuM1300/ADuM1301

Transcription

1 FEATURES Low power operation 5 V operation. ma per channel Mbps to Mbps 3.5 ma per channel Mbps 3 ma per channel 9 Mbps 3 V operation.8 ma per channel Mbps to Mbps. ma per channel Mbps ma per channel 9 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 5 C High data rate: dc to 9 Mbps (NRZ) Precise timing characteristics ns max pulse width distortion ns max channel-to-channel matching High common-mode transient immunity: >5 kv/μs Output enable function 6-lead SOIC wide body package, Pb-free models available Safety and regulatory approvals UL recognition: 5 V rms for minute per UL 577 CSA component acceptance notice #5A VDE certificate of conformity DIN EN (VDE 884 Part ): 3- DIN EN 695 (VDE 85): -; EN 695: VIORM = 56 V peak TÜV approval: IEC/EN/UL/CSA 6- APPLICATIONS General-purpose multichannel isolation SPI interface/data converter isolation RS-3/RS-4/RS-485 transceiver Industrial field bus isolation Triple-Channel Digital Isolators ADuM3/ADuM3 GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS The ADuM3x are 3-channel digital isolators based on Analog Devices icoupler technology. Combining high speed CMOS and monolithic transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices. By avoiding the use of LEDs and photodiodes, icoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple icoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these icoupler products. Furthermore, icoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The ADuM3x isolators provide three independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). Both models operate with the supply voltage on either side ranging from.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM3x provides low pulse width distortion (< ns for CRW grade) and tight channel-to-channel matching (< ns for CRW grade). Unlike other optocoupler alternatives, the ADuM3x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. Protected by U.S. Patents 5,95,849 and 6,873,65. Other patents pending. V DD 6 V DD V DD 6 V DD GND 5 GND GND 5 GND V IA 3 ENCODE DECODE 4 V OA V IA 3 ENCODE DECODE 4 V OA V IB 4 ENCODE DECODE 3 V OB V IB 4 ENCODE DECODE 3 V OB V IC 5 ENCODE DECODE V OC V OC 5 DECODE ENCODE V IC NC 6 NC NC 6 NC NC 7 V E V E 7 V E OR V GND 8 GND Figure. ADuM3 Functional Block Diagram Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners GND 8 9 GND Figure. ADuM3 Functional Block Diagram One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved

2 TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagrams... Revision History... Specifications... 3 Electrical Characteristics 5 V Operation... 3 Electrical Characteristics 3 V Operation... 5 Electrical Characteristics Mixed 5 V/3 V or 3 V/5 V Operation... 7 Package Characteristics... Regulatory Information... Insulation and Safety-Related Specifications... Recommended Operating Conditions... Absolute Maximum Ratings... ESD Caution... Pin Configurations and Function Descriptions... 3 Typical Performance Characteristics... 4 Application Information... 6 PC Board Layout... 6 Propagation Delay-Related Parameters... 6 DC Correctness and Magnetic Field Immunity... 6 Power Consumption... 7 Outline Dimensions... 8 Ordering Guide... 8 DIN EN (VDE 884 Part ) Insulation Characteristics... REVISION HISTORY /6 Rev. D to Rev. E Updated Format...Universal Added TÜV Approval...Universal Changes to Figure... 5/5 Rev. C to Rev. D Changes to Format...Universal Changes to Figure... Changes to Table 6... Changes to Ordering Guide /4 Rev. B to Rev. C Changes to Format...Universal Changes to Features... Changes to Electrical Characteristics 5 V Operation... 3 Changes to Electrical Characteristics 3 V Operation... 5 Changes to Electrical Characteristics Mixed 5 V/3 V or 3 V/5 V Operation...7 Changes to Ordering Guide /4 Rev. A to Rev. B Changes to the Format...Universal Changes to the Features... Changes to Table 7 and Table Changes to Table Changes to the DC Correctness and Magnetic Field Immunity Section... 9 Changes to the Power Consumption Section... Changes to the Ordering Guide... 9/3 Rev. to Rev. A Edits to Regulatory Information... 3 Edits to Absolute Maximum Ratings... 5 Deleted the Package Branding Information... 6 Rev. E Page of

3 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 5 V OPERATION ADuM3/ADuM3 4.5 V VDD 5.5 V, 4.5 V VDD 5.5 V; all min/max specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 5 C, VDD = VDD = 5 V. Table. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent IDDI (Q).5.53 ma Output Supply Current per Channel, Quiescent IDDO (Q).9. ma ADuM3, Total Supply Current Three Channels DC to Mbps VDD Supply Current IDD (Q).6.5 ma DC to MHz logic signal freq. VDD Supply Current IDD (Q).7. ma DC to MHz logic signal freq. Mbps (BRW and CRW Grades Only) VDD Supply Current IDD () ma 5 MHz logic signal freq. VDD Supply Current IDD ().9.5 ma 5 MHz logic signal freq. 9 Mbps (CRW Grade Only) VDD Supply Current IDD (9) ma 45 MHz logic signal freq. VDD Supply Current IDD (9) 6 8 ma 45 MHz logic signal freq. ADuM3, Total Supply Current, Three Channels DC to Mbps VDD Supply Current IDD (Q).3. ma DC to MHz logic signal freq. VDD Supply Current IDD (Q)..4 ma DC to MHz logic signal freq. Mbps (BRW and CRW Grades Only) VDD Supply Current IDD () ma 5 MHz logic signal freq. VDD Supply Current IDD () ma 5 MHz logic signal freq. 9 Mbps (CRW Grade Only) VDD Supply Current IDD (9) ma 45 MHz logic signal freq. VDD Supply Current IDD (9) 9 37 ma 45 MHz logic signal freq. For All Models Input Currents IIA, IIB, IIC, IE, IE +. + μa VIA, VIB, VIC VDD or VDD, VE, VE VDD or VDD Logic High Input Threshold VIH, VEH. V Logic Low Input Threshold VIL, VEL.8 V Logic High Output Voltages VOAH, VOBH, VOCH VDD, VDD. 5. V IOx = μa, VIx = VIxH VDD, VDD V IOx = 4 ma, VIx = VIxH Logic Low Output Voltages VOAL, VOBL, VOCL.. V IOx = μa, VIx = VIxL.4. V IOx = 4 μa, VIx = VIxL..4 V IOx = 4 ma, VIx = VIxL SWITCHING SPECIFICATIONS ADuM3xARW Minimum Pulse Width 3 PW ns CL = 5 pf, CMOS signal levels Maximum Data Rate 4 Mbps CL = 5 pf, CMOS signal levels Propagation Delay 5 tphl, tplh 5 65 ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl 5 PWD 4 ns CL = 5 pf, CMOS signal levels Propagation Delay Skew 6 tpsk 5 ns CL = 5 pf, CMOS signal levels Channel-to-Channel Matching 7 tpskcd/od 5 ns CL = 5 pf, CMOS signal levels Rev. E Page 3 of

4 Parameter Symbol Min Typ Max Unit Test Conditions ADuM3xBRW Minimum Pulse Width 3 PW ns CL = 5 pf, CMOS signal levels Maximum Data Rate 4 Mbps CL = 5 pf, CMOS signal levels Propagation Delay 5 tphl, tplh 3 5 ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl 5 PWD 3 ns CL = 5 pf, CMOS signal levels Change vs. Temperature 5 ps/ C CL = 5 pf, CMOS signal levels Propagation Delay Skew 6 tpsk 5 ns CL = 5 pf, CMOS signal levels tpskcd 3 ns CL = 5 pf, CMOS signal levels Codirectional Channels 7 tpskod 6 ns CL = 5 pf, CMOS signal levels Opposing-Directional Channels 7 ADuM3xCRW Minimum Pulse Width 3 PW 8.3. ns CL = 5 pf, CMOS signal levels Maximum Data Rate 4 9 Mbps CL = 5 pf, CMOS signal levels Propagation Delay 5 tphl, tplh ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl 5 PWD.5 ns CL = 5 pf, CMOS signal levels Change vs. Temperature 3 ps/ C CL = 5 pf, CMOS signal levels Propagation Delay Skew 6 tpsk ns CL = 5 pf, CMOS signal levels tpskcd ns CL = 5 pf, CMOS signal levels Codirectional Channels 7 tpskod 5 ns CL = 5 pf, CMOS signal levels Opposing-Directional Channels 7 For All Models Output Disable Propagation Delay tphz, tplh 6 8 ns CL = 5 pf, CMOS signal levels (High/Low to High Impedance) Output Enable Propagation Delay tpzh, tpzl 6 8 ns CL = 5 pf, CMOS signal levels (High Impedance to High/Low) Output Rise/Fall Time (% to 9%) tr/tf.5 ns CL = 5 pf, CMOS signal levels Common-Mode Transient Immunity at Logic High Output 8 CMH 5 35 kv/μs VIx = VDD/VDD, VCM = V, transient magnitude = 8 V Common-Mode Transient Immunity at Logic Low Output 8 CML 5 35 kv/μs VIx = V, VCM = V, transient magnitude = 8 V Refresh Rate fr. Mbps Input Dynamic Supply Current per Channel 9 IDDI (D).9 ma/mbps Output Dynamic Supply Current per Channel 9 IDDO (D).5 ma/mbps All voltages are relative to their respective ground. The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure for total VDD and VDD supply currents as a function of data rate for ADuM3/ADuM3 channel configurations. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tphl propagation delay is measured from the 5% level of the falling edge of the VIx signal to the 5% level of the falling edge of the VOx signal. tplh propagation delay is measured from the 5% level of the rising edge of the VIx signal to the 5% level of the rising edge of the VOx signal. 6 tpsk is the magnitude of the worst-case difference in tphl or tplh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO >.8 VDD. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO <.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. E Page 4 of

5 ELECTRICAL CHARACTERISTICS 3 V OPERATION.7 V VDD 3.6 V,.7 V VDD 3.6 V; all min/max specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 5 C, VDD = VDD = 3. V. Table. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent IDDI (Q).6.3 ma Output Supply Current per Channel, Quiescent IDDO (Q)..4 ma ADuM3, Total Supply Current, Three Channels DC to Mbps VDD Supply Current IDD (Q).9.7 ma DC to MHz logic signal freq. VDD Supply Current IDD (Q).4.7 ma DC to MHz logic signal freq. Mbps (BRW and CRW Grades Only) VDD Supply Current IDD () ma 5 MHz logic signal freq. VDD Supply Current IDD ()..6 ma 5 MHz logic signal freq. 9 Mbps (CRW Grade Only) VDD Supply Current IDD (9) 3 48 ma 45 MHz logic signal freq. VDD Supply Current IDD (9) 8 3 ma 45 MHz logic signal freq. ADuM3, Total Supply Current, Three Channels DC to Mbps VDD Supply Current IDD (Q).7.4 ma DC to MHz logic signal freq. VDD Supply Current IDD (Q).6.9 ma DC to MHz logic signal freq. Mbps (BRW and CRW Grades Only) VDD Supply Current IDD () ma 5 MHz logic signal freq. VDD Supply Current IDD ().8.5 ma 5 MHz logic signal freq. 9 Mbps (CRW Grade Only) VDD Supply Current IDD (9) 4 36 ma 45 MHz logic signal freq. VDD Supply Current IDD (9) 6 3 ma 45 MHz logic signal freq. For All Models Input Currents IIA, IIB, IIC, IE, IE +. + μa VIA, VIB, VIC VDD or VDD, VE,VE VDD or VDD Logic High Input Threshold VIH, VEH.6 V Logic Low Input Threshold VIL, VEL.4 V Logic High Output Voltages VOAH, VOBH, VDD, VDD. 3. V IOx = μa, VIx = VIxH VOCH VDD, VDD.4.8 V IOx = 4 ma, VIx = VIxH Logic Low Output Voltages VOAL, VOBL, VOCL.. V IOx = μa, VIx = VIxL.4. V IOx = 4 μa, VIx = VIxL..4 V IOx = 4 ma, VIx = VIxL SWITCHING SPECIFICATIONS ADuM3xARW Minimum Pulse Width 3 PW ns CL = 5 pf, CMOS signal levels Maximum Data Rate 4 Mbps CL = 5 pf, CMOS signal levels Propagation Delay 5 tphl, tplh 5 75 ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl 5 PWD 4 ns CL = 5 pf, CMOS signal levels Propagation Delay Skew 6 tpsk 5 ns CL = 5 pf, CMOS signal levels Channel-to-Channel Matching 7 tpskcd/od 5 ns CL = 5 pf, CMOS signal levels Rev. E Page 5 of

6 Parameter Symbol Min Typ Max Unit Test Conditions ADuM3xBRW Minimum Pulse Width 3 PW ns CL = 5 pf, CMOS signal levels Maximum Data Rate 4 Mbps CL = 5 pf, CMOS signal levels Propagation Delay 5 tphl, tplh 38 5 ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl 5 PWD 3 ns CL = 5 pf, CMOS signal levels Change vs. Temperature 5 ps/ C CL = 5 pf, CMOS signal levels Propagation Delay Skew 6 tpsk 6 ns CL = 5 pf, CMOS signal levels tpskcd 3 ns CL = 5 pf, CMOS signal levels Codirectional Channels 7 tpskod 6 ns CL = 5 pf, CMOS signal levels Opposing-Directional Channels 7 ADuM3xCRW Minimum Pulse Width 3 PW 8.3. ns CL = 5 pf, CMOS signal levels Maximum Data Rate 4 9 Mbps CL = 5 pf, CMOS signal levels Propagation Delay 5 tphl, tplh ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl 5 PWD.5 ns CL = 5 pf, CMOS signal levels Change vs. Temperature 3 ps/ C CL = 5 pf, CMOS signal levels Propagation Delay Skew 6 tpsk 6 ns CL = 5 pf, CMOS signal levels tpskcd ns CL = 5 pf, CMOS signal levels Codirectional Channels 7 tpskod 5 ns CL = 5 pf, CMOS signal levels Opposing-Directional Channels 7 For All Models Output Disable Propagation Delay tphz, tplh 6 8 ns CL = 5 pf, CMOS signal levels (High/Low to High Impedance) Output Enable Propagation Delay tpzh, tpzl 6 8 ns CL = 5 pf, CMOS signal levels (High Impedance to High/Low) Output Rise/Fall Time (% to 9%) tr/tf 3 ns CL = 5 pf, CMOS signal levels Common-Mode Transient Immunity at Logic High Output 8 CMH 5 35 kv/μs VIx = VDD/VDD, VCM = V, transient magnitude = 8 V Common-Mode Transient Immunity at Logic Low Output 8 CML 5 35 kv/μs VIx = V, VCM = V, transient magnitude = 8 V Refresh Rate fr. Mbps Input Dynamic Supply Current, per Channel 9 IDDI (D). ma/mbps Output Dynamic Supply Current, per Channel 9 IDDO (D).3 ma/mbps All voltages are relative to their respective ground. The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure for total VDD and VDD supply currents as a function of data rate for ADuM3/ADuM3 channel configurations. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tphl propagation delay is measured from the 5% level of the falling edge of the VIx signal to the 5% level of the falling edge of the VOx signal. tplh propagation delay is measured from the 5% level of the rising edge of the VIx signal to the 5% level of the rising edge of the VOx signal. 6 tpsk is the magnitude of the worst-case difference in tphl or tplh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO >.8 VDD. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO <.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. E Page 6 of

7 ELECTRICAL CHARACTERISTICS MIXED 5 V/3 V OR 3 V/5 V OPERATION 5 V/3 V operation: 4.5 V VDD 5.5 V,.7 V VDD 3.6 V; 3 V/5 V operation:.7 V VDD 3.6 V, 4.5 V VDD 5.5 V; all min/max specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 5 C; VDD = 3. V, VDD = 5 V or VDD = 5 V, VDD = 3. V. Table 3. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent IDDI (Q) 5 V/3 V Operation.5.53 ma 3 V/5 V Operation.6.3 ma Output Supply Current per Channel, Quiescent IDDO (Q) 5 V/3 V Operation..4 ma 3 V/5 V Operation.9. ma ADuM3, Total Supply Current, Three Channels DC to Mbps VDD Supply Current IDD (Q) 5 V/3 V Operation.6.5 ma DC to MHz logic signal freq. 3 V/5 V Operation.9.7 ma DC to MHz logic signal freq. VDD Supply Current IDD(Q) 5 V/3 V Operation.4.7 ma DC to MHz logic signal freq. 3 V/5 V Operation.7. ma DC to MHz logic signal freq. Mbps (BRW and CRW Grades Only) VDD Supply Current IDD () 5 V/3 V Operation ma 5 MHz logic signal freq. 3 V/5 V Operation ma 5 MHz logic signal freq. VDD Supply Current IDD () 5 V/3 V Operation..6 ma 5 MHz logic signal freq. 3 V/5 V Operation.9.5 ma 5 MHz logic signal freq. 9 Mbps (CRW Grade Only) VDD Supply Current IDD (9) 5 V/3 V Operation ma 45 MHz logic signal freq. 3 V/5 V Operation 3 48 ma 45 MHz logic signal freq. VDD Supply Current IDD (9) 5 V/3 V Operation 8 3 ma 45 MHz logic signal freq. 3 V/5 V Operation 6 8 ma 45 MHz logic signal freq. ADuM3, Total Supply Current, Three Channels DC to Mbps VDD Supply Current IDD (Q) 5 V/3 V Operation.3. ma DC to MHz logic signal freq. 3 V/5 V Operation.7.4 ma DC to MHz logic signal freq. VDD Supply Current IDD (Q) 5 V/3 V Operation.6.9 ma DC to MHz logic signal freq. 3 V/5 V Operation..4 ma DC to MHz logic signal freq. Mbps (BRW and CRW Grades Only) VDD Supply Current IDD () 5 V/3 V Operation ma 5 MHz logic signal freq. 3 V/5 V Operation ma 5 MHz logic signal freq. VDD Supply Current IDD () 5 V/3 V Operation.8.5 ma 5 MHz logic signal freq. 3 V/5 V Operation ma 5 MHz logic signal freq. Rev. E Page 7 of

8 Parameter Symbol Min Typ Max Unit Test Conditions 9 Mbps (CRW Grade Only) VDD Supply Current IDD (9) 5 V/3 V Operation ma 45 MHz logic signal freq. 3 V/5 V Operation 4 36 ma 45 MHz logic signal freq. VDD Supply Current IDD (9) 5 V/3 V Operation 6 3 ma 45 MHz logic signal freq. 3 V/5 V Operation 9 37 ma 45 MHz logic signal freq. For All Models Input Currents IIA, IIB, IIC, IE, IE +. + μa VIA,VIB, VIC VDD or VDD, VE,VE VDD or VDD Logic High Input Threshold VIH, VEH 5 V/3 V Operation. V 3 V/5 V Operation.6 V Logic Low Input Threshold VIL, VEL 5 V/3 V Operation.8 V 3 V/5 V Operation.4 V Logic High Output Voltages VOAH, VOBH, VOCH VDD, VDD. VDD, VDD V IOx = μa, VIx = VIxH VDD, VDD, V IOx = 4 ma, VIx = VIxH VDD.4 VDD. Logic Low Output Voltages VOAL, VOBL, VOCL.. V IOx = μa, VIx = VIxL.4. V IOx = 4 μa, VIx = VIxL..4 V IOx = 4 ma, VIx = VIxL SWITCHING SPECIFICATIONS ADuM3xARW Minimum Pulse Width 3 PW ns CL = 5 pf, CMOS signal levels Maximum Data Rate 4 Mbps CL = 5 pf, CMOS signal levels Propagation Delay 5 tphl, tplh 5 7 ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl 5 PWD 4 ns CL = 5 pf, CMOS signal levels Propagation Delay Skew 6 tpsk 5 ns CL = 5 pf, CMOS signal levels Channel-to-Channel Matching 7 tpskcd/od 5 ns CL = 5 pf, CMOS signal levels ADuM3xBRW Minimum Pulse Width 3 PW ns CL = 5 pf, CMOS signal levels Maximum Data Rate 4 Mbps CL = 5 pf, CMOS signal levels Propagation Delay 5 tphl, tplh ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl 5 PWD 3 ns CL = 5 pf, CMOS signal levels Change vs. Temperature 5 ps/ C CL = 5 pf, CMOS signal levels Propagation Delay Skew 6 tpsk 6 ns CL = 5 pf, CMOS signal levels tpskcd 3 ns CL = 5 pf, CMOS signal levels Codirectional Channels 7 tpskod ns CL = 5 pf, CMOS signal levels Opposing-Directional Channels 7 ADuM3xCRW Minimum Pulse Width 3 PW 8.3. ns CL = 5 pf, CMOS signal levels Maximum Data Rate 4 9 Mbps CL = 5 pf, CMOS signal levels Propagation Delay 5 tphl, tplh 3 4 ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh-tphl 5 PWD.5 ns CL = 5 pf, CMOS signal levels Change vs. Temperature 3 ps/ C CL = 5 pf, CMOS signal levels Propagation Delay Skew 6 tpsk 4 ns CL = 5 pf, CMOS signal levels tpskcd ns CL = 5 pf, CMOS signal levels Codirectional Channels 7 Opposing-Directional Channels 7 tpskod 5 ns CL = 5 pf, CMOS signal levels Rev. E Page 8 of

9 Parameter Symbol Min Typ Max Unit Test Conditions For All Models Output Disable Propagation Delay tphz, tplh 6 8 ns CL = 5 pf, CMOS signal levels (High/Low to High Impedance) Output Enable Propagation Delay tpzh, tpzl 6 8 ns CL = 5 pf, CMOS signal levels (High Impedance to High/Low) Output Rise/Fall Time (% to 9%) tr/tf CL = 5 pf, CMOS signal levels 5 V/3 V Operation 3. ns 3 V/5 V Operation.5 ns Common-Mode Transient Immunity at Logic High Output 8 CMH 5 35 kv/μs VIx = VDD/VDD, VCM = V, transient magnitude = 8 V Common-Mode Transient Immunity at Logic Low Output 8 CML 5 35 kv/μs VIx = V, VCM = V, transient magnitude = 8 V Refresh Rate fr 5 V/3 V Operation. Mbps 3 V/5 V Operation. Mbps Input Dynamic Supply Current, per Channel 9 IDDI (D) 5 V/3 V Operation.9 ma/mbps 3 V/5 V Operation. ma/mbps Output Dynamic Supply Current, per Channel 9 IDDI (D) 5 V/3 V Operation.3 ma/mbps 3 V/5 V Operation.5 ma/mbps All voltages are relative to their respective ground. The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure for total VDD and VDD supply currents as a function of data rate for ADuM3/ADuM3 channel configurations. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tphl propagation delay is measured from the 5% level of the falling edge of the VIx signal to the 5% level of the falling edge of the VOx signal. tplh propagation delay is measured from the 5% level of the rising edge of the VIx signal to the 5% level of the rising edge of the VOx signal. 6 tpsk is the magnitude of the worst-case difference in tphl or tplh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO >.8 VDD. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO <.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on perchannel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. E Page 9 of

10 PACKAGE CHARACTERISTICS Table 4. Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input-to-Output) RI-O, Ω Capacitance (Input-to-Output) CI-O.7 pf f = MHz Input Capacitance CI 4. pf IC Junction-to-Case Thermal Resistance, Side θjci 33 C/W Thermocouple located IC Junction-to-Case Thermal Resistance, Side θjco 8 C/W at center of package underside Device considered a -terminal device; Pins,, 3, 4, 5, 6, 7, and 8 shorted together and Pins 9,,,, 3, 4, 5, and 6 shorted together. Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM3x have been approved by the organizations listed in Table 5. Table 5. UL CSA VDE TÜV Recognized under 577 component recognition program Double/reinforced insulation, 5 V rms isolation voltage Approved under CSA Component Acceptance Notice #5A Reinforced insulation per CSA and IEC 695-, 4 V rms maximum working voltage Certified according to DIN EN (VDE 884 Part ): 3- Basic insulation, 56 V peak Approved according to: IEC 6-: ( nd Edition), EN 6-: ( nd Edition) UL 6-:4 CSA C..6.:5 Reinforced insulation, 4 V rms maximum working voltage Complies with DIN EN (VDE 884 Part ): 3-, DIN EN 695 (VDE 85): -; EN 695: Reinforced insulation, 56 V peak File E4 File 578 File Certificate U8V In accordance with UL577, each ADuM3x is proof tested by applying an insulation test voltage 3 V rms for sec (current leakage detection limit = 5 μa). In accordance with DIN EN , each ADuM3x is proof tested by applying an insulation test voltage 5 V peak for sec (partial discharge detection limit = 5 pc). The * marking branded on the component designates DIN EN approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 5 V rms minute duration Minimum External Air Gap (Clearance) L(I) 7.7 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I) 8. min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance).7 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >75 V DIN IEC /VDE 33 Part Isolation Group IIIa Material Group (DIN VDE, /89, Table ) Rev. E Page of

11 DIN EN (VDE 884 PART ) INSULATION CHARACTERISTICS Table 7. Description Symbol Characteristic Unit Installation Classification per DIN VDE For Rated Mains Voltage 5 V rms I-IV For Rated Mains Voltage 3 V rms I-III For Rated Mains Voltage 4 V rms I-II Climatic Classification 4/5/ Pollution Degree (DIN VDE, Table ) Maximum Working Insulation Voltage VIORM 56 V peak Input-to-Output Test Voltage, Method b VPR 5 V peak VIORM.875 = VPR, % Production Test, tm = sec, Partial Discharge < 5 pc Input-to-Output Test Voltage, Method a VPR After Environmental Tests Subgroup 896 V peak VIORM.6 = VPR, tm = 6 sec, Partial Discharge < 5 pc After Input and/or Safety Test Subgroup /3 67 V peak VIORM. = VPR, tm = 6 sec, Partial Discharge < 5 pc Highest Allowable Overvoltage (Transient Overvoltage, ttr = sec) VTR 4 V peak Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure; also see Figure 3) Case Temperature TS 5 C Side Current IS 65 ma Side Current IS 335 ma Insulation Resistance at TS, VIO = 5 V RS > 9 Ω These isolators are suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The * marking on packages denotes DIN EN approval. 35 RECOMMENDED OPERATING CONDITIONS 3 SAFETY-LIMITING CURRENT (ma) SIDE # SIDE # Table 8. Parameter Symbol Min Max Unit Operating Temperature TA 4 +5 C Supply Voltages VDD, VDD V Input Signal Rise and Fall Times. ms All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields. 5 5 CASE TEMPERATURE ( C) Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN EN Rev. E Page of

12 ABSOLUTE MAXIMUM RATINGS Ambient temperature = 5 C, unless otherwise noted. Table 9. Parameter Symbol Min Max Unit Storage Temperature TST C Ambient Operating Temperature TA 4 +5 C Supply Voltages VDD, VDD V Input Voltage, VIA, VIB, VIC, VE, VE.5 VDDI +.5 V Output Voltage, VOA, VOB, VOC.5 VDDO +.5 V Average Output Current per Pin 3 Side IO 3 +3 ma Side IO 3 +3 ma Common-Mode Transients 4 + kv/μs All voltages are relative to their respective ground. VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See PC Board Layout section. 3 See Figure 3 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Ratings may cause latch-up or permanent damage. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Table. Truth Table (Positive Logic) VIX Input VEX Input VDDI State VDDO State VOX Output Notes H H or NC Powered Powered H L H or NC Powered Powered L X L Powered Powered Z X H or NC Unpowered Powered H Outputs return to the input state within μs of VDDI power restoration. X L Unpowered Powered Z X X Powered Unpowered Indeterminate Outputs return to the input state within μs of VDDO power restoration, if VEX state is H or NC. Outputs returns to high impedance state within 8 ns of VDDO power restoration, if VEX state is L. VIX and VOX refer to the input and output signals of a given channel (A, B, or C). VEX refers to the output enable signal on the same side as the VOX outputs. VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively. In noisy environments, connecting VEX to an external logic high or low is recommended. Rev. E Page of

13 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V DD *GND 6 V DD 5 GND * V IA 3 ADuM3 4 V OA V IB 4 TOP VIEW 3 V OB V IC 5 (Not to Scale) V OC NC 6 NC NC 7 V E *GND 8 9 GND * NC = NO CONNECT Figure 4. ADuM3 Pin Configuration V DD *GND V IA 3 ADuM3 6 V DD 5 GND * 4 V OA V IB 4 TOP VIEW 3 V OB V OC 5 (Not to Scale) V IC NC 6 NC V E 7 V E *GND 8 9 GND * NC = NO CONNECT Figure 5. ADuM3 Pin Configuration * Pins and 8 are internally connected, and connecting both to GND is recommended. Pins 9 and 5 are internally connected, and connecting both to GND is recommended. Output enable Pin on the ADuM3 can be left disconnected if outputs are to be always enabled. Output enable Pins 7 and on the ADuM3 can be left disconnected if outputs are to be always enabled. In noisy environments, connecting Pin 7 (for ADuM3) and Pin (for both models) to an external logic high or low is recommended. Table. ADuM3 Pin Function Descriptions Pin No. Mnemonic Function VDD Supply Voltage for Isolator Side,.7 V to 5.5 V. GND Ground. Ground reference for isolator Side. 3 VIA Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C. 6 NC No Connect. 7 NC No Connect. 8 GND Ground. Ground reference for isolator Side. 9 GND Ground. Ground reference for isolator Side. VE Output Enable. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE is high or disconnected. VOA, VOB, and VOC outputs are disabled when VE is low. In noisy environments, connecting VE to an external logic high or low is recommended. NC No Connect. VOC Logic Output C. 3 VOB Logic Output B. 4 VOA Logic Output A. 5 GND Ground. Ground reference for isolator Side. 6 VDD Supply Voltage for Isolator Side,.7 V to 5.5 V. Table. ADuM3 Pin Function Descriptions Pin No. Mnemonic Function VDD Supply Voltage for Isolator Side,.7 V to 5.5 V. GND Ground. Ground reference for isolator Side. 3 VIA Logic Input A. 4 VIB Logic Input B. 5 VOC Logic Output C. 6 NC No Connect. 7 VE Output Enable. Active high logic input. VOC output is enabled when VE is high or disconnected. VOC is disabled when VE is low. In noisy environments, connecting VE to an external logic high or low is recommended. 8 GND Ground. Ground reference for isolator Side. 9 GND Ground. Ground reference for isolator Side. VE Output Enable. Active high logic input. VOA and VOB outputs are enabled when VE is high or disconnected. VOA and VOB outputs are disabled when VE is low. In noisy environments, connecting VE to an external logic high or low is recommended. NC No Connect. VIC Logic Input C. 3 VOB Logic Output B. 4 VOA Logic Output A. 5 GND Ground. Ground reference for isolator Side. 6 VDD Supply Voltage for Isolator Side,.7 V to 5.5 V. Rev. E Page 3 of

14 TYPICAL PERFORMANCE CHARACTERISTICS CURRENT/CHANNEL (ma) V 3V CURRENT (ma) 4 3 5V 3V DATA RATE (Mbps) Figure 6. Typical Input Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation DATA RATE (Mbps) Figure 9. Typical ADuM3 VDD Supply Current vs. Data Rate for 5 V and 3 V Operation CURRENT/CHANNEL (ma) 4 3 5V 3V CURRENT (ma) V 3V DATA RATE (Mbps) Figure 7. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load) DATA RATE (Mbps) Figure. Typical ADuM3 VDD Supply Current vs. Data Rate for 5 V and 3 V Operation CURRENT/CHANNEL (ma) V 3V CURRENT (ma) V 3V DATA RATE (Mbps) Figure 8. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (5 pf Output Load) DATA RATE (Mbps) Figure. Typical ADuM3 VDD Supply Current vs. Data Rate for 5 V and 3 V Operation Rev. E Page 4 of

15 3 4 5 CURRENT (ma) 5 5V 3V PROPAGATION DELAY (ns) V 5 5V DATA RATE (Mbps) Figure. Typical ADuM3 VDD Supply Current vs. Data Rate for 5 V and 3 V Operation TEMPERATURE ( C) Figure 3. Propagation Delay vs. Temperature, C Grade Rev. E Page 5 of

16 APPLICATION INFORMATION PC BOARD LAYOUT The ADuM3x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (Figure 4). Bypass capacitors are most conveniently connected between Pins and for VDD and between Pins 5 and 6 for VDD. The capacitor value should be between. μf and. μf. The total lead length between both ends of the capacitor and the input power supply pin should not exceed mm. Bypassing between Pins and 8 and between Pins 9 and 6 should also be considered unless the ground pair on each package side is connected close to the package. V DD GND V IA V IB V IC/OC NC V E GND V DD GND V OA V OB V OC/IC NC V E GND Figure 4. Recommended Printed Circuit Board Layout In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the device s Absolute Maximum Ratings, thereby leading to latch-up or permanent damage. PROPAGATION DELAY-RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to a logic high. INPUT (V IX ) OUTPUT (V OX ) t PLH t PHL 5% Figure 5. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal s timing is preserved. Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADuM3x component. 5% Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM3x components operating under the same conditions DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~ ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is therefore either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table ) by the watchdog timer circuit. The ADuM3x is extremely immune to external magnetic fields. The limitation on the ADuM3x s magnetic field immunity is set by the condition in which induced voltage in the transformer s receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM3x is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than. V. The decoder has a sensing threshold at about.5 V, thus establishing a.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = ( dβ/dt) rn ; n =,,, N where: β is magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the n th turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM3x and an imposed requirement that the induced voltage be at most 5% of the.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 6. MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss)... k k k M M M MAGNETIC FIELD FREQUENCY (Hz) Figure 6. Maximum Allowable External Magnetic Flux Density Rev. E Page 6 of

17 For example, at a magnetic field frequency of MHz, the maximum allowable magnetic field of. kgauss induces a voltage of.5 V at the receiving coil. This is about 5% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >. V to.75 V still well above the.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM3x transformers. Figure 7 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM3x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the MHz example noted, one would have to place a.5 ka current 5 mm away from the ADuM3x to affect the component s operation. MAXIMUM ALLOWABLE CURRENT (ka). DISTANCE = mm DISTANCE = 5mm DISTANCE = m. k k k M M M MAGNETIC FIELD FREQUENCY (Hz) Figure 7. Maximum Allowable Current for Various Current-to-ADuM3x Spacings Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. POWER CONSUMPTION The supply current at a given channel of the ADuM3x isolator is a function of the supply voltage, the channel s data rate, and the channel s output load. For each input channel, the supply current is given by IDDI = IDDI (Q) f.5 fr IDDI = IDDI (D) (f fr) + IDDI (Q) f >.5 fr For each output channel, the supply current is given by IDDO = IDDO (Q) f.5 fr IDDO = (IDDO (D) + (.5 3 ) CL VDDO) (f fr) + IDDO (Q) f >.5 fr where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (ma/mbps). CL is the output load capacitance (pf). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz); it is half of the input data rate expressed in units of Mbps. fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (ma). To calculate the total VDD and VDD supply current, the supply currents for each input and output channel corresponding to VDD and VDD are calculated and totaled. Figure 6 and Figure 7 provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 8 provides perchannel supply current as a function of data rate for a 5 pf output condition. Figure 9 through Figure provide total VDD and VDD supply current as a function of data rate for ADuM3/ADuM3 channel configurations. Rev. E Page 7 of

18 OUTLINE DIMENSIONS.5 (.434). (.3976) (.99) 7.4 (.93) 8.65 (.493). (.3937).3 (.8). (.39) COPLANARITY..7 (.5) BSC.5 (.).3 (.).65 (.43).35 (.95) SEATING PLANE 8.33 (.3). (.79).75 (.95).5 (.98) 45.7 (.5).4 (.57) COMPLIANT TO JEDEC STANDARDS MS-3-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 8. 6-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-6) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Number of Inputs, VDD Side Number of Inputs, VDD Side Maximum Data Rate (Mbps) Maximum Propagation Delay, 5 V (ns) Maximum Pulse Width Distortion (ns) Temperature Range ( C) Package Option ADuM3ARW to +5 RW-6 ADuM3BRW to +5 RW-6 ADuM3CRW to +5 RW-6 ADuM3ARWZ, to +5 RW-6 ADuM3BRWZ, to +5 RW-6 ADuM3CRWZ, to +5 RW-6 ADuM3ARW 4 4 to +5 RW-6 ADuM3BRW to +5 RW-6 ADuM3CRW to +5 RW-6 ADuM3ARWZ, to +5 RW-6 ADuM3BRWZ, to +5 RW-6 ADuM3CRWZ, to +5 RW-6 RW-6 = 6-lead wide body SOIC. Tape and reel are available. The addition of an -RL suffix designates a 3 (, units) tape-and-reel option. 3 Z = Pb-free part. Rev. E Page 8 of

19 NOTES Rev. E Page 9 of

20 NOTES 6 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C3787--/6(E) Rev. E Page of