High Speed, ESD-Protected, Full-Duplex, icoupler Isolated RS-485 Transceiver ADM2490E

Transcription

1 High Speed, ESD-Protected, Full-Duplex, icoupler Isolated RS-485 Transceiver FEATURES Isolated, full-duplex RS-485/RS-422 transceiver ±8 kv ESD protection on RS-485 input/output pins 16 Mbps data rate Complies with ANSI TIA/EIA-485-A-1998 and ISO 8482: 1987(E) Suitable for 5 V or 3 V operation (VDD1) High common-mode transient immunity: >25 kv/μs Receiver has open-circuit, fail-safe design 32 nodes on the bus Thermal shutdown protection Safety and regulatory approvals UL recognition: 5000 V rms isolation voltage for 1 minute per UL 1577 VDE certificate of conformity DIN EN (VDE Part 2): DIN EN (VDE 0805): ; EN 60950: 2000 VIORM = 848 V peak Operating temperature range: 40 C to +105 C Wide body, 16-lead SOIC package APPLICATIONS Isolated RS-485/RS-422 interfaces Industrial field networks INTERBUS Multipoint data transmission systems GENERAL DESCRIPTION The is an isolated data transceiver with ±8 kv ESD protection that is suitable for high speed, full-duplex communication on multipoint transmission lines. It is designed for balanced transmission lines and complies with ANSI TIA/EIA-485-A-1998 and ISO 8482: 1987(E). The device employs Analog Devices, Inc., icoupler technology to combine a 2-channel isolator, a threestate differential line driver, and a differential input receiver into a single package. The differential transmitter outputs and receiver inputs feature electrostatic discharge circuitry that provides protection to ±8 kv TxD RxD FUNCTIONAL BLOCK DIAGRAM V DD1 GND 1 GALVANIC ISOLATION Figure 1. V DD2 GND 2 using the human body model (HBM). The logic side of the device can be powered with either a 5 V or a 3 V supply, whereas the bus side requires an isolated 5 V supply. The device has current-limiting and thermal shutdown features to protect against output short circuits and situations where bus contention could cause excessive power dissipation. The is available in a wide body, 16-lead SOIC package and operates over the 40 C to +105 C temperature range. Y Z A B Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 * PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS Evaluation Board DOCUMENTATION Application Notes AN-0971: Recommendations for Control of Radiated Emissions with isopower Devices AN-1176: Component Footprints and Symbols in the Binary.Bxl File Format AN-1179: Junction Temperature Calculation for Analog Devices RS-485/RS-422, CAN, and LVDS/M-LVDS Transceivers AN-727: icoupler Isolation in RS-485 Applications AN-740: icoupler Isolation in RS-232 Applications AN-793: ESD/Latch-Up Considerations with icoupler Isolation Products AN-825: Power Supply Considerations in icoupler Isolation Products AN-960: RS-485/RS-422 Circuit Implementation Guide Data Sheet : High Speed ESD Protected Full-Duplex icoupler Isolated RS-485 Transceiver Data Sheet User Guides UG-496: Evaluating the 5 kv, Signal Isolated, High Speed, 16 Mbps, ESD Protected, Full Duplex, icoupler, Isolated RS-485 Transceiver SOFTWARE AND SYSTEMS REQUIREMENTS ADI RS-485/RS-422 Cross Reference Guide REFERENCE MATERIALS Press Analog Devices Achieves Major Milestone by Shipping 1 Billionth Channel of icoupler Digital Isolation Product Selection Guide Digital Isolator Product Selection and Resource Guide Solutions Bulletins & Brochures Emerging Energy Applications Solutions Bulletin, Volume 10, Issue 4 Test & Instrumentation Solutions Bulletin, Volume 10, Issue 3 Technical Articles Inside icoupler Technology:ADuM347x PWM Controller and Transformer Driver with Quad-Channel Isolators Design Summary NAppkin Note: Lowering the Power of the ADuM524x DESIGN RESOURCES Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints DISCUSSIONS View all EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

3 TABLE OF CONTENTS Features... 1 Applications... 1 Functional Block Diagram... 1 General Description... 1 Revision History... 2 Specifications... 3 Timing Specifications... 4 Package Characteristics... 4 Regulatory Information... 5 Insulation and Safety-Related Specifications... 5 VDE Insulation Characteristics... 5 Absolute Maximum Ratings... 6 ESD Caution... 6 Pin Configuration and Function Descriptions... 7 Test Circuits... 8 Switching Characteristics...9 Typical Performance Characteristics Circuit Description Electrical Isolation Truth Tables Thermal Shutdown Fail-Safe Receiver Inputs Magnetic Field Immunity Applications Information Isolated Power Supply Circuit PCB Layout Typical Applications Outline Dimensions Ordering Guide REVISION HISTORY 8/08 Rev. 0 to Rev. A Changes to Regulatory Approval Status Throughout... 1 Changed VDE 0884 to VDE Throughout... 1 Changes to Table Changes to Table Changes to Figure Changes to icoupler Technology Section Changes to Magnetic Field Immunity Section Changes to Isolated Power Supply Circuit Section Changes to Figure Added Typical Applications Section Updated Outline Dimensions Changes to Ordering Guide /06 Revision 0: Initial Version Rev. A Page 2 of 16

4 SPECIFICATIONS All voltages are relative to their respective ground; 2.7 VDD1 5.5 V, 4.5 V VDD2 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25 C, VDD1 = VDD2 = 5.0 V, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions SUPPLY CURRENT Power Supply Current, Logic Side TxD/RxD Data Rate < 2 Mbps IDD1 3.0 ma 2.7 V VDD1 5.5 V, unloaded TxD/RxD Data Rate = 16 Mbps IDD1 6 ma 100 Ω load between Y and Z Power Supply Current, Bus Side TxD/RxD Data Rate < 2 Mbps IDD2 4.0 ma 2.7 V VDD1 5.5 V, unloaded TxD/RxD Data Rate = 16 Mbps IDD2 60 ma 100 Ω load between Y and Z DRIVER Differential Outputs Differential Output Voltage, Loaded VOD V RL = 50 Ω (RS-422), see Figure V RL = 27 Ω (RS-485), see Figure 3 VOD V 7 V VTEST1 +12 V, see Figure 4 VOD for Complementary Output States VOD 0.2 V RL = 54 Ω or 100 Ω, see Figure 3 Common-Mode Output Voltage VOC 3.0 V RL = 54 Ω or 100 Ω, see Figure 3 VOC for Complementary Output States VOC 0.2 V RL = 54 Ω or 100 Ω, see Figure 3 Short-Circuit Output Current IOS 200 ma Logic Inputs Input Threshold Low VIL 0.25 VDD1 V Input Threshold High VIH 0.7 VDD1 V TxD Input Current ITxD μa RECEIVER Differential Inputs Differential Input Threshold Voltage VTH V Input Voltage Hysteresis VHYS 70 mv VOC = 0 V Input Current (A, B) II 1.0 ma VOC = 12 V 0.8 ma VOC = 7 V Line Input Resistance RIN 12 kω Logic Outputs Output Voltage Low VOLRxD V IORxD = 1.5 ma, VA VB = 0.2 V Output Voltage High VOHRxD VDD1 0.3 VDD1 0.2 V IORxD = 1.5 ma, VA VB = 0.2 V Short-Circuit Current 100 ma COMMON-MODE TRANSIENT IMMUNITY 1 25 kv/μs VCM = 1 kv, transient magnitude = 800 V 1 CM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common-mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. A Page 3 of 16

5 TIMING SPECIFICATIONS TA = 40 C to +85 C. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions DRIVER Maximum Data Rate 16 Mbps Propagation Delay tplh, tphl ns RL = 54 Ω, CL1 = C L2 = 100 pf, see Figure 6 and Figure 8 Pulse Width Distortion, PWD = tpylh tpyhl, PWD = tpzlh tpzhl tpwd, tpwd 7 ns RL = 54 Ω, CL1 = CL2 = 100 pf, see Figure 6 and Figure 8 Single-Ended Output Rise/Fall Times tr, tf 20 ns RL = 54 Ω, CL1 = CL2 = 100 pf, see Figure 6 and Figure 8 RECEIVER Propagation Delay tplh, tphl 60 ns CL = 15 pf, see Figure 7 and Figure 9 Pulse Width Distortion, PWD = tplh tphl tpwd 10 ns CL = 15 pf, see Figure 7 and Figure 9 TA = 40 C to +105 C. Table 3. Parameter Symbol Min Typ Max Unit Test Conditions DRIVER Maximum Data Rate 10 Mbps Propagation Delay tpylh, tpyhl, tpzlh, tpzhl ns RL = 54 Ω, CL1 = CL2 = 100 pf, see Figure 6 and Figure 8 Pulse Width Distortion, PWD = tpylh tpyhl, PWD = tpzlh tpzhl tpwd, tpwd 9 ns RL = 54 Ω, CL1 = CL2 = 100 pf, see Figure 6 and Figure 8 Single-Ended Output Rise/Fall Time tr, tf 27 ns RL = 54 Ω, CL1 = CL2 = 100 pf, see Figure 6 and Figure 8 RECEIVER Propagation Delay tplh, tphl 60 ns CL = 15 pf, see Figure 7 and Figure 9 Pulse Width Distortion, PWD = tplh tphl tpwd 10 ns CL = 15 pf, see Figure 7 and Figure 9 PACKAGE CHARACTERISTICS Table 4. Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input to Output) 1 RI-O Ω Capacitance (Input to Output) 1 CI-O 3 pf f = 1 MHz Input Capacitance 2 CI 4 pf Input IC Junction-to-Case Thermal Resistance θjci 33 C/W Thermocouple located at center of package underside Output IC Junction-to-Case Thermal Resistance θjco 28 C/W 1 Device considered a 2-terminal device: Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, and Pin 16 are shorted together. 2 Input capacitance is from any input data pin to ground. Rev. A Page 4 of 16

6 REGULATORY INFORMATION Table 5. Approvals Organization Approval Type Notes UL Recognized under the Component Recognition Program of Underwriters Laboratories, Inc. VDE Certified according to DIN EN (VDE Part 2): , DIN EN (VDE 0805): ; EN 60950: 2000 In accordance with UL 1577, each is proof tested by applying an insulation test voltage 6000 V rms for 1 second (current leakage detection limit = 10 μa). In accordance with DIN EN , each is proof tested by applying an insulation test voltage 1590 V peak for 1 second (partial discharge detection limit = 5 pc). INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 5000 V rms 1 minute duration Minimum External Air Gap (Clearance) L(I01) 7.45 mm min Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 8.1 mm min Measured from input terminals to output terminals, shortest distance along body Minimum Internal Gap (Internal Clearance) mm min Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89) VDE INSULATION CHARACTERISTICS This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data must be ensured by means of protective circuits. An asterisk (*) on a package denotes VDE approval for 848 V peak working voltage. Table 7. Description Symbol Characteristic Unit Installation Classification per DIN VDE 0110 for Rated Mains Voltage 300 V rms I to IV 450 V rms I to II 600 V rms I to II Climatic Classification 40/105/21 Pollution Degree (DIN VDE 0110, see Table 1) 2 Maximum Working Insulation Voltage VIORM 848 V peak Input-to-Output Test Voltage, Method b1 VPR 1590 V peak VIORM = VPR, 100% Production Tested, tm = 1 sec, Partial Discharge < 5 pc Input-to-Output Test Voltage, Method a After Environmental Tests, Subgroup 1 VIORM 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pc 1357 V peak After Input and/or Safety Test, Subgroup 2/3 VIORM 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pc VPR 1018 V peak Highest Allowable Overvoltage (Transient Overvoltage, ttr = 10 sec) VTR 6000 V peak Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure; see Figure 16) Case Temperature TS 150 C Input Current IS, INPUT 265 ma Output Current IS, OUTPUT 335 ma Insulation Resistance at TS, VIO = 500 V RS >10 9 Ω Rev. A Page 5 of 16

7 ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Each voltage is relative to its respective ground. Table 8. Parameter Storage Temperature Range Ambient Operating Temperature Range VDD1 VDD2 Logic Input Voltages Bus Terminal Voltages Logic Output Voltages Average Output Current, per Pin ESD (Human Body Model) on A, B, Y, and Z Pins θja Thermal Impedance Rating 55 C to +150 C 40 C to +105 C 0.5 V to +7 V 0.5 V to +6 V 0.5 V to VDD V 9 V to +14 V 0.5 V to VDD V ±35 ma ±8 kv 60 C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. ESD CAUTION Rev. A Page 6 of 16

8 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V DD1 1 GND V DD2 15 GND 2 RxD 3 14 A NC 4 TOP VIEW 13 B GND 1 5 (Not to Scale) 12 NC TxD 6 11 Z NC 7 10 Y GND GND 2 NC = NO CONNECT Figure 2. Pin Configuration Table 9. Pin Function Descriptions Pin No. Mnemonic Description 1 VDD1 Power Supply (Logic Side). Decoupling capacitor to GND1 required; capacitor value should be between 0.01 μf and 0.1 μf. 2, 5, 8 GND1 Ground (Logic Side). 3 RxD Receiver Output. 4, 7, 12 NC No Connect. These pins must be left floating. 6 TxD Transmit Data. 9, 15 GND2 Ground (Bus Side). 10 Y Driver Noninverting Output. 11 Z Driver Inverting Output. 13 B Receiver Inverting Input. 14 A Receiver Noninverting Input. 16 VDD2 Power Supply (Bus Side). Decoupling capacitor to GND2 required; capacitor value should be between 0.01 μf and 0.1 μf. Rev. A Page 7 of 16

9 TEST CIRCUITS V OD R L Y C L1 R L V OC Z R LDIFF C L Figure 3. Driver Voltage Measurement Figure 6. Driver Propagation Delay 375Ω A V OD3 60Ω V TEST 375Ω Figure 4. Driver Voltage Measurement V OUT B C L Figure 7. Receiver Propagation Delay V DD2 V DD1 V DD2 TxD RxD GALVANIC ISOLATION Y Z A B 220Ω 100Ω 220Ω GND 1 GND 2 GND 2 Figure 5. Supply-Current Measurement Test Circuit (See Figure 10 and Figure 11) Rev. A Page 8 of 16

10 SWITCHING CHARACTERISTICS 3V 1.5V 1.5V 0V Z t PLH t PHL VO 1/2VO Y t PWD = t PLH t PHL V OH A, B V OL 90% POINT 90% POINT 10% POINT 10% POINT t R t F Figure 8. Driver Propagation Delay, Rise/Fall Timing A, B 0V 0V t PLH t PHL VOH RxD 1.5V 1.5V Figure 9. Receiver Propagation Delay V OL Rev. A Page 9 of 16

11 TYPICAL PERFORMANCE CHARACTERISTICS t PLH t PHL I DD1 (ma) NO LOAD 100Ω LOAD 220Ω-100Ω-220Ω LOAD DELAY (ns) TEMPERATURE ( C) Figure 10. IDD1 Supply Current vs. Temperature (See Figure 5) TEMPERATURE ( C) Figure 13. Receiver Propagation Delay vs. Temperature Ω-100Ω-220Ω LOAD TxD I DD2 (ma) Ω LOAD 1 Y AND Z OUTPUTS 20 2 RxD 10 NO LOAD TEMPERATURE ( C) Figure 11. IDD2 Supply Current vs. Temperature (See Figure 5) CH1 2V CH3 2V CH2 2V CH4 2V M20ns A CH2 2.84V T 44.2% Figure 14. Driver/Receiver Propagation Delay, Low to High (RLDIFF = 54 Ω, CL1 = CL2 = 100 pf) t PZHL t PYLH t PZLH t PYHL 40 1 TxD DELAY (ns) 30 Y AND Z OUTPUTS RxD TEMPERATURE ( C) Figure 12. Driver Propagation Delay vs. Temperature CH1 2V CH3 2V CH2 2V CH4 2V M20ns A CH2 2.84V T 44.2% Figure 15. Driver/Receiver Propagation Delay, High to Low (RLDIFF = 54 Ω, CL1 = CL2 = 100 pf) Rev. A Page 10 of 16

12 SAFETY-LIMITING CURRENT (ma) SIDE 1 SIDE 2 VOLTAGE (V) CASE TEMPERATURE ( C) Figure 16. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per VDE TEMPERATURE ( C) Figure 19. Receiver Output High Voltage vs. Temperature, IRxD = 4 ma CURRENT (ma) 6 8 VOLTAGE (V) VOLTAGE (V) Figure 17. Output Current vs. Receiver Output High Voltage TEMPERATURE ( C) Figure 20. Receiver Output Low Voltage vs. Temperature, IRxD = 4 ma CURRENT (ma) VOLTAGE (V) Figure 18. Output Current vs. Receiver Output Low Voltage Rev. A Page 11 of 16

13 CIRCUIT DESCRIPTION ELECTRICAL ISOLATION In the, electrical isolation is implemented on the logic side of the interface. Therefore, the part has two main sections: a digital isolation section and a transceiver section (see Figure 21). The driver input signal, which is applied to the TxD pin and referenced to logic ground (GND1), is coupled across an isolation barrier to appear at the transceiver section referenced to isolated ground (GND2). Similarly, the receiver input, which is referenced to isolated ground in the transceiver section, is coupled across the isolation barrier to appear at the RxD pin referenced to logic ground. icoupler Technology The digital signals transmit across the isolation barrier using icoupler technology. This technique uses chip scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. Digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. At the secondary winding, the induced waveforms are decoded into the binary value that was originally transmitted. Positive and negative logic transitions at the input cause narrow pulses (~1 ns) to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the output is forced to a default state (see Table 12). TRUTH TABLES The truth tables in this section use the abbreviations shown in Table 10. Table 10. Truth Table Abbreviations Abbreviation Description H High level I Indeterminate L Low level X Irrelevant Table 11. Transmitting Supply Status Input Outputs VDD1 VDD2 TxD Y Z On On H H L On On L L H Table 12. Receiving Supply Status Inputs Output VDD1 VDD2 A B (V) RxD On On >0.2 H On On < 0.2 L On On 0.2 < A B < +0.2 I On On Inputs open H On Off X H Off On X H Off Off X L V DD1 V DD2 ISOLATION BARRIER TxD ENCODE DECODE D Y Z RxD DECODE ENCODE R A B DIGITAL ISOLATION TRANSCEIVER GND 1 GND 2 Figure 21. Digital Isolation and Transceiver Sections Rev. A Page 12 of 16

14 THERMAL SHUTDOWN The contains thermal-shutdown circuitry that protects the part from excessive power dissipation during fault conditions. Shorting the driver outputs to a low impedance source can result in high driver currents. The thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. This circuitry is designed to disable the driver outputs when a die temperature of 150 C is reached. As the device cools, the drivers are re-enabled at a temperature of 140 C. FAIL-SAFE RECEIVER INPUTS The receiver inputs include a fail-safe feature that guarantees a logic high on the RxD pin when the A and B inputs are floating or open-circuited. MAGNETIC FIELD IMMUNITY The limitation on the magnetic field immunity of the icoupler is set by the condition in which an induced voltage in the receiving coil of the transformer is large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than 1 V. The decoder has a sensing threshold of about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by dβ 2 V = πrn ; n = 1, 2, K, N dt where: β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the n th turn in the receiving coil (cm). Given the geometry of the receiving coil and an imposed requirement that the induced voltage is, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field can be determined using Figure 22. MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) k 10k 100k 1M 10M 100M MAGNETIC FIELD FREQUENCY (Hz) Figure 22. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse and is the worst-case polarity, it reduces the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder. Figure 23 shows the magnetic flux density values in terms of more familiar quantities, such as maximum allowable current flow at given distances away from the transformers. MAXIMUM ALLOWABLE CURRENT (ka) DISTANCE = 5mm DISTANCE = 100mm DISTANCE = 1m k 10k 100k 1M 10M 100M MAGNETIC FIELD FREQUENCY (Hz) Figure 23. Maximum Allowable Current for Various Current-to- Spacings With combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce error voltages large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility Rev. A Page 13 of 16

15 APPLICATIONS INFORMATION ISOLATED POWER SUPPLY CIRCUIT The requires isolated power capable of 5 V at up to approximately 65 ma (this current is dependent on the data rate and termination resistors used) to be supplied between the VDD2 and the GND2 pins. A transformer driver circuit with a center-tapped transformer and LDO can be used to generate the isolated 5 V supply, as shown in Figure 25. The center-tapped transformer provides electrical isolation of the 5 V power supply. The primary winding of the transformer is excited with a pair of square waveforms that are 180 out of phase with each other. A pair of Schottky diodes and a smoothing capacitor are used to create a rectified signal from the secondary winding. The ADP3330 linear voltage regulator provides a regulated power supply to the bus-side circuitry (VDD2) of the. PCB LAYOUT The isolated RS-485 transceiver requires no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins (see Figure 24). Bypass capacitors are conveniently connected between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VDD2. The capacitor value should be between 0.01 μf and 0.1 μf. The total lead length between both ends of the capacitor and the input power-supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless the ground pair on each package side is connected close to the package. V DD1 GND 1 RxD NC GND 1 TxD NC GND 1 V DD2 GND 2 A B NC Z Y GND 2 NC = NO CONNECT Figure 24. Recommended Printed Circuit Board Layout In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage V CC ISOLATION BARRIER SD103C 5V IN OUT TRANSFORMER DRIVER V CC 22µF 10µF ADP3330 SD GND ERR SD103C V CC V DD1 V DD2 GND 1 GND Figure 25. Isolated Power-Supply Circuit Rev. A Page 14 of 16

16 TYPICAL APPLICATIONS The transceiver is designed for point-to-point transmission lines. Figure 26 shows a full-duplex point-to-point application. To minimize reflections, terminate the line at the receiver end with a termination resistor. The value of the termination resistor should be equal to the characteristic impedance of the cable. RxO R A B R T Y Z D TxD Z B TxD D Y R T A R RxD NOTES 1. R T IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE. Figure 26. Full-Duplex Point-to-Point Application Rev. A Page 15 of 16

17 OUTLINE DIMENSIONS (0.4134) (0.3976) (0.2992) 7.40 (0.2913) (0.4193) (0.3937) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 1.27 (0.0500) BSC 2.65 (0.1043) 2.35 (0.0925) (0.0201) SEATING PLANE 0.33 (0.0130) 0.31 (0.0122) 0.20 (0.0079) (0.0295) 0.25 (0.0098) (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Temperature Range Package Description Package Option BRWZ 1 40 C to +105 C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 BRWZ-REEL C to +105 C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 1 Z = RoHS Compliant Part B Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /08(A) Rev. A Page 16 of 16