Dual-Channel Digital Isolators ADuM1200/ADuM1201

Transcription

1 Dual-Channel Digital Isolators ADuM/ADuM FEATURES Narrow body, RoHS-compliant, SOIC 8-lead package Low power operation 5 V operation. ma per channel Mbps to Mbps 3.7 ma per channel Mbps 8. ma per channel 5 Mbps 3 V operation.8 ma per channel Mbps to Mbps. ma per channel Mbps.8 ma per channel 5 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 5 C High data rate: dc to 5 Mbps (NRZ) Precise timing characteristics 3 ns maximum pulse width distortion 3 ns maximum channel-to-channel matching High common-mode transient immunity: >5 kv/μs Safety and regulatory approvals UL recognition 5 V rms for minute per UL 577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN V VDE V 88- (VDE V 88-):6- VIORM = 56 V peak APPLICATIONS Size-critical multichannel isolation SPI interface/data converter isolation RS-3/RS-/RS-85 transceiver isolation Digital field bus isolation GENERAL DESCRIPTION The ADuMx are dual-channel, digital isolators based on the Analog Devices, Inc. icoupler technology. Combining high speed CMOS and monolithic transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives, such as optocoupler devices. By avoiding the use of LEDs and photodiodes, icoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple icoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these icoupler products. Furthermore, icoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The ADuMx isolators provide two independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). Both parts operate with the supply voltage on either side ranging from.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuMx provide low pulse width distortion (<3 ns for CR grade) and tight channel-to-channel matching (<3 ns for CR grade). Unlike other optocoupler alternatives, the ADuMx isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. Protected by U.S. Patents 5,95,89; 6,873,65; 6,93,578; and 7,75,39. Other patents are pending. FUNCTIONAL BLOCK DIAGRAMS V DD 8 V DD V DD 8 V DD V IA ENCODE DECODE 7 V OA V OA DECODE ENCODE 7 V IA V IB 3 ENCODE DECODE 6 V OB V IB 3 ENCODE DECODE 6 V OB GND 5 GND 6- GND 5 GND 6- Figure. ADuM Functional Block Diagram Figure. ADuM Functional Block Diagram Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 ADuM/ADuM TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagrams... Revision History... Specifications... 3 Electrical Characteristics 5 V Operation... 3 Electrical Characteristics 3 V Operation... 5 Electrical Characteristics Mixed 5 V/3 V or 3 V/5 V Operation... 7 Package Characteristics... Regulatory Information... Insulation and Safety-Related Specifications... DIN V VDE V 88- (VDE V 88-):6- Insulation Characteristics... Recommended Operating Conditions... Absolute Maximum Ratings... ESD Caution... Pin Configurations and Function Descriptions... 3 Typical Performance Characteristics... Application Information... 5 PC Board Layout... 5 Propagation Delay-Related Parameters... 5 DC Correctness and Magnetic Field Immunity... 5 Power Consumption... 6 Insulation Lifetime... 6 Outline Dimensions... 8 Ordering Guide... 8 REVISION HISTORY /7 Rev. D to Rev. E Changes to Note... Added ADuMxAR Change vs. Temperature Parameter... 3 Added ADuMxAR Change vs. Temperature Parameter... 5 Added ADuMxAR Change vs. Temperature Parameter /7 Rev. C to Rev. D Updated VDE Certification Throughout... Changes to Features, Note, Figure, and Figure... Changes to Table Changes to Regulatory Information Section... Added Table... Added Insulation Lifetime Section... 6 Updated Outline Dimensions... 8 Changes to Ordering Guide... 8 /6 Rev. B to Rev. C Updated Format...Universal Added Note... Changes to Absolute Maximum Ratings... Changes to DC Correctness and Magnetic Field Immunity Section / Rev. A to Rev. B Changes to Table / Rev. to Rev. A Changes to Format...Universal Changes to General Description... Changes to Electrical Characteristics 5 V Operation...3 Changes to Electrical Characteristics 3 V Operation...5 Changes to Electrical Characteristics Mixed 5 V/3 V or 3 V/5 V Operation...7 / Revision : Initial Version Rev. E Page of

3 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 5 V OPERATION ADuM/ADuM All voltages are relative to their respective ground..5 V VDD 5.5 V,.5 V VDD 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 5 C, VDD = VDD = 5 V. Table. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent IDDI (Q).5.6 ma Output Supply Current per Channel, Quiescent IDDO (Q).9.5 ma ADuM Total Supply Current, Two Channels DC to Mbps VDD Supply Current IDD (Q).. ma DC to MHz logic signal freq. VDD Supply Current IDD (Q).5.8 ma DC to MHz logic signal freq. Mbps (BR and CR Grades Only) VDD Supply Current IDD () ma 5 MHz logic signal freq. VDD Supply Current IDD ().3. ma 5 MHz logic signal freq. 5 Mbps (CR Grade Only) VDD Supply Current IDD (5) 3 ma.5 MHz logic signal freq. VDD Supply Current IDD (5).8 3. ma.5 MHz logic signal freq. ADuM Total Supply Current, Two Channels DC to Mbps VDD Supply Current IDD (Q).8. ma DC to MHz logic signal freq. VDD Supply Current IDD (Q).8. ma DC to MHz logic signal freq. Mbps (BR and CR Grades Only) VDD Supply Current IDD () ma 5 MHz logic signal freq. VDD Supply Current IDD () ma 5 MHz logic signal freq. 5 Mbps (CR Grade Only) VDD Supply Current IDD (5) ma.5 MHz logic signal freq. VDD Supply Current IDD (5) ma.5 MHz logic signal freq. For All Models Input Currents IIA, IIB +. + μa V VIA, VIB VDD or VDD Logic High Input Threshold VIH.7 (VDD or VDD) V Logic Low Input Threshold VIL.3 (VDD or VDD) V Logic High Output Voltages VOAH (VDD or VDD). 5. V IOx = μa, VIx = VIxH VOBH (VDD or VDD).5.8 V IOx = ma, VIx = VIxH Logic Low Output Voltages VOAL.. V IOx = μa, VIx = VIxL VOBL.. V IOx = μa, VIx = VIxL.. V IOx = ma, VIx = VIxL SWITCHING SPECIFICATIONS ADuMxAR Minimum Pulse Width PW ns CL = 5 pf, CMOS signal levels Maximum Data Rate 3 Mbps CL = 5 pf, CMOS signal levels Propagation Delay tphl, tplh 5 5 ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl PWD ns CL = 5 pf, CMOS signal levels Change vs. Temperature ps/ C CL = 5 pf, CMOS signal levels Propagation Delay Skew 5 tpsk ns CL = 5 pf, CMOS signal levels Channel-to-Channel Matching 6 tpskcd/tpskod 5 ns CL = 5 pf, CMOS signal levels Output Rise/Fall Time (% to 9%) tr/tf ns CL = 5 pf, CMOS signal levels Rev. E Page 3 of

4 ADuM/ADuM Parameter Symbol Min Typ Max Unit Test Conditions ADuMxBR Minimum Pulse Width PW ns CL = 5 pf, CMOS signal levels Maximum Data Rate 3 Mbps CL = 5 pf, CMOS signal levels Propagation Delay tphl, tplh 5 ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl PWD 3 ns CL = 5 pf, CMOS signal levels Change vs. Temperature 5 ps/ C CL = 5 pf, CMOS signal levels Propagation Delay Skew 5 tpsk 5 ns CL = 5 pf, CMOS signal levels tpskcd 3 ns CL = 5 pf, CMOS signal levels Codirectional Channels 6 Opposing Directional Channels 6 tpskod 5 ns CL = 5 pf, CMOS signal levels Output Rise/Fall Time (% to 9%) tr/tf.5 ns CL = 5 pf, CMOS signal levels ADuMxCR Minimum Pulse Width PW ns CL = 5 pf, CMOS signal levels Maximum Data Rate Mbps CL = 5 pf, CMOS signal levels Propagation Delay tphl, tplh 5 ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl PWD 3 ns CL = 5 pf, CMOS signal levels Change vs. Temperature 5 ps/ C CL = 5 pf, CMOS signal levels Propagation Delay Skew 5 tpsk 5 ns CL = 5 pf, CMOS signal levels tpskcd 3 ns CL = 5 pf, CMOS signal levels Codirectional Channels 6 Opposing Directional Channels 6 tpskod 5 ns CL = 5 pf, CMOS signal levels Output Rise/Fall Time (% to 9%) tr/tf.5 ns CL = 5 pf, CMOS signal levels For All Models Common-Mode Transient Immunity at Logic High Output 7 CMH 5 35 kv/μs VIx = VDD or VDD, VCM = V, transient magnitude = 8 V Common-Mode Transient Immunity at Logic Low Output 7 CML 5 35 kv/μs VIx = V, VCM = V, transient magnitude = 8 V Refresh Rate fr. Mbps Input Dynamic Supply Current per Channel 8 IDDI (D).9 ma/mbps Output Dynamic Supply Current per Channel 8 IDDO (D).5 ma/mbps The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure for total VDD and VDD supply currents as a function of data rate for ADuM and ADuM channel configurations. The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. tphl propagation delay is measured from the 5% level of the falling edge of the VIx signal to the 5% level of the falling edge of the VOx signal. tplh propagation delay is measured from the 5% level of the rising edge of the VIx signal to the 5% level of the rising edge of the VOx signal. 5 tpsk is the magnitude of the worst-case difference in tphl and/or tplh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO >.8 VDD. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO <.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate. Rev. E Page of

5 ELECTRICAL CHARACTERISTICS 3 V OPERATION ADuM/ADuM All voltages are relative to their respective ground..7 V VDD 3.6 V,.7 V VDD 3.6 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 5 C, VDD = VDD = 3. V. Table. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent IDDI (Q).6.35 ma Output Supply Current per Channel, Quiescent IDDO (Q).. ma ADuM Total Supply Current, Two Channels DC to Mbps VDD Supply Current IDD (Q).6. ma DC to MHz logic signal freq. VDD Supply Current IDD (Q)..6 ma DC to MHz logic signal freq. Mbps (BR and CR Grades Only) VDD Supply Current IDD (). 3. ma 5 MHz logic signal freq. VDD Supply Current IDD ().7. ma 5 MHz logic signal freq. 5 Mbps (CR Grade Only) VDD Supply Current IDD (5) ma.5 MHz logic signal freq. VDD Supply Current IDD (5).5. ma.5 MHz logic signal freq. ADuM Total Supply Current, Two Channels DC to Mbps VDD Supply Current IDD (Q)..8 ma DC to MHz logic signal freq. VDD Supply Current IDD (Q)..8 ma DC to MHz logic signal freq. Mbps (BR and CR Grades Only) VDD Supply Current IDD ().5. ma 5 MHz logic signal freq. VDD Supply Current IDD ().5. ma 5 MHz logic signal freq. 5 Mbps (CR Grade Only) VDD Supply Current IDD (5) 3..8 ma.5 MHz logic signal freq. VDD Supply Current IDD (5) 3..8 ma.5 MHz logic signal freq. For All Models Input Currents IIA, IIB +. + μa V VIA, VIB VDD or VDD Logic High Input Threshold VIH.7 (VDD or VDD) V Logic Low Input Threshold VIL.3 (VDD or VDD) Logic High Output Voltages VOAH (VDD or VDD) 3. V IOx = μa, VIx = VIxH. VOBH (VDD or VDD).5.8 V IOx = ma, VIx = VIxH Logic Low Output Voltages VOAL.. V IOx = μa, VIx = VIxL VOBL.. V IOx = μa, VIx = VIxL.. V IOx = ma, VIx = VIxL SWITCHING SPECIFICATIONS ADuMxAR Minimum Pulse Width PW ns CL = 5 pf, CMOS signal levels Maximum Data Rate 3 Mbps CL = 5 pf, CMOS signal levels Propagation Delay tphl, tplh 5 5 ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl PWD ns CL = 5 pf, CMOS signal levels Change vs. Temperature ps/ C CL = 5 pf, CMOS signal levels Propagation Delay Skew 5 tpsk ns CL = 5 pf, CMOS signal levels Channel-to-Channel Matching 6 tpskcd/tpskod 5 ns CL = 5 pf, CMOS signal levels Output Rise/Fall Time (% to 9%) tr/tf ns CL = 5 pf, CMOS signal levels Rev. E Page 5 of

6 ADuM/ADuM Parameter Symbol Min Typ Max Unit Test Conditions ADuMxBR Minimum Pulse Width PW ns CL = 5 pf, CMOS signal levels Maximum Data Rate 3 Mbps CL = 5 pf, CMOS signal levels Propagation Delay tphl, tplh 6 ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl PWD 3 ns CL = 5 pf, CMOS signal levels Change vs. Temperature 5 ps/ C CL = 5 pf, CMOS signal levels Propagation Delay Skew 5 tpsk ns CL = 5 pf, CMOS signal levels tpskcd 3 ns CL = 5 pf, CMOS signal levels Codirectional Channels 6 Opposing Directional Channels 6 tpskod ns CL = 5 pf, CMOS signal levels Output Rise/Fall Time (% to 9%) tr/tf 3. ns CL = 5 pf, CMOS signal levels ADuMxCR Minimum Pulse Width PW ns CL = 5 pf, CMOS signal levels Maximum Data Rate Mbps CL = 5 pf, CMOS signal levels Propagation Delay tphl, tplh 55 ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl PWD 3 ns CL = 5 pf, CMOS signal levels Change vs. Temperature 5 ps/ C CL = 5 pf, CMOS signal levels Propagation Delay Skew 5 tpsk 6 ns CL = 5 pf, CMOS signal levels tpskcd 3 ns CL = 5 pf, CMOS signal levels Codirectional Channels 6 Opposing Directional Channels 6 tpskod 6 ns CL = 5 pf, CMOS signal levels Output Rise/Fall Time (% to 9%) tr/tf 3. ns CL = 5 pf, CMOS signal levels For All Models Common-Mode Transient Immunity at Logic High Output 7 CMH 5 35 kv/μs VIx = VDD or VDD, VCM = V, transient magnitude = 8 V Common=Mode Transient Immunity at Logic Low Output 7 CML 5 35 kv/μs VIx = V, VCM = V, transient magnitude = 8 V Refresh Rate fr. Mbps Input Dynamic Supply Current per Channel 8 IDDI (D). ma/mbps Output Dynamic Supply Current per Channel 8 IDDO (D).3 ma/mbps The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure for total VDD and VDD supply currents as a function of data rate for ADuM and ADuM channel configurations. The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. tphl propagation delay is measured from the 5% level of the falling edge of the VIx signal to the 5% level of the falling edge of the VOx signal. tplh propagation delay is measured from the 5% level of the rising edge of the VIx signal to the 5% level of the rising edge of the VOx signal. 5 tpsk is the magnitude of the worst-case difference in tphl and/or tplh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO >.8 VDD. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO <.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate. Rev. E Page 6 of

7 ADuM/ADuM ELECTRICAL CHARACTERISTICS MIXED 5 V/3 V OR 3 V/5 V OPERATION All voltages are relative to their respective ground. 5 V/3 V operation:.5 V VDD 5.5 V,.7 V VDD 3.6 V. 3 V/5 V operation:.7 V VDD 3.6 V,.5 V VDD 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 5 C; VDD = 3. V, VDD = 5. V; or VDD = 5. V, VDD = 3. V. Table 3. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current per Channel, Quiescent IDDI (Q) 5 V/3 V Operation.5.6 ma 3 V/5 V Operation.6.35 ma Output Supply Current per Channel, Quiescent IDDO (Q) 5 V/3 V Operation.. ma 3 V/5 V Operation.9.5 ma ADuM Total Supply Current, Two Channels DC to Mbps VDD Supply Current IDD (Q) 5 V/3 V Operation.. ma DC to MHz logic signal freq. 3 V/5 V Operation.6. ma DC to MHz logic signal freq. VDD Supply Current IDD (Q) 5 V/3 V Operation..6 ma DC to MHz logic signal freq. 3 V/5 V Operation.5.8 ma DC to MHz logic signal freq. Mbps (BR and CR Grades Only) VDD Supply Current IDD () 5 V/3 V Operation ma 5 MHz logic signal freq. 3 V/5 V Operation. 3. ma 5 MHz logic signal freq. VDD Supply Current IDD () 5 V/3 V Operation.7. ma 5 MHz logic signal freq. 3 V/5 V Operation.3. ma 5 MHz logic signal freq. 5 Mbps (CR Grade Only) VDD Supply Current IDD (5) 5 V/3 V Operation 3 ma.5 MHz logic signal freq. 3 V/5 V Operation ma.5 MHz logic signal freq. VDD Supply Current IDD (5) 5 V/3 V Operation.5. ma.5 MHz logic signal freq. 3 V/5 V Operation.8 3. ma.5 MHz logic signal freq. ADuM Total Supply Current, Two Channels DC to Mbps VDD Supply Current IDD (Q) 5 V/3 V Operation.8. ma DC to MHz logic signal freq. 3 V/5 V Operation..8 ma DC to MHz logic signal freq. VDD Supply Current IDD (Q) 5 V/3 V Operation..8 ma DC to MHz logic signal freq. 3 V/5 V Operation.8. ma DC to MHz logic signal freq. Mbps (BR and CR Grades Only) VDD Supply Current IDD () 5 V/3 V Operation ma 5 MHz logic signal freq. 3 V/5 V Operation.5. ma 5 MHz logic signal freq. VDD Supply Current IDD () 5 V/3 V Operation.5. ma 5 MHz logic signal freq. 3 V/5 V Operation ma 5 MHz logic signal freq. 5 Mbps (CR Grade Only) VDD Supply Current IDD (5) 5 V/3 V Operation ma.5 MHz logic signal freq. 3 V/5 V Operation 3..8 ma.5 MHz logic signal freq. VDD Supply Current IDD (5) 5 V/3 V Operation 3..8 ma.5 MHz logic signal freq. 3 V/5 V Operation ma.5 MHz logic signal freq. Rev. E Page 7 of

8 ADuM/ADuM Parameter Symbol Min Typ Max Unit Test Conditions For All Models Input Currents IIA, IIB +. + μa V VIA, VIB VDD or VDD Logic High Input Threshold VIH.7 (VDD or VDD) V Logic Low Input Threshold VIL.3 (VDD or VDD) Logic High Output Voltages VOAH, VOBH (VDD or VDD). (VDD or VDD).5 (VDD or VDD) (VDD or VDD). V V V IOx = μa, VIx = VIxH IOx = ma, VIx = VIxH Logic Low Output Voltages VOAL, VOBL.. V IOx = μa, VIx = VIxL.. V IOx = μa, VIx = VIxL.. V IOx = ma, VIx = VIxL SWITCHING SPECIFICATIONS ADuMxAR Minimum Pulse Width PW ns CL = 5 pf, CMOS signal levels Maximum Data Rate 3 Mbps CL = 5 pf, CMOS signal levels Propagation Delay tphl, tplh 5 5 ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl PWD ns CL = 5 pf, CMOS signal levels Change vs. Temperature ps/ C CL = 5 pf, CMOS signal levels Propagation Delay Skew 5 tpsk 5 ns CL = 5 pf, CMOS signal levels Channel-to-Channel Matching 6 tpskcd/tpskod 5 ns CL = 5 pf, CMOS signal levels Output Rise/Fall Time (% to 9%) tr/tf ns CL = 5 pf, CMOS signal levels ADuMxBR Minimum Pulse Width PW ns CL = 5 pf, CMOS signal levels Maximum Data Rate 3 Mbps CL = 5 pf, CMOS signal levels Propagation Delay tphl, tplh 5 55 ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl PWD 3 ns CL = 5 pf, CMOS signal levels Change vs. Temperature 5 ps/ C CL = 5 pf, CMOS signal levels Propagation Delay Skew 5 tpsk ns CL = 5 pf, CMOS signal levels tpskcd 3 ns CL = 5 pf, CMOS signal levels Codirectional Channels 6 tpskod ns CL = 5 pf, CMOS signal levels Opposing Directional Channels 6 Output Rise/Fall Time % to 9%) tr/tf CL = 5 pf, CMOS signal levels 5 V/3 V Operation 3. ns 3 V/5 V Operation.5 ns ADuMxCR Minimum Pulse Width PW ns CL = 5 pf, CMOS signal levels Maximum Data Rate Mbps CL = 5 pf, CMOS signal levels Propagation Delay tphl, tplh 5 ns CL = 5 pf, CMOS signal levels Pulse Width Distortion, tplh tphl PWD 3 ns CL = 5 pf, CMOS signal levels Change vs. Temperature 5 ps/ C CL = 5 pf, CMOS signal levels Propagation Delay Skew 5 tpsk 5 ns CL = 5 pf, CMOS signal levels tpskcd 3 ns CL = 5 pf, CMOS signal levels Codirectional Channels 6 tpskod 5 ns CL = 5 pf, CMOS signal levels Opposing Directional Channels 6 Output Rise/Fall Time (% to 9%) tr/tf CL = 5 pf, CMOS signal levels 5 V/3 V Operation 3. ns 3 V/5 V Operation.5 ns Rev. E Page 8 of

9 ADuM/ADuM Parameter Symbol Min Typ Max Unit Test Conditions For All Models Common-Mode Transient Immunity at Logic High Output 7 CMH 5 35 kv/μs VIx = VDD or VDD, VCM = V, transient magnitude = 8 V Common-Mode Transient Immunity at Logic Low Output 7 CML 5 35 kv/μs VIx = V, VCM = V, transient magnitude = 8 V Refresh Rate fr 5 V/3 V Operation. Mbps 3 V/5 V Operation. Mbps Input Dynamic Supply Current per Channel 8 IDDI (D) 5 V/3 V Operation.9 ma/mbps 3 V/5 V Operation. ma/mbps Output Dynamic Supply Current per Channel 8 IDDO (D) 5 V/3 V Operation.3 ma/mbps 3 V/5 V Operation.5 ma/mbps The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure for total VDD and VDD supply currents as a function of data rate for ADuM and ADuM channel configurations. The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. tphl propagation delay is measured from the 5% level of the falling edge of the VIx signal to the 5% level of the falling edge of the VOx signal. tplh propagation delay is measured from the 5% level of the rising edge of the VIx signal to the 5% level of the rising edge of the VOx signal. 5 tpsk is the magnitude of the worst-case difference in tphl and/or tplh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO >.8 VDD. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO <.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate. Rev. E Page 9 of

10 ADuM/ADuM PACKAGE CHARACTERISTICS Table. Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input-to-Output) RI-O Ω Capacitance (Input-to-Output) CI-O. pf f = MHz Input Capacitance CI. pf IC Junction-to-Case Thermal Resistance, Side θjci 6 C/W Thermocouple located at center of package underside IC Junction-to-Case Thermal Resistance, Side θjco C/W The device is considered a -terminal device; Pin, Pin, Pin 3, and Pin are shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together. REGULATORY INFORMATION The ADuM/ADuM are approved by the organizations listed in Table 5. Refer to Table and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 5. UL CSA VDE Recognized Under 577 Component Recognition Program Approved under CSA Component Acceptance Notice #5A Certified according to DIN V VDE V 88- (VDE V 88-):6- Single/Basic 5 V rms Isolation Voltage Basic insulation per CSA and Reinforced insulation, 56 V peak IEC 695-, V rms (566 peak) maximum working voltage Functional insulation per CSA and IEC 695-, 8 V rms (3 V peak) maximum working voltage File E File 578 File In accordance with UL 577, each ADuMx is proof tested by applying an insulation test voltage 3 V rms for second (current leakage detection limit = 5 μa). In accordance with DIN V VDE V 88-, each ADuMx is proof tested by applying an insulation test voltage 5 V peak for sec (partial discharge detection limit = 5 pc). The * marking branded on the component designates DIN V VDE V 88- approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 5 V rms -minute duration Minimum External Air Gap (Clearance) L(I).9 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I). min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance).7 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >75 V DIN IEC /VDE 33 Part Isolation Group IIIa Material Group (DIN VDE, /89, Table ) Rev. E Page of

11 ADuM/ADuM DIN V VDE V 88- (VDE V 88-):6- INSULATION CHARACTERISTICS This isolator is suitable for reinforced isolation, only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. Note that the * marking on the package denotes DIN V VDE V 88- approval for a 56 V peak working voltage. Table 7. Description Conditions Symbol Characteristic Unit Installation Classification per DIN VDE For Rated Mains Voltage 5 V rms I to IV For Rated Mains Voltage 3 V rms I to III For Rated Mains Voltage V rms I to II Climatic Classification /5/ Pollution Degree per DIN VDE, Table Maximum Working Insulation Voltage VIORM 56 V peak Input-to-Output Test Voltage, Method B VIORM.875 = VPR, % production test, tm = sec, VPR 5 V peak partial discharge < 5 pc Input-to-Output Test Voltage, Method A VIORM.6 = VPR, tm = 6 sec, partial discharge < 5 pc VPR After Environmental Tests Subgroup 896 V peak After Input and/or Safety Test Subgroup VIORM. = VPR, tm = 6 sec, partial discharge < 5 pc 67 V peak and Subgroup 3 Highest Allowable Overvoltage Transient overvoltage, ttr = seconds VTR V peak Safety-Limiting Values Maximum value allowed in the event of a failure (see Figure 3) Case Temperature TS 5 C Side Current IS 6 ma Side Current IS 7 ma Insulation Resistance at TS VIO = 5 V RS > 9 Ω SAFETY-LIMITING CURRENT (ma) SIDE # SIDE # RECOMMENDED OPERATING CONDITIONS Table 8. Parameter Operating Temperature (TA) Supply Voltages (VDD, VDD) Input Signal Rise and Fall Times Rating C to +5 C.7 V to 5.5 V. ms All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields. 5 5 CASE TEMPERATURE ( C) Figure 3. Thermal Derating Curve, Dependence of Safety- Limiting Values on Case Temperature per DIN V VDE V Rev. E Page of

12 ADuM/ADuM ABSOLUTE MAXIMUM RATINGS Ambient temperature = 5 C, unless otherwise noted. Table 9. Parameter Storage Temperature (TST) Ambient Operating Temperature (TA) Supply Voltages (VDD, VDD) Input Voltages (VIA, VIB), Output Voltages (VOA, VOB), Average Output Current per Pin (IO) 3 Common-Mode Transients (CML, CMH) Rating 55 C to +5 C C to +5 C.5 V to +7. V.5 V to VDDI +.5 V.5 V to VDDO +.5 V 35 ma to +35 ma kv/μs to + kv/μs Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION All voltages are relative to their respective ground. VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. 3 See Figure 3 for maximum rated current values for various temperatures. Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating can cause latch-up or permanent damage. Table. Maximum Continuous Working Voltage Parameter Max Unit Constraint AC Voltage, Bipolar Waveform 565 V peak 5-year minimum lifetime AC Voltage, Unipolar Waveform Functional Insulation 3 V peak Maximum approved working voltage per IEC 695- Basic Insulation 56 V peak Maximum approved working voltage per IEC 695- and VDE V 88- DC Voltage Functional Insulation 3 V peak Maximum approved working voltage per IEC 695- Basic Insulation 56 V peak Maximum approved working voltage per IEC 695- and VDE V 88- Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Table. ADuM Truth Table (Positive Logic) VIA Input VIB Input VDD State VDD State VOA Output VOB Output Notes H H Powered Powered H H L L Powered Powered L L H L Powered Powered H L L H Powered Powered L H X X Unpowered Powered H H Outputs return to the input state within μs of VDDI power restoration. X X Powered Unpowered Indeterminate Indeterminate Outputs return to the input state within μs of VDDO power restoration. Table. ADuM Truth Table (Positive Logic) VIA Input VIB Input VDD State VDD State VOA Output VOB Output Notes H H Powered Powered H H L L Powered Powered L L H L Powered Powered H L L H Powered Powered L H X X Unpowered Powered Indeterminate H Outputs return to the input state within μs of VDD power restoration. X X Powered Unpowered H Indeterminate Outputs return to the input state within μs of VDDO power restoration. Rev. E Page of

13 ADuM/ADuM PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V DD 8 V DD V IA ADuM 7 V OA V IB 3 TOP VIEW (Not to Scale) 6 V OB GND 5 GND Figure. ADuM Pin Configuration 6- V DD 8 V DD ADuM V OA 7 V IA V 3 TOP VIEW IB 6 V (Not to Scale) OB GND 5 GND Figure 5. ADuM Pin Configuration 6-5 Table 3. ADuM Pin Function Descriptions Pin No. Mnemonic Description VDD Supply Voltage for Isolator Side,.7 V to 5.5 V. VIA Logic Input A. 3 VIB Logic Input B. GND Ground. Ground Reference for Isolator Side. 5 GND Ground. Ground Reference for Isolator Side. 6 VOB Logic Output B. 7 VOA Logic Output A. 8 VDD Supply Voltage for Isolator Side,.7 V to 5.5 V. Table. ADuM Pin Function Descriptions Pin No. Mnemonic Description VDD Supply Voltage for Isolator Side,.7 V to 5.5 V. VOA Logic Output A. 3 VIB Logic Input B. GND Ground. Ground Reference for Isolator Side. 5 GND Ground. Ground Reference for Isolator Side. 6 VOB Logic Output B. 7 VIA Logic Input A. 8 VDD Supply Voltage for Isolator Side,.7 V to 5.5 V. Rev. E Page 3 of

14 ADuM/ADuM TYPICAL PERFORMANCE CHARACTERISTICS 8 5 CURRENT/CHANNEL (ma) 6 5V 3V CURRENT (ma) 5 5V 3V 3 DATA RATE (Mbps) DATA RATE (Mbps) 6-9 Figure 6. Typical Input Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation Figure 9. Typical ADuM VDD Supply Current vs. Data Rate for 5 V and 3 V Operation 3 3 CURRENT/CHANNEL (ma) 5V 3V CURRENT (ma) 5V 3V 3 DATA RATE (Mbps) DATA RATE (Mbps) 6- Figure 7. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load) Figure. Typical ADuM VDD Supply Current vs. Data Rate for 5 V and 3 V Operation 3 8 CURRENT/CHANNEL (ma) 5V 3V CURRENT (ma) 6 5V 3V 3 DATA RATE (Mbps) DATA RATE (Mbps) 6- Figure 8. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (5 pf Output Load) Figure. Typical ADuM VDD or VDD Supply Current vs. Data Rate for 5 V and 3 V Operation Rev. E Page of

15 ADuM/ADuM APPLICATION INFORMATION PC BOARD LAYOUT The ADuMx digital isolators require no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins. The capacitor value should be between. μf and. μf. The total lead length between both ends of the capacitor and the input power supply pin should not exceed mm. PROPAGATION DELAY-RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic Low output can differ from the propagation delay to a Logic high output. INPUT (V Ix ) OUTPUT (V Ox ) t PLH t PHL 5% Figure. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved. Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADuMx component. Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuMx components operating under the same conditions. DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~ ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is therefore either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions of more than ~ μs at the input, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table and Table ) by the watchdog timer circuit. 5% 6- The ADuMx are extremely immune to external magnetic fields. The limitation on the magnetic field immunity of the ADuMx is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuMx is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than. V. The decoder has a sensing threshold at about.5 V, therefore establishing a.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = ( dβ/dt)σ rn ; n =,,, N where: β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuMx and an imposed requirement that the induced voltage be 5% at most of the.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 3. MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss)... k k k M M M MAGNETIC FIELD FREQUENCY (Hz) Figure 3. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of MHz, the maximum allowable magnetic field of. kgauss induces a voltage of.5 V at the receiving coil. This is about 5% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and has the worst-case polarity), it reduces the received pulse from >. V to.75 V still well above the.5 V sensing threshold of the decoder. 6-3 Rev. E Page 5 of

16 ADuM/ADuM The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuMx transformers. Figure expresses these allowable current magnitudes as a function of frequency for selected distances. As seen, the ADuMx are extremely immune and can be affected only by extremely large currents operated at high frequency and very close to the component. For the MHz example, one would have to place a.5 ka current 5 mm away from the ADuMx to affect the operation of the component. MAXIMUM ALLOWABLE CURRENT (ka). DISTANCE = mm DISTANCE = 5mm DISTANCE = m. k k k M M M MAGNETIC FIELD FREQUENCY (Hz) Figure. Maximum Allowable Current for Various Current-to-ADuMx Spacings Note that at combinations of strong magnetic fields and high frequencies, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the threshold of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. POWER CONSUMPTION The supply current at a given channel of the ADuMx isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel. For each input channel, the supply current is given by IDDI = IDDI (Q) f.5fr IDDI = IDDI (D) (f fr) + IDDI (Q) f >.5fr For each output channel, the supply current is given by IDDO = IDDO (Q) f.5fr IDDO = (IDDO (D) + (.5 3 ) CLVDDO) (f fr) + IDDO (Q) f >.5fr 6- where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (ma/mbps). CL is the output load capacitance (pf). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz, half of the input data rate, NRZ signaling). fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (ma). To calculate the total IDD and IDD supply current, the supply currents for each input and output channel corresponding to IDD and IDD are calculated and totaled. Figure 6 and Figure 7 provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 8 provides perchannel supply current as a function of data rate for a 5 pf output condition. Figure 9 through Figure provide total VDD and VDD supply current as a function of data rate for ADuM and ADuM channel configurations. INSULATION LIFETIME All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuMx. Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table summarize the peak voltage for 5 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than the 5-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. The insulation lifetime of the ADuMx depends on the voltage waveform type imposed across the isolation barrier. The icoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 5, Figure 6, and Figure 7 illustrate these different isolation voltage waveforms, respectively. Bipolar ac voltage is the most stringent environment. The goal of a 5-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage. Rev. E Page 6 of

17 ADuM/ADuM In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower, which allows operation at higher working voltages while still achieving a 5-year service life. The working voltages listed in Table can be applied while maintaining the 5-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross insulation voltage waveform that does not conform to Figure 6 or Figure 7 should be treated as a bipolar ac waveform and its peak voltage should be limited to the 5-year lifetime voltage value listed in Table. Note that the voltage presented in Figure 6 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross V. RATED PEAK VOLTAGE V Figure 5. Bipolar AC Waveform RATED PEAK VOLTAGE V Figure 6. Unipolar AC Waveform RATED PEAK VOLTAGE V Figure 7. DC Waveform Rev. E Page 7 of

18 ADuM/ADuM OUTLINE DIMENSIONS 5. (.968).8 (.89). (.57) 3.8 (.97) (.) 5.8 (.8).5 (.98). (.) COPLANARITY. SEATING PLANE.7 (.5) BSC.75 (.688).35 (.53).5 (.).3 (.) 8.5 (.98).7 (.67).5 (.96).5 (.99).7 (.5). (.57) 5 COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 8. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters (inches) 7-A ORDERING GUIDE Number of Inputs, VDD Side Number of Inputs, VDD Side Maximum Data Rate (Mbps) Maximum Propagation Delay, 5 V (ns) Maximum Pulse Width Distortion (ns) Model Temperature Range ( C) ADuMAR to +5 R-8 ADuMAR-RL7 to +5 R-8 ADuMARZ to +5 R-8 ADuMARZ-RL7 to +5 R-8 ADuMBR 5 3 to +5 R-8 ADuMBR-RL7 5 3 to +5 R-8 ADuMBRZ 5 3 to +5 R-8 ADuMBRZ-RL7 5 3 to +5 R-8 ADuMCR to +5 R-8 ADuMCR-RL to +5 R-8 ADuMCRZ to +5 R-8 ADuMCRZ-RL to +5 R-8 ADuMAR to +5 R-8 ADuMAR-RL7 to +5 R-8 ADuMARZ to +5 R-8 ADuMARZ-RL7 to +5 R-8 ADuMBR 5 3 to +5 R-8 ADuMBR-RL7 5 3 to +5 R-8 ADuMBRZ 5 3 to +5 R-8 ADuMBRZ-RL7 5 3 to +5 R-8 ADuMCR to +5 R-8 ADuMCR-RL to +5 R-8 ADuMCRZ to +5 R-8 ADuMCRZ-RL to +5 R-8 R-8 = 8-lead narrow body SOIC_N. Z = RoHS Compliant Part. Package Option Rev. E Page 8 of

19 ADuM/ADuM NOTES Rev. E Page 9 of

20 ADuM/ADuM NOTES 7 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D6--/7(E) Rev. E Page of