Integrated DC-to-DC Converter ADuM6010

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1 FEATURES isopower integrated, isolated dc-to-dc converter Regulated 3.5 V or 5.25 V output Up to 50 mw output power 20-lead SSOP package with 5 mm creepage High temperature operation: 05 C High common-mode transient immunity: >25 kv/μs Safety and regulatory approvals UL recognition (pending) 3750 V rms for minute per UL 577 CSA Component Acceptance Notice #5A (pending) VDE certificate of conformity (pending) DIN V VDE V (VDE V ): VIORM = 849 V peak APPLICATIONS Power supply start-up bias and gate drives Isolated sensor interfaces Industrial PLCs GENERAL DESCRIPTION The is an integrated, isolated dc-to-dc converter. Based on the Analog Devices, Inc., icoupler technology, the dc-to-dc converter provides regulated, isolated power, adjustable between 3.5 V and 5.25 V. Input supply voltages can range from slightly below the required output to significantly higher. Popular combination ant their associated power levels are shown in Table. The icoupler chip-scale transformer technology is used for isolated logic signals and for the magnetic components of the dc-to-dc converter. The result is a small form factor, total isolation solution. Integrated DC-to-DC Converter PDIS V DDP FUTIONAL BLOCK DIAGRAM 20 9 GND ISO GND ISO 5 GND ISO 4 PCS 3 V SEL.25V 2 V ISO OSC RECT REG GND ISO Figure. Table. Power Levels Input Voltage (V) Output Voltage (V) Output Power (mw) Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 906, Norwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagram... Revision History... 2 Specifications... 3 Electrical Characteristics 5 V Primary Input Supply/5 V Secondary Isolated Supply... 3 Electrical Characteristics 3.3 V Primary Input Supply/3.3 V Secondary Isolated Supply... 4 Electrical Characteristics 5 V Primary Input Supply/3.3 V Secondary Isolated Supply... 5 Package Characteristics... 6 Regulatory Approvals... 6 Insulation and Safety-Related Specifications... 6 Data Sheet DIN V VDE V (VDE V ) Insulation Characteristics...7 Recommended Operating Conditions...7 Absolute Maximum Ratings...8 ESD Caution...8 Pin Configurations and Function Descriptions...9 Truth Table... 0 Typical Performance Characteristics... Applications Information... 3 PCB Layout... 3 Thermal Analysis... 3 EMI Considerations... 4 Insulation Lifetime... 4 Outline Dimensions... 5 Ordering Guide... 5 REVISION HISTORY 0/2 Revision 0: Initial Version Rev. 0 Page 2 of 5

3 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY All typical specifications are at TA = 25 C, VDDP = VISO = 5 V, VSEL resistor network: R = 0 kω, R2 = 30 kω. Minimum/maximum specifications apply over the entire recommended operation range which is 4.5 V VDDP, VSEL, VISO 5.5 V, and 40 C TA +05 C, unless otherwise noted. Switching specifications are tested with CL = 5 pf and CMOS signal levels, unless otherwise noted. Table 2. DC-to-DC Converter Static Specifications Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC-TO-DC CONVERTER SUPPLY Setpoint VISO V IISO = 5 ma, R = 0 kω, R2 = 30 kω Line Regulation VISO (LINE) 20 mv/v IISO = 5 ma, VDD = 4.5 V to 5.5 V Load Regulation VISO (LOAD) 5 % IISO = 3 ma to 27 ma Output Ripple VISO (RIP) 75 mv p-p 20 MHz bandwidth, CBO = 0. μf 0 μf, IISO = 27 ma Output Noise VISO (NOISE) 200 mv p-p CBO = 0. μf 0 μf, IISO = 27 ma Switching Frequency fosc TBD MHz Pulse Width Modulation Frequency fpwm TBD khz Output Supply IISO (MAX) 29 ma VISO > 4.5 V Efficiency at IISO (MAX) 29 % IISO = 27 ma IDDP, No VISO Load IDD (Q) ma IDDP, Full VISO Load IDD (MAX) 95 ma Thermal Shutdown Shutdown Temperature 54 C Thermal Hysteresis 0 C Table 3. Input and Output Characteristics Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Logic High Input Threshold VIH 0.7 VISO or 0.7 VDDP V Logic Low Input Threshold VIL 0.3 VISO or 0.3 VDDP V Undervoltage Lockout VISO, VDDP supply Positive Going Threshold VUV+ 2.7 V Negative Going Threshold VUV 2.4 V Hysteresis VUVH 0.3 V Input Currents per Channel IPDIS μa 0 V VPDIS VDDP Rev. 0 Page 3 of 5

4 Data Sheet ELECTRICAL CHARACTERISTICS 3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY All typical specifications are at TA = 25 C, VDDP = VISO = 3.3 V, VSEL resistor network: R = 0 kω, R2 = 6.2 kω. Minimum/maximum specifications apply over the entire recommended operation range which is 3.0 V VDDP, VSEL, VISO 3.6 V, and 40 C TA +05 C, unless otherwise noted. Switching specifications are tested with CL = 5 pf and CMOS signal levels, unless otherwise noted. Table 4. DC-to-DC Converter Static Specifications Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC-TO-DC CONVERTER SUPPLY Setpoint VISO V IISO = 5 ma, R = 0 kω, R2 = 6.2 kω Line Regulation VISO (LINE) 20 mv/v IISO = 5 ma, VDD = 3.0 V to 3.6 V Load Regulation VISO (LOAD) 5 % IISO = 3 ma to 27 ma Output Ripple VISO (RIP) 50 mv p-p 20 MHz bandwidth, CBO = 0. μf 0 μf, IISO = 8 ma Output Noise VISO (NOISE) 30 mv p-p CBO = 0. μf 0 μf, IISO = 8 ma Switching Frequency fosc TBD MHz Pulse Width Modulation Frequency fpwm TBD khz Output Supply IISO (MAX) 20 ma 3.6 V >VISO > 3 V Efficiency at IISO (MAX) 27 % IISO = 8 ma IDD, No VISO Load IDD (Q) 4 7 ma IDD, Full VISO Load IDD (MAX) 99 ma Thermal Shutdown Shutdown Temperature 54 C Thermal Hysteresis 0 C Thermal Shutdown Shutdown Temperature 54 C Thermal Hysteresis 0 C Table 5. Input and Output Characteristics Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Logic High Input Threshold VIH 0.7 VISO or 0.7 VDDP V Logic Low Input Threshold VIL 0.3 VISO or 0.3 VDDP V Undervoltage Lockout VDDP supply Positive Going Threshold VUV+ 2.7 V Negative Going Threshold VUV 2.4 V Hysteresis VUVH 0.3 V Input Currents per Channel IPDIS μa 0 V VPDIS VDDP Rev. 0 Page 4 of 5

5 ELECTRICAL CHARACTERISTICS 5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY All typical specifications are at TA = 25 C, VDDP = 5.0 V, VISO = 3.3 V, VSEL resistor network: R = 0 kω, R2 = 6.2 kω. Minimum/maximum specifications apply over the entire recommended operation range which is 4.5 V VDDP 5.5 V, 3.0 V VISO 3.6 V, and 40 C TA +05 C, unless otherwise noted. Switching specifications are tested with CL = 5 pf and CMOS signal levels, unless otherwise noted. Table 6. DC-to-DC Converter Static Specifications Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC-TO-DC CONVERTER SUPPLY Setpoint VISO V IISO = 5 ma, R = 0 kω, R2 = 6.2 kω Line Regulation VISO (LINE) 20 mv/v IISO = 5 ma, VDD = 4.5 V to 5.5 V Load Regulation VISO (LOAD) 5 % IISO = 3 ma to 27 ma Output Ripple VISO (RIP) 50 mv p-p 20 MHz bandwidth, CBO = 0. μf 0 μf, IISO = 27 ma Output Noise VISO (NOISE) 30 mv p-p CBO = 0. μf 0 μf, IISO = 27 ma Switching Frequency fosc TBD MHz Pulse Width Modulation Frequency fpwm TBD khz Output Supply IISO (MAX) 30 ma 3.6 V > VISO > 3 V Efficiency at IISO (MAX) 24 % IISO = 27 ma IDD, No VISO Load IDD (Q) ma IDD, Full VISO Load IDD (MAX) 7 ma Thermal Shutdown Shutdown Temperature 54 C Thermal Hysteresis 0 C Table 7. Input and Output Characteristics Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC SPECIFICATIONS Logic High Input Threshold VIH 0.7 VISO or 0.7 VDDP V Logic Low Input Threshold VIL 0.3 VISO or 0.3 VDDP V Undervoltage Lockout VISO, VDDP supply Positive Going Threshold VUV+ 2.7 V Negative Going Threshold VUV 2.4 V Hysteresis VUVH 0.3 V Input Currents per Channel IPDIS μa 0 V VPDIS VDDP Rev. 0 Page 5 of 5

6 Data Sheet PACKAGE CHARACTERISTICS Table 8. Thermal and Isolation Characteristics Parameter Symbol Min Typ Max Unit Test Conditions/Comments Resistance (Input to Output) RI-O 0 2 Ω Capacitance (Input to Output) CI-O 2.2 pf f = MHz Input Capacitance 2 CI 4.0 pf IC Junction-to-Ambient Thermal Resistance θja 83 C/W Thermocouple located at center of package underside, test conducted on 4-layer board with thin traces 3 The device is considered a 2-terminal device: Pin to Pin 0 are shorted together; and Pin to Pin 20 are shorted together. 2 Input capacitance is from any input data pin to ground. 3 See the Thermal Analysis section for thermal model definitions. REGULATORY APPROVALS Table 9. UL (Pending) CSA (Pending) VDE (Pending) 2 Recognized under 577 component recognition program Approved under CSA Component Acceptance Notice #5A Certified according to DIN V VDE V (VDE V ): Single protection, 3750 V rms isolation voltage Reinforced insulation per CSA and IEC , 360 V rms (509 V peak) maximum working voltage Reinforced insulation, 849 V peak File E2400 File File In accordance with UL 577, each is proof tested by applying an insulation test voltage 3000 V rms for second (current leakage detection limit = 0 μa). 2 In accordance with DIN V VDE V , each is proof tested by applying an insulation test voltage 590 V peak for second (partial discharge detection limit = 5 pc). The * marking branded on the component designates DIN V VDE V approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 0. Critical Safety-Related Dimensions and Material Properties Parameter Symbol Value Unit Test Conditions/Comments Rated Dielectric Insulation Voltage 3750 V rms -minute duration Minimum External Air Gap (Clearance) L(I0) 5. mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 5. mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.07 min mm Distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 2/VDE 0303, Part Isolation Group II Material group (DIN VDE 00, /89, Table ) Rev. 0 Page 6 of 5

7 DIN V VDE V (VDE V ) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by the protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V approval. Table. VDE Characteristics Description Test Conditions/Comments Symbol Characteristic Unit Installation Classification per DIN VDE 00 For Rated Mains Voltage 50 V rms I to IV For Rated Mains Voltage 300 V rms I to IV For Rated Mains Voltage 400 V rms I to III Climatic Classification 40/05/2 Pollution Degree per DIN VDE 00, Table 2 Maximum Working Insulation Voltage VIORM 849 V peak Input-to-Output Test Voltage, Method b VIORM.875 = Vpd(m), 00% production test, tini = tm = sec, partial discharge < 5 pc Vpd(m) 592 V peak Input-to-Output Test Voltage, Method a After Environmental Tests Subgroup VIORM.5 = Vpd(m), tini = 60 sec, Vpd(m) 273 V peak tm = 0 sec, partial discharge < 5 pc After Input and/or Safety Test Subgroup 2 VIORM.2 = Vpd(m), tini = 60 sec, Vpd(m) 08 V peak and Subgroup 3 tm = 0 sec, partial discharge < 5 pc Highest Allowable Overvoltage VIOTM 5300 V peak Withstand Isolation Voltage minute withstand rating VISO 3750 V rms Surge Isolation Voltage VPEAK = 0 kv,.2 μs rise time, 50 μs, 50% fall time VIOSM 6000 V peak Safety Limiting Values Maximum value allowed in the event of a failure (see Figure 2) Case Temperature TS 50 C Total Power Dissipation at 25 C IS 2.5 W Insulation Resistance at TS VIO = 500 V RS >0 9 Ω SAFE LIMITING POWER (W) AMBIENT TEMPERATURE ( C) Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN RECOMMENDED OPERATING CONDITIONS Table 2. Parameter Symbol Min Max Unit Operating Temperature TA C Supply Voltages 2 VDD at VSEL = 0 V VDD V VDD at VSEL = VISO V Operation at 05 C requires reduction of the maximum load current as specified in Table 3. 2 Each voltage is relative to its respective ground Rev. 0 Page 7 of 5

8 ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25 C, unless otherwise noted. Table 3. Parameter Storage Temperature (TST) Ambient Operating Temperature (TA) Supply Voltages (VDDP, VISO) VISO Supply Current 2 TA = 40 C to +05 C Input Voltage (PDIS, VSEL), 3 Common-Mode Transients 4 Rating 55 C to +50 C 40 C to +05 C 0.5 V to +7.0 V 30 ma 0.5 V to VDDI V 00 kv/μs to +00 kv/μs All voltages are relative to their respective ground. 2 The VISO provides current for dc and dynamic loads on the VISO I/O channels. This current must be included when determining the total VISO supply current. See Figure 2 for the maximum rated current values for various temperatures. 3 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the Applications Information section. 4 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. Data Sheet Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime Applicable Parameter Max Unit Certification AC Voltage Bipolar Waveform 360 V peak All certifications, 50-year operation Unipolar Waveform 560 V peak Working voltage per IEC DC Voltage DC Peak Voltage 560 V peak Working voltage per IEC Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information. ESD CAUTION Rev. 0 Page 8 of 5

9 PIN CONFIGURATION AND FUTION DESCRIPTIONS PDIS V DDP GND ISO GND ISO TOP VIEW 6 (Not to Scale) 5 GND ISO V SEL 9 2 V ISO 0 GND ISO NOTES. PINS LABELED CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THESE PINS TO GROUND. AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT. Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description, 3, 4, 7, 4, This pin is not connected internally (see Figure 3). 7, 8, 20 2, 5, 6, 0 GNDP Ground. Ground reference for isolator primary. Pin 2 and Pin 0 are internally connected, and it is recommended that both pins be connected to a common ground. 8 PDIS Power Disable. When this pin is tied to GNDP the power converter is active; when a logic high voltage is applied, the power supply enters a low power standby mode. 9 VDDP Primary Supply Voltage, 3.0 V to 5.5 V., 5, 6,9 GNDISO Ground Reference for Isolator Side 2. Pin 9 and Pin are internally connected, and it is recommended that both pins be connected to a common ground. 2 VISO Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL low) or 5.0 V (VSEL high). 3 VSEL Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V. Rev. 0 Page 9 of 5

10 Data Sheet TRUTH TABLE Table 6. Truth Table (Positive Logic) VDDP (V) VSEL Input PDIS Input VISO Output (V) Notes 5 R = 30 kω, R2 = 0 kω Low 5 5 R = 30 kω, R2 = 0 kω High R = 25 kω, R2 = 5 kω Low R = 25 kω, R2 = 5 kω High 0 5 R = 25 kω, R2 = 5 kω Low R = 25 kω, R2 = 5 kω High R = 30 kω, R2 = 0 kω Low 5 Configuration not recommended 3.3 R = 30 kω, R2 = 0 kω High 0 Rev. 0 Page 0 of 5

11 TYPICAL PERFORMAE CHARACTERISTICS EFFICIEY (%) V/5V 5V/3.3V 3.3V/3.3V POWER DISSIPATION (W) I IN P IN I DDP CURRENT (A) LOAD CURRENT (A) Figure 4. Typical Power Supply Efficiency at 5 V/5 V, 5 V/3.3 V, and 3.3 V/3.3 V VDD INPUT VOLTAGE (V) Figure 7. Typical Short-Circuit Input Current and Power vs. VDD Supply Voltage POWER DISSIPATION (W) VDD = 5V/V ISO = 5V VDD = 5V/V ISO = 3.3V VDD = 3.3V/V ISO = 3.3V V ISO (00mV/DIV) 90% LOAD I ISO (A) Figure 5. Typical Total Power Dissipation vs. IISO with Data Channels Idle % LOAD (ms/div) Figure 8. Typical VISO Transient Load Response, 5 V Input, 5 V Output, 0% to 90% Load Step VDD = 5V/V ISO = 5V VDD = 5V/V ISO = 3.3V VDD = 3.3V/V ISO = 3.3V V ISO (00mV/DIV) I DD (A) % LOAD V ISO (ma) Figure 6. Typical Isolated Output Supply Current, IISO, as a Function of External Load, No Dynamic Current Draw at 5 V/5 V, 5 V/3.3 V, and 3.3 V/3.3 V % LOAD (ms/div) Figure 9. Typical Transient Load Response, 3.3 V input 3.3 V Output, 0% to 90% Load Step Rev. 0 Page of 5

12 Data Sheet V ISO (00mV/DIV) 90% LOAD V ISO (V) % LOAD (ms/div) TIME (µs) Figure 0. Typical Transient Load Response, 5 V Input, 3.3 V Output, 0% to 90% Load Step Figure 2. Typical VISO = 3.3 V Output Voltage Ripple at 90% Load V ISO (V) TIME (µs) Figure. Typical VISO = 5 V Output Voltage Ripple at 90% Load Rev. 0 Page 2 of 5

13 APPLICATIONS INFORMATION The dc-to-dc converter section of the works on principles that are common to most modern power supplies. It has split controller architecture with isolated pulse-width modulation (PWM) feedback. VDDP power is supplied to an oscillating circuit that switches current into a chip-scale air core transformer. Power transferred to the secondary side is rectified and regulated to a value between 3.5 V and 5.25 V depending on the set-point supplied by an external voltage divider (see Equation ). The secondary (VISO) side controller regulates the output by creating a PWM control signal that is sent to the primary (VDDP) side by a dedicated icoupler data channel. The PWM modulates the oscillator circuit to control the power being sent to the secondary side. Feedback allows for significantly higher power and efficiency. ( R R2) V ISO.25 V () R where: R is a resistor between VSEL and GNDISO. R2 is a resistor between VSEL and VISO. The implements undervoltage lockout (UVLO) with hysteresis on the VISO and VDDP power inputs. This feature ensures that the converter does not go into oscillation due to noisy input power or slow power-on ramp rates. PCB LAYOUT The digital isolator with 0.5 W isopower integrated dc-to-dc converter requires no external interface circuitry for the logic interfaces. Power supply bypass with a low ESR capacitor is required, as close to the chip pads as possible. The isopower inputs require several passive components to bypass the power effectively as well as set the output voltage and bypass the core voltage regulator (see Figure 3 through Figure 5). + 0µF 0.µF PDIS 8 V DDP 9 0 Figure 3. VDDP Bias and Bypass Components V SEL 3 30kΩ V ISO 2 GND ISO + 0.µF 0kΩ 0µF Figure 4. VISO Bias and Bypass Components The power supply section of the uses a? MHz oscillator frequency to efficiently pass power through its chipscale transformers. Bypass capacitors are required for several operating frequencies. Noise suppression requires a low inductance, high frequency capacitor; ripple suppression and proper regulation require a large value capacitor. These are most conveniently connected between Pin 9 and Pin 0 for VDDP and between Pin and Pin 2 for VISO. To suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. The recommended capacitor values are 0. μf and 0 μf for VDD. The smaller capacitor must have a low ESR; for example, use of an NPO or X5R ceramic capacitor is advised. An additional 0 nf capacitor can be added in parallel if further EMI reduction is required. Note that the total lead length between the ends of the low ESR capacitor and the input power supply pin must not exceed 2 mm. Installing the bypass capacitor with traces more than 2 mm in length may result in data corruption. A 0. μf bypass between Pin and Pin 2 and between Pin 9 and Pin 20 is required for proper operation of the data channels. PDIS V DDP BYPASS < 2mm Figure 5. Recommended PCB Layout GND ISO V SEL VISO GND ISO In applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. Furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins, exceeding the absolute maximum ratings specified in Table 3, thereby leading to latch-up and/or permanent damage. THERMAL ANALYSIS The consist of four internal die attached to a split lead frame with two die attach paddles. For the purposes of thermal analysis, the die is treated as a thermal unit, with the highest junction temperature reflected in the θja from Table 8. The value of θja is based on measurements taken with the parts mounted on a JEDEC standard, 4-layer board with fine width traces and still air. Under normal operating conditions, the can operate at full load across the full temperature range without derating the output current Rev. 0 Page 3 of 5

14 EMI CONSIDERATIONS The dc-to-dc converter section of the components must, of necessity, operate at a very high frequency to allow efficient power transfer through the small transformers. This creates high frequency currents that can propagate in circuit board ground and power planes, causing edge and dipole radiation. Grounded enclosures are recommended for applications that use these devices. If grounded enclosures are not possible, follow good RF design practices in the layout of the PCB. See the AN-097 Application Note at for the most current PCB layout recommendations for the. INSULATION LIFETIME All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. Analog Devices conducts an extensive set of evaluations to determine the lifetime of the insulation structure within the. Accelerated life testing is performed using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined, allowing calculation of the time to failure at the working voltage of interest. The values shown in Table 4 summarize the peak voltages for 50 years of service life in several operating conditions. In many cases, the working voltage approved by agency testing is higher than the 50-year service life voltage. Operation at working voltages higher than the service life voltage listed leads to premature insulation failure. The insulation lifetime of the depends on the voltage waveform type imposed across the isolation barrier. The icoupler insulation structure degrades at different rates, depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 6, Data Sheet Figure 7, and Figure 8 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. A 50-year operating lifetime under the bipolar ac condition determines the Analog Devices recommended maximum working voltage. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 4 can be applied while maintaining the 50-year minimum lifetime, provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross-insulation voltage waveform that does not conform to Figure 7 or Figure 8 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 4. RATED PEAK VOLTAGE 0V 0V Figure 6. Bipolar AC Waveform RATED PEAK VOLTAGE Figure 7. DC Waveform RATED PEAK VOLTAGE 0V NOTES. THE VOLTAGE IS SHOWN AS SINU SOIDAL FOR ILLUSTRATION PUPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE WAVEFORM VARYING BETWEEN 0V AND SOME LIMITING VALUE. THE LIMITING VALUE CAN BE POSITIVE OR NEGATIVE, BUT THE VOLTAGE CANNOT CROSS 0V. Figure 8. Unipolar AC Waveform Rev. 0 Page 4 of 5

15 OUTLINE DIMENSIONS MAX MIN COPLANARITY BSC SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-50-AE A Figure Lead Shrink Small Outline Package [SSOP] (RS-20) Dimensions shown in millimeters ORDERING GUIDE Model, 2 Temperature Range Package Description Package Option ARSZ 40 C to +05 C 20-Lead SSOP RS-20 ARSZ-RL7 40 C to +05 C 20-Lead SSOP RS-20 Tape and reel are available. The addition of an RL suffix designates a 7 tape and reel option. 2 Z = RoHS Compliant Part. 202 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /2(0) Rev. 0 Page 5 of 5

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