2Pai Semi. π130/π131/π132. Enhanced ESD, 3.0 kv rms/6.0 kv rms Triple-Channel Digital Isolators. Data Sheet

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1 FEATURES Ultra low power consumption: 0.5mA/Ch High data rate: Pai Semi πxaxx: 600Mbps πxexx: 00Mbps πxmxx: 0Mbps πxuxx: 50kbps High common-mode transient immunity: 00 kv/µs typical High robustness to radiated and conducted noise Low propagation delay: 7.5 ns maximum for 5 V operation 9.0 ns maximum for. V operation Isolation voltages: πxx: AC 000Vrms πxx6: AC 6000Vrms High ESD rating: ESDA/JEDEC JS Human body model (HBM) ±8kV, all pins Safety and regulatory approvals (Pending) UL recognition(ongoing): 000Vrms/6000Vrms for minute per UL 577 CSA Component Acceptance Notice 5A VDE certificate number: DIN V VDE V (VDE V 088-0):006- V IORM = 565V peak/89v peak CQC certification per GB V to 5.5 V level translation AEC-Q00 qualification Wide temperature range: -0 C to 5 C 6-lead, RoHS-compliant, (W)SOIC package APPLICATIONS General-purpose multichannel isolation Industrial field bus isolation GENERAL DESCRIPTION The πxxx are PaiSemi digital isolators product family. By using maturated standard semiconductor CMOS technology and innovative design, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices and other integrated isolators. The πxxx isolator data channels are independent and are available in a variety of configurations with a withstand voltage rating of.0 kv rms to 6.0 kv rms and the data rate from DC up to 600Mbps (see the Ordering Guide). Enhanced ESD,.0 kv rms/6.0 kv rms Triple-Channel Digital Isolators FUTIONAL BLOCK DIAGRAMS VDD GND VIA VIB VIC GND VDD GND VIA VIB VOC GND VDD GND VOA VIB VIC GND π0 π π 6 5 GND GND VDD VOA VOB VOC GND VDD VOA VOB VIC GND 5 GND 0 9 VDD VIA VOB VOC GND Figure. functional Block Diagram The devices operate with the supply voltage on either side ranging from.0 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. The fail-safe state is available in which the outputs transition to a preset state when the input power supply is not applied. VIN_A VIN_B VIN_C VDD CIN 0.uF GND VDD GND VIA VIB 5 VIC GND π0 6 VDD 5 GND VOA VOB VOC 0 GND 9 GND VDD Figure. π0 typical Application Circuit COUT 0.uF VOUT_A VOUT_B VOUT_C Rev.0 Information furnished by Pai semi is believed to be accurate and reliable. However, no responsibility is assumed by Pai semi for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Pai semi. Trademarks and registered trademarks are the property of their respective owners. Room 907, Building 8, No.98, GuoShouJing Road, Pudong New District, Shanghai, 00, China Pai Semiconductor Co., Limited. All rights reserved.

2 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 5 V OPERATION All typical specifications are at TA = 5 C, VDD = VDD = 5 V. Minimum/maximum specifications apply over the entire recommended operation range of.5 V VDD 5.5 V,.5 V VDD 5.5 V, and 0 C TA +5 C, unless otherwise noted. Switching specifications are tested with CL = 5 pf and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals and CL = 0 pf. Table. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS πxa Pulse Width PW.6 ns Within pulse width distortion (PWD) limit Max Data Rate 600 Mbps Within PWD limit πxm Pulse Width PW 00 ns Within pulse width distortion (PWD) limit Max Data Rate 0 Mbps Within PWD limit πxu Pulse Width PW 6.6 μs Within pulse width distortion (PWD) limit Max Data Rate 50 Kbps Within PWD limit Propagation Delay tphl, tplh ns 50% input to 50% output Pulse Width Distortion PWD ns tplh tphl Change vs. Temperature.5 ps/ C Propagation Delay Skew tpsk 0.5 ns Between any two units at the same temperature, voltage, and load Channel Matching Codirectional tpskcd 0 0. ns Opposing Direction tpskod 0 0. ns Jitter 50 ps p-p See the Jitter Measurement section 8 ps rms See the Jitter Measurement section DC SPECIFICATIONS Input Threshold Voltage Logic High V IH.6 V Logic Low V IL. V Output Voltage Logic High VOH V DDx 0. V DDx V I Ox = 0 µa, V Ix = V IxH V DDx 0. V DDx V I Ox = ma, V Ix = V IxH Logic Low VOL V I Ox = 0 µa, V Ix = V IxL V I Ox = ma, V Ix = V IxL Input Current per Channel I I µa 0 V V Ix V DDx Quiescent Supply Current CL = 0 pf π0 IDD (Q) µa V I = 0 (N0), (N) 5 IDD (Q) µa V I = 0 (N0), (N) 5 IDD (Q) µa V I = (N0), 0 (N) 5 IDD (Q) µa V I = (N0), 0 (N) 5 Rev. A Page of

3 Parameter Symbol Min Typ Max Unit Test Conditions/Comments π IDD (Q) µa V I = 0 (N0), (N) 5 IDD (Q) 80 5 µa V I = 0 (N0), (N) 5 IDD (Q) µa V I = (N0), 0 (N) 5 IDD (Q) µa V I = (N0), 0 (N) 5 π IDD (Q) µa V I = 0 (N0), (N) 5 IDD (Q) 80 5 µa V I = 0 (N0), (N) 5 IDD (Q) µa V I = (N0), 0 (N) 5 IDD (Q) µa V I = (N0), 0 (N) 5 Dynamic Supply Current Dynamic Input IDDI (D) µa /Mbps CL = 0 pf Inputs switching, 50% duty cycle Dynamic Output IDDO (D) 7 µa /Mbps Inputs switching, 50% duty cycle Under voltage Lockout UVLO Positive V DDx Threshold VDDxUV V Negative V DDx Threshold VDDxUV V V DDx Hysteresis VDDxUVH V AC SPECIFICATIONS Output Rise/Fall Time t R/t F 0.7 ns 0% to 90% Common-Mode Transient Immunity 6 CM H 5 kv/µs V Ix = V DDx, V CM = 000 V, transient magnitude = 800 V CM L 5 kv/µs V Ix = 0 V, V CM = 000 V, transient magnitude = 800 V Notes: IOx is the Channel x output current, where x = A, B or C. VIxH is the input side logic high voltage. VIxL is the input side logic low voltage. VI is the input voltage. 5 N0 is the π0xx0/πxx0/πxx0 models, and N is the π0xx/πxx/πxx models. See the Ordering Guide. 6 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output VO > 0.8 VDDx. CML is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Table. Total Supply Current vs. Data Throughput (CL = 0 pf) 50 Kbps 0 Mbps 50 Mbps Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit SUPPLY CURRENT π0a Supply Current Side IDD ma Supply Current Side IDD ma πa Supply Current Side IDD ma Supply Current Side IDD ma πa Supply Current Side IDD ma Supply Current Side IDD ma Rev. A Page of

4 50 Kbps 0 Mbps Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit SUPPLY CURRENT π0m Supply Current Side IDD ma Supply Current Side IDD ma πm Supply Current Side IDD ma Supply Current Side IDD ma πm Supply Current Side IDD ma Supply Current Side IDD ma SUPPLY CURRENT π0u Supply Current Side IDD ma Supply Current Side IDD ma πu Supply Current Side IDD ma Supply Current Side IDD ma πu Supply Current Side IDD ma Supply Current Side IDD ma Rev. A Page of

5 ELECTRICAL CHARACTERISTICS. V OPERATION. All typical specifications are at TA = 5 C, VDD = VDD =. V. Minimum/maximum specifications apply over the entire recommended operation range:.0 V VDD.6 V,.0 V VDD.6 V, and 0 C TA +5 C, unless otherwise noted. Switching specifications are tested with CL = 5 pf and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals and CL = 0 pf. Table. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS πxa Pulse Width PW.6 ns Within pulse width distortion (PWD) limit Max Data Rate 600 Mbps Within PWD limit πxm Pulse Width PW 00 ns Within pulse width distortion (PWD) limit Max Data Rate 0 Mbps Within PWD limit πxu Pulse Width PW 6.6 μs Within pulse width distortion (PWD) limit Max Data Rate 50 Kbps Within PWD limit Propagation Delay tphl, tplh.. 5. ns 50% input to 50% output Pulse Width Distortion PWD ns tplh tphl Change vs. Temperature.5 ps/ C Propagation Delay Skew tpsk 0.5 ns Between any two units at the same Channel Matching Codirectional tpskcd 0 0. ns temperature, voltage, and load Opposing Direction tpskod 0 0. ns Jitter 66 ps p-p See the Jitter Measurement section DC SPECIFICATIONS Input Threshold Voltage Logic High V IH. V Logic Low V IL 0.9 V ps rms See the Jitter Measurement section Output Voltage Logic High VOH V DDx 0. VDDx V I Ox = 0 µa, V Ix = V IxH V DDx 0. V DDx V I Ox = ma, VIx = V IxH Logic Low VOL V I Ox = 0 µa, V Ix = V IxL V I Ox = ma, VIx = V IxL Input Current per Channel I I µa 0 V V Ix V DDx Quiescent Supply Current π0 IDD (Q) µa CL = 0 pf V I = 0 (N0), (N) 5 IDD (Q) µa V I = 0 (N0), (N) 5 IDD (Q) µa V I = (N0), 0 (N) 5 IDD (Q) µa V I = (N0), 0 (N) 5 Rev. A Page 5 of

6 Parameter Symbol Min Typ Max Unit Test Conditions/Comments π IDD (Q) 7 µa V I = 0 (N0), (N) 5 IDD (Q) µa V I = 0 (N0), (N) 5 IDD (Q) µa V I = (N0), 0 (N) 5 IDD (Q) µa V I = (N0), 0 (N) 5 π IDD (Q) 7 µa V I = 0 (N0), (N) 5 IDD (Q) µa V I = 0 (N0), (N) 5 IDD (Q) µa V I = (N0), 0 (N) 5 IDD (Q) µa V I = (N0), 0 (N) 5 Dynamic Supply Current CL = 0 pf Dynamic Input IDDI (D) µa /Mbps Inputs switching, 50% duty cycle Dynamic Output IDDO (D) 5 6 µa /Mbps Inputs switching, 50% duty cycle Undervoltage Lockout UVLO Positive V DDx Threshold VDDxUV V Negative V DDx Threshold VDDxUV V V DDx Hysteresis VDDxUVH V AC SPECIFICATIONS Output Rise/Fall Time t R/t F 0.7 ns 0% to 90% Common-Mode Transient Immunity 6 CM H 5 kv/µs V Ix = V DDx, V CM = 000 V, transient magnitude = 800 V CM L 5 kv/µs V Ix = 0 V, V CM = 000 V, transient magnitude = 800 V Notes: IOx is the Channel x output current, where x = A, B or C. VIxH is the input side logic high voltage. VIxL is the input side logic low voltage. VI is the input voltage. 5 N0 is the π0xx0/πxx0/πxx0 models, and N is the π0xx/πxx/πxx models. See the Ordering Guide. 6 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDx. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Table. Total Supply Current vs. Data Throughput (CL = 0 pf) 50 Kbps 0 Mbps 50 Mbps Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit SUPPLY CURRENT π0a Supply Current Side IDD ma Supply Current Side IDD ma πa Supply Current Side IDD ma Supply Current Side IDD ma πa Supply Current Side IDD ma Supply Current Side IDD ma Rev. A Page 6 of

7 50 Kbps 0 Mbps Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit SUPPLY CURRENT π0m Supply Current Side IDD ma Supply Current Side IDD ma πm Supply Current Side IDD ma Supply Current Side IDD ma πm Supply Current Side IDD ma Supply Current Side IDD ma SUPPLY CURRENT π0u Supply Current Side IDD 0.08 ma Supply Current Side IDD 0.6 ma πu Supply Current Side IDD 0.5 ma Supply Current Side IDD 0.5 ma πu Supply Current Side IDD 0.5 ma Supply Current Side IDD 0.5 ma INSULATION AND SAFETY RELATED SPECIFICATIONS Table 5. πxx Parameter Symbol Value Unit Test Conditions/Comments Rated Dielectric Insulation Voltage 000 V rms -minute duration Minimum External Air Gap (Clearance) L (I0).0 mm min Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L (I0).0 mm min Measured from input terminals to output terminals, shortest distance path along body Minimum Clearance in the Plane of the Printed Circuit Board (PCB Clearance) L (PCB).5 mm min Measured from input terminals to output terminals, shortest distance through air, line of sight, in the PCB mounting plane Minimum Internal Gap (Internal Clearance) 8 µm min Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >00 V DIN IEC /VDE 00 Part Material Group II Material Group (DIN VDE 00, /89, Table ) Rev. A Page 7 of

8 πxx6 Parameter Symbol Value Unit Test Conditions/Comments Rated Dielectric Insulation Voltage 6000 V rms -minute duration Minimum External Air Gap (Clearance) L (I0) 8. mm min Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L (I0) 8. mm min Measured from input terminals to output terminals, shortest distance path along body Minimum Clearance in the Plane of the Printed Circuit Board (PCB Clearance) L (PCB) 8. mm min Measured from input terminals to output terminals, shortest distance through air, line of sight, in the PCB mounting plane Minimum Internal Gap (Internal Clearance) µm min Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >00 V DIN IEC /VDE 00 Part Material Group II Material Group (DIN VDE 00, /89, Table ) PACKAGE CHARACTERISTICS Table 6. πxx Parameter Symbol Min Typ Max Unit Test Conditions/Comments Resistance (Input to Output) RI-O 0 Ω Capacitance (Input to Output) CI-O 0.6 pf f = 00Hz Input Capacitance C I.0 pf IC Junction to Ambient Thermal Resistance θja 76 C/W Thermocouple located at center of package underside Notes: The device is considered a -terminal device: Pin through Pin 8 are shorted together, and Pin 9 through Pin 6 are shorted together. Input capacitance is from any input data pin to ground. πxx6 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Resistance (Input to Output) RI-O 0 Ω Capacitance (Input to Output) CI-O 0.6 pf f = 00Hz Input Capacitance C I.0 pf IC Junction to Ambient Thermal Resistance θja 5 C/W Thermocouple located at center of package underside Notes: The device is considered a -terminal device: Pin through Pin 8 are shorted together, and Pin 9 through Pin 6 are shorted together. Input capacitance is from any input data pin to ground. REGULATORY INFORMATION See Table 0 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross isolation waveforms and insulation levels. Table7. πxx UL (Pending) CSA (Pending) VDE (Pending) CQC (Pending) Recognized under UL 577 Component Recognition Program Approved under CSA Component Acceptance Notice 5A DIN V VDE V (VDE V 088-0):006- Certified under CQC-75-0 Rev. A Page 8 of

9 Single Protection, 000 V rms Isolation Voltage CSA A+A and IEC , second edition, +A+A: Basic insulation at 00 V rms (565 V peak) Reinforced insulation at 00 V rms (8 V peak) IEC Edition.: Basic insulation ( MOPP), 50 V rms (5 V peak) CSA and IEC 600- third edition Basic insulation at 00 V rms mains, 00 V rms (565 V peak) Reinforced insulation at 00 V rms mains, 00 V secondary (8 V peak) Basic insulation, V IORM = 565 V peak, V IOSM = 65 V peak GB9.-0 File (pending) File (pending) File (pending) File (pending) Basic insulation at 770 V rms (089 V peak) working voltage Reinforced insulation at 85 V rms (55 V peak) Notes: In accordance with UL 577, each π0x/πx/πx is proof tested by applying an insulation test voltage 800 V rms for sec. In accordance with DIN V VDE V 088-0, each π0x/πx/πx is proof tested by applying an insulation test voltage 059 V peak for sec (partial discharge detection limit = 5 pc). The * marking branded on the component designates DIN V VDE V approval. πxx6 UL (Pending) CSA (Pending) VDE (Pending) CQC (Pending) Recognized under UL 577 Component Recognition Program Single Protection, 6000 V rms Isolation Voltage Approved under CSA Component Acceptance Notice 5A CSA A+A and IEC , second edition, +A+A: Basic insulation at 80 V rms (7 V peak) Reinforced insulation at 5 V rms (587 V peak) IEC Edition.: Basic insulation ( MOPP), 6 V rms (69 V peak) CSA and IEC 600- third edition Basic insulation at 00 V rms mains, 80 V rms (7 V peak) Reinforced insulation at 00 V rms mains, 00 V secondary (8 V peak) DIN V VDE V (VDE V 088-0):006- Basic insulation, V IORM = 89 V peak, V IOSM = 769 V peak Reinforced insulation, V IORM =89 V peak, V IOSM = 0 kv peak Certified under CQC-75-0 GB9.-0 File (pending) File (pending) File (pending) File (pending) Basic insulation at 80 V rms (7 V peak) working voltage Reinforced insulation at 5 V rms (587 V peak) Notes: In accordance with UL 577, each π0x6/πx6/πx6 is proof tested by applying an insulation test voltage 700 V rms for sec. In accordance with DIN V VDE V 088-0, each π0x6/πx6/πx6 is proof tested by applying an insulation test voltage 59 V peak for sec (partial discharge detection limit = 5 pc). The * marking branded on the component designates DIN V VDE V approval. Rev. A Page 9 of

10 DIN V VDE V (VDE V 088-0) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance of the safety data. The * marking on packages denotes DIN V VDE V approval. Table 8. πxx Description Test Conditions/Comments Symbol Characteristic Unit Installation Classification per DIN VDE 00 For Rated Mains Voltage 50 V rms For Rated Mains Voltage 00 V rms For Rated Mains Voltage 00 V rms I to IV I to III I to III Climatic Classification 0/05/ Pollution Degree per DIN VDE 00, Table Maximum Working Insulation Voltage VIORM 565 V peak Input to Output Test Voltage, Method B Input to Output Test Voltage, Method A After Environmental Tests Subgroup After Input and/or Safety Test Subgroup and Subgroup V IORM.875 = V pd (m), 00% production test, tini = t m = sec, partial discharge < 5 pc V IORM.5 = V pd (m), t ini = 60 sec, t m = 0 sec, partial discharge < 5 pc V IORM. = V pd (m), t ini = 60 sec, t m = 0 sec, partial discharge < 5 pc Vpd (m) 059 V peak Vpd (m) 88 V peak 678 V peak Highest Allowable Overvoltage VIOTM 5656 V peak Surge Isolation Voltage Basic V peak = 6 kv,. µs rise time, 50 µs, 50% VIOSM 65 V peak fall time Safety Limiting Values Maximum value allowed in the event of a failure (see Figure ) Maximum Junction Temperature T S 50 C Total Power Dissipation at 5 C P S.6 W Insulation Resistance at T S V IO = 800 V R S >0 9 Ω πxx6 Description Test Conditions/Comments Symbol Characteristic Unit Installation Classification per DIN VDE 00 For Rated Mains Voltage 50 V rms For Rated Mains Voltage 00 V rms For Rated Mains Voltage 600 V rms I to IV I to IV I to III Climatic Classification 0/5/ Pollution Degree per DIN VDE 00, Table Maximum Working Insulation Voltage VIORM 89 V peak Input to Output Test Voltage, Method B Input to Output Test Voltage, Method A After Environmental Tests Subgroup After Input and/or Safety Test Subgroup and Subgroup V IORM.875 = V pd (m), 00% production test, tini = t m = sec, partial discharge < 5 pc V IORM.5 = V pd (m), t ini = 60 sec, t m = 0 sec, partial discharge < 5 pc V IORM. = V pd (m), t ini = 60 sec, t m = 0 sec, partial discharge < 5 pc Vpd (m) 59 V peak Vpd (m) 7 V peak 09 V peak Rev. A Page 0 of

11 Propagation Delay Time(ns) Data Sheet Highest Allowable Overvoltage VIOTM 88 V peak Surge Isolation Voltage Basic V peak = 0 kv,. µs rise time, 50 µs, 50% VIOSM 769 V peak fall time Surge Isolation Voltage Reinforced V peak = 6 kv,. µs rise time, 50 µs, 50% VIOSM 0000 V peak fall time Safety Limiting Values Maximum value allowed in the event of a failure (see Figure ) Maximum Junction Temperature T S 50 C Total Power Dissipation at 5 C P S.78 W Insulation Resistance at T S V IO = 800 V R S >0 9 Ω πxx πxx6 Figure. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V tplh at.v tphl at.v tplh at 5V tphl at 5V Free-Air Temperature ( ) Figure Propagation Delay vs. Temperature at Various Voltages Rev. A Page of

12 ABSOLUTE MAXIMUM RATINGS TA = 5 C, unless otherwise noted. Table 9. Parameter Supply Voltages (V DD, V DD) Input Voltages (V IA, V IB) Output Voltages (V OA, V OB) Average Output Current per Pin Side Output Current (I O) Side Output Current (I O) Common-Mode Transients Rating 0.5 V to +7.0 V 0.5 V to V DDI V 0.5 V to V DDO V 0 ma to +0 ma 0 ma to +0 ma 50 kv/µs to +50 kv/µs Storage Temperature (T ST) Range 65 C to +50 C Ambient Operating Temperature 0 C to +5 C (T A) Range Notes: VDDI is the input side supply voltage. VDDO is the output side supply voltage. See Figure for the maximum rated current values for various temperatures. Common-mode transients refer to the common-mode transients across the insulation barrier. Common-mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 0. Maximum Continuous Working Voltage πxx Parameter Rating Constraint AC VOLTAGE Lifetime limited by package creepage maximum approved working voltage per IEC Bipolar Waveform Basic Insulation Reinforced Insulation Unipolar Waveform Basic Insulation Reinforced Insulation 789 V peak 0 V peak 909 V peak 69 V peak DC VOLTAGE Lifetime limited by package creepage maximum approved working voltage per IEC Basic Insulation Reinforced Insulation 558 V peak 85 V peak Rev. A Page of

13 πxx6 Parameter Rating Constraint AC VOLTAGE Lifetime limited by package creepage maximum approved working voltage per IEC Bipolar Waveform Basic Insulation Reinforced Insulation Unipolar Waveform Basic Insulation Reinforced Insulation 89 V peak 89 V peak 698 V peak 9 V peak DC VOLTAGE Lifetime limited by package creepage maximum approved working voltage per IEC Basic Insulation Reinforced Insulation 57 V peak 579 V peak Notes: Maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Insulation lifetimes for the specified test condition is greater than 50 years. Truth Tables Table. Truth Table (Positive Logic) VIx Input V DDI State V DDO State Default Low (N0), VOx Output, Default High (N), VOx Output, Test Conditions/Comments Low Powered Powered Low Low Normal operation High Powered Powered High High Normal operation Don t Care 5 Unpowered Powered Low High Fail-safe output Don t Care 5 Powered Unpowered High Impedance High Impedance Notes: VIx and VOx refer to the input and output signals of a given channel (A, B or C). VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively. N0 is the π0xx0/πxx0/πxx0 models; N is the π0xx/πxx/πxx models. See the Ordering Guide. Powered = Power Up (Vcc VDDxUV+), Power Down (Vcc VDDxUV ). Unpowered = Power Up (Vcc < VDDxUV+), Power Down (Vcc < VDDxUV ). 5 Input pins (VIx) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection circuitry. Rev. A Page of

14 PIN CONFIGURATIONS AND FUTION DESCRIPTIONS VDD 6 VDD GND VIA π0 5 GND VOA VIB VIC GND VOB TOP VIEW (Not to scale) VOC GND Figure. π0 Pin Configuration π0 Pin Function Descriptions Pin No. Mnemonic Description VDD Supply Voltage for Isolator Side. GND Ground. This pin is the ground reference for Isolator Side. VIA Logic Input A. VIB Logic Input B. 5 VIC Logic Input C. 6 No connect. 7 No connect. 8 GND Ground. This pin is the ground reference for Isolator Side. 9 GND Ground. This pin is the ground reference for Isolator Side. 0 No connect. No connect. VOC Logic Output C. VOB Logic Output B. VOA Logic Output A. 5 GND Ground. This pin is the ground reference for Isolator Side. 6 VDD Supply Voltage for Isolator Side. Rev. A Page of

15 VDD 6 VDD GND VIA π 5 GND VOA VIB VOC GND VOB TOP VIEW (Not to scale) VIC GND Figure5. π Pin Configuration π Pin Function Descriptions Pin No. Mnemonic Description VDD Supply Voltage for Isolator Side. GND Ground. This pin is the ground reference for Isolator Side. VIA Logic Input A. VIB Logic Input B. 5 VOC Logic Output C. 6 No connect. 7 No connect. 8 GND Ground. This pin is the ground reference for Isolator Side. 9 GND Ground. This pin is the ground reference for Isolator Side. 0 No connect. No connect. VIC Logic Input C. VOB Logic Output B. VOA Logic Output A. 5 GND Ground. This pin is the ground reference for Isolator Side. 6 VDD Supply Voltage for Isolator Side. Rev. A Page 5 of

16 VDD 6 VDD GND VOA π 5 GND VIA VIB VIC GND VOB TOP VIEW (Not to scale) VOC GND Figure6. π Pin Configuration π Pin Function Descriptions Pin No. Mnemonic Description VDD Supply Voltage for Isolator Side. GND Ground. This pin is the ground reference for Isolator Side. VOA Logic Output A. VIB Logic Input B. 5 VIC Logic Input C. 6 No connect. 7 No connect. 8 GND Ground. This pin is the ground reference for Isolator Side. 9 GND Ground. This pin is the ground reference for Isolator Side. 0 No connect. No connect. VOC Logic Output C. VOB Logic Output B. VIA Logic Input A. 5 GND Ground. This pin is the ground reference for Isolator Side. 6 VDD Supply Voltage for Isolator Side. Rev. A Page 6 of

17 Data Sheet APPLICATIONS INFORMATION OVERVIEW The transmit data across an isolation barrier by layers of silicon oxide isolation. The have very low propagation delay and high speed. The input/output design techniques allow logic and supply voltages over a wide range from.0 V to 5.5 V, offering voltage translation of. V, and 5 V logic. The architecture is designed for high common-mode transient immunity and high immunity to electrical noise and magnetic interference. See the Ordering Guide for the model numbers that have the failsafe output state of low or the fail-safe output state of high. PCB LAYOUT The digital isolators require no external Channel matching is the maximum amount the propagation delay differs between channels within a single component. Propagation delay skew is the maximum amount the propagation delay differs between multiple components operating under the same conditions. JITTER MEASUREMENT Figure 9 shows the eye diagram for the. The measurement was taken using an Keysight 860A pulse pattern generator at 0 Mbps with pseudorandom bit sequences (PRBS) (n ), n =, for 5 V supplies. Jitter was measured with the Keysight DSOS0A oscilloscope, GHz, 0 GS/s with the DPOJET jitter and eye diagram analysis tools. The result shows a typical measurement on the with 7 ps p-p jitter. interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 7). Bypass capacitors are most conveniently connected between Pin and Pin 8 for VDD and between Pin 9 and Pin 6 for VDD. The recommended bypass capacitor value is between 0.0 μf and 0. μf. The total lead length between both ends of the capacitor and the input power supply pin must not exceed 0 mm. Figure9. Eye Diagram INSULATION LIFETIME Figure7.Recommended Printed Circuit Board Layout In applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. Furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the Absolute Maximum Ratings of the device, thereby leading to latch-up or permanent damage. PROPAGATION DELAY RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a Logic 0 output may differ from the propagation delay to a Logic output. INPUT (VIx) 50% tplh OUTPUT (VOx) tphl 50% 0 Figure 8. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved. All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation as well as on the materials and material interfaces. The two types of insulation degradation of primary interest are breakdown along surfaces exposed to the air and insulation wear out. Surface breakdown is the phenomenon of surface tracking and the primary determinant of surface creepage requirements in system level standards. Insulation wear out is the phenomenon where charge injection or displacement currents inside the insulation material cause long-term insulation degradation. Surface Tracking Surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working voltage, the environmental conditions, and the properties of the insulation material. Safety agencies perform characterization testing on the surface insulation of components that allows the components to be categorized in different material groups. Lower material group ratings are more resistant to surface tracking and, therefore, can provide adequate lifetime with smaller creepage. The minimum creepage for a given working voltage and material Rev. A Page 7 of

18 group is in each system level standard and is based on the total rms voltage across the isolation, pollution degree, and material group. The material group and creepage for the isolators are presented in Table 5. Insulation Wear Out The lifetime of insulation caused by wear out is determined by its thickness, material properties, and the voltage stress applied. It is important to verify that the product lifetime is adequate at the application working voltage. The working voltage supported by an isolator for wear out may not be the same as the working voltage supported for tracking. It is the working voltage applicable to tracking that is specified in most standards. Testing and modeling show that the primary driver of long term degradation is displacement current in the silicon oxide insulation causing incremental damage. The stress on the insulation can be broken down into broad categories, such as dc stress, which causes very little wear out because there is no displacement current, and an ac component time varying voltage stress, which causes wear out. The ratings in certification documents are usually based on 60 Hz sinusoidal stress because this reflects isolation from line voltage. However, many practical applications have combintions of 60 Hz ac and dc across the barrier as shown in Equation. Because only the ac portion of the stress causes wear out, the equation can be rearranged to solve for the ac rms voltage, as is shown in Equation. For insulation wear out with the silicon oxide materials used in these products, the ac rms voltage determines the product lifetime. creepage, clearance, and lifetime of a device, see Figure 0 and the following equations. ISO LA TIO N VO LTA GE V PE AK V RMS TIME V AC RMS Figure0. Critical Voltage Example The working voltage across the barrier from Equation is This is the working voltage used together with the material group and pollution degree when looking up the creepage required by a system standard. To determine if the lifetime is adequate, obtain the time varying portion of the working voltage. To obtain the ac rms voltage, use Equation. V DC - 05 where: VRMS is the total rms working voltage. VAC RMS is the time varying portion of the working voltage. VDC is the dc offset of the working voltage. Calculation and Use of Parameters Example The following example frequently arises in power conversion applications. Assume that the line voltage on one side of the isolation is 0 VAC RMS and a 00 VDC bus voltage is present on the other side of the isolation barrier. The isolator material is polyimide. To establish the critical voltages in determining the In this case, the ac rms voltage is simply the line voltage of 0 V rms. This calculation is more relevant when the waveform is not sinusoidal. The value is compared to the limits for working voltage in Table 0 for the expected lifetime, less than a 60 Hz sine wave, and it is well within the limit for a 50-year service life. Note that the dc working voltage limit in Table 0 is set by the creepage of the package as specified in IEC This value can differ for specific system level standards. Rev. A Page 8 of

19 OUTLINE DIMENSIONS CONTROLLING DIMENSIONS ARE IN MILLIMETERS; IH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFEREE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. 6-Lead Standard Small Outline Package [SOIC_N] N/Arrow Body (S-6-N) Dimensions shown in millimeters and (inches) Figure. 6-Lead Standard Small Outline Package [SOIC_W] Wide Body (S-6-W) Dimensions shown in millimeters and (inches) Rev. A Page 9 of

20 REEL INFORMATION S-6-N S-6-W Rev. A Page 0 of

21 ORDERING GUIDE Model Temperature Range No. of Inputs, V DD Side No. of Inputs, V DD Side Withstand Voltage Rating (kv rms) Fail-Safe Output State Package Description Package Option Quantity π0a 0 C to +5 C 0 High 6-Lead SOIC_N S-6-N 500 per reel π0a0 0 C to +5 C 0 Low 6-Lead SOIC_N S-6-N 500 per reel πa 0 C to +5 C High 6-Lead SOIC_N S-6-N 500 per reel πa0 0 C to +5 C Low 6-Lead SOIC_N S-6-N 500 per reel πa 0 C to +5 C High 6-Lead SOIC_N S-6-N 500 per reel πa0 0 C to +5 C Low 6-Lead SOIC_N S-6-N 500 per reel π0e 0 C to +5 C 0 High 6-LeEd SOIC_N S-6-N 500 per reel π0e0 0 C to +5 C 0 Low 6-LeEd SOIC_N S-6-N 500 per reel πe 0 C to +5 C High 6-LeEd SOIC_N S-6-N 500 per reel πe0 0 C to +5 C Low 6-LeEd SOIC_N S-6-N 500 per reel πe 0 C to +5 C High 6-LeEd SOIC_N S-6-N 500 per reel πe0 0 C to +5 C Low 6-LeEd SOIC_N S-6-N 500 per reel π0m 0 C to +5 C 0 High 6-LeEd SOIC_N S-6-N 500 per reel π0m0 0 C to +5 C 0 Low 6-LeEd SOIC_N S-6-N 500 per reel πm 0 C to +5 C High 6-LeEd SOIC_N S-6-N 500 per reel πm0 0 C to +5 C Low 6-LeEd SOIC_N S-6-N 500 per reel πm 0 C to +5 C High 6-LeEd SOIC_N S-6-N 500 per reel πm0 0 C to +5 C Low 6-LeEd SOIC_N S-6-N 500 per reel π0u 0 C to +5 C 0 High 6-Lead SOIC_N S-6-N 500 per reel π0u0 0 C to +5 C 0 Low 6-Lead SOIC_N S-6-N 500 per reel πu 0 C to +5 C High 6-Lead SOIC_N S-6-N 500 per reel πu0 0 C to +5 C Low 6-Lead SOIC_N S-6-N 500 per reel πu 0 C to +5 C High 6-Lead SOIC_N S-6-N 500 per reel πu0 0 C to +5 C Low 6-Lead SOIC_N S-6-N 500 per reel π0a6 0 C to +5 C 0 6 High 6-Lead SOIC_W S-6-W 000 per reel π0a60 0 C to +5 C 0 6 Low 6-Lead SOIC_W S-6-W 000 per reel πa6 0 C to +5 C 6 High 6-Lead SOIC_W S-6-W 000 per reel πa60 0 C to +5 C 6 Low 6-Lead SOIC_W S-6-W 000 per reel πa6 0 C to +5 C 6 High 6-Lead SOIC_W S-6-W 000 per reel πa60 0 C to +5 C 6 Low 6-Lead SOIC_W S-6-W 000 per reel π0m6 0 C to +5 C 0 6 High 6-Lead SOIC_W S-6-W 000 per reel π0m60 0 C to +5 C 0 6 Low 6-Lead SOIC_W S-6-W 000 per reel πm6 0 C to +5 C 6 High 6-Lead SOIC_W S-6-W 000 per reel πm60 0 C to +5 C 6 Low 6-Lead SOIC_W S-6-W 000 per reel πm6 0 C to +5 C 6 High 6-Lead SOIC_W S-6-W 000 per reel πm60 0 C to +5 C 6 Low 6-Lead SOIC_W S-6-W 000 per reel Rev. A Page of

22 π0u6 0 C to +5 C 0 6 High 6-Lead SOIC_W S-6-W 000 per reel π0u60 0 C to +5 C 0 6 Low 6-Lead SOIC_W S-6-W 000 per reel πu6 0 C to +5 C 6 High 6-Lead SOIC_W S-6-W 000 per reel πu60 0 C to +5 C 6 Low 6-Lead SOIC_W S-6-W 000 per reel πu6 0 C to +5 C 6 High 6-Lead SOIC_W S-6-W 000 per reel πu60 0 C to +5 C 6 Low 6-Lead SOIC_W S-6-W 000 per reel Part number named rule: SeriesNumber:,,... π()()(0)(a)()(0) Total Channel Amount: N=N Channels N=,,,5,6... Reverse Channel Amount: N=N Channels N=0,,,... Data Rate:A=600Mbps E=00Mbps M=0Mbps U=50Kbps Isolation Voltages: N= KVrms AC N= KVrms AC N=6 6KVrms AC Fail-Safe Output State: 0=Logic Low =Logic High Rev. A Page of