SN54LV166A, SN74LV166A 8-BIT PARALLEL-LOAD SHIFT REGISTERS

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1 2-V to 5.5-V V CC Operation Max t pd of 10.5 at 5 V Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T A = 25 C Typical V OV (Output V O Undershoot) >2.3 V at V CC = 3.3 V, T A = 25 C I off Supports Partial-Power-Down-Mode Operation Synchronous Load SN54LV166A...J O W PACKAGE SN74LV166A... D, DB, DGV, NS, O PW PACKAGE (TOP VIEW) SE A B C D IN GND V CC S/LD Q G F E Direct Overriding Clear Parallel-to-Serial Conversion Latch-Up Performance Exceeds 100 ma Per JESD 78, Class II ESD Protection Exceeds JESD V uman-body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (01) B C NC D IN SN54LV166A... FK PACKAGE (TOP VIEW) A SE NC V CC S/LD Q NC G F GND NC E description/ordering information NC No internal connection The LV166A devices are 8-bit parallel-load shift registers, designed for 2-V to 5.5-V V CC operation. TA ODEING INFOMATION PACKAGE ODEABLE PAT NUMBE SN74LV166AD SN74LV166AD TOP-SIDE MAKING SOIC D Tube of 40 eel of 2500 LV166A SOP NS eel of 2000 SN74LV166ANS 74LV166A 40 C to85 C SSOP DB eel of 2000 SN74LV166ADB LV166A Tube of 90 SN74LV166APW TSSOP PW eel of 2000 SN74LV166APW LV166A eel of 250 SN74LV166APWT TVSOP DGV eel of 2000 SN74LV166ADGV LV166A CDIP J Tube of 25 SNJ54LV166AJ SNJ54LV166AJ 55 C to 125 C CFP W Tube of 150 SNJ54LV166AW SNJ54LV166AW LCCC FK Tube of 55 SNJ54LV166AFK SNJ54LV166AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTEWISE NOTED this document contai PODUCTION DATA information current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2003, Texas Itruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 description/ordering information (continued) The LV166A parallel-in or serial-in, serial-out registers feature gated clock (, IN) inputs and an overriding clear () input. The parallel-in or serial-in modes are established by the shift/ load (S/LD) input. When high, S/LD enables the serial (SE) data input and couples the eight flip-flops for serial shifting with each clock () pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of through a 2-input positive-no gate, permitting one input to be used as a clock-enable or clock-inhibit function. olding either or IN high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. IN should be changed to the high level only when is high. overrides all other inputs, including, and resets all flip-flops to zero. These devices are fully specified for partial-power-down applicatio using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE INPUTS OUTPUTS INTENAL S/LD IN SE PAALLEL A... QA QB L X X X X X L L L X L L X X QA0 QB0 0 L L X a...h a b h L X QAn QGn L L X L QAn QGn X X X QA0 QB0 0 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 logic diagram (positive logic) S/LD SE 15 1 A B C D E F G IN Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. typical clear, shift, load, inhibit, and shift sequence IN SE S/LD Parallel Inputs A B C D E F G L L L Serial Shift L L L Inhibit Serial Shift Clear Load POST OFFICE BOX DALLAS, TEXAS

4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7 V Input voltage range, V I (see Note 1) V to 7 V Output voltage range applied in high or low state, V O (see Notes 1 and 2) V to V CC V Voltage range applied to any output in the power-off state, V O (see Note 1) V to 7 V Input clamp current, I IK (V I < 0) ma Output clamp current, I OK (V O < 0 or V O > V CC ) ±50 ma Continuous output current, I O (V O = 0 to V CC ) ±25 ma Continuous current through V CC or GND ±50 ma Package thermal impedance, θ JA (see Note 3): D package C/W DB package C/W DGV package C/W NS package C/W PW package C/W Storage temperature range, T stg C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD POST OFFICE BOX DALLAS, TEXAS 75265

5 recommended operating conditio (see Note 4) SN54LV166A SN74LV166A MIN MAX MIN MAX Supply voltage V VI VIL igh-level input voltage Low-level input voltage = 2 V = 2.3 V to 2.7 V = 3 V to 3.6 V = 4.5 V to 5.5 V = 2 V = 2.3 V to 2.7 V = 3 V to 3.6 V = 4.5 V to 5.5 V VI Input voltage V VO Output voltage 0 0 V IO IOL igh-level output current Low-level output current = 2 V µa = 2.3 V to 2.7 V 2 2 = 3 V to 3.6 V 6 6 ma = 4.5 V to 5.5 V = 2 V µa = 2.3 V to 2.7 V 2 2 = 3 V to 3.6 V 6 6 ma = 4.5 V to 5.5 V = 2.3 V to 2.7 V t/ v Input traition rise or fall rate = 3 V to 3.6 V /V = 4.5 V to 5.5 V TA Operating free-air temperature C NOTE 4: All unused inputs of the device must be held at or GND to eure proper device operation. efer to the TI application report, Implicatio of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PAAMETE TEST CONDITIONS VO VOL SN54LV166A SN74LV166A MIN TYP MAX MIN TYP MAX IO = 50 µa 2 V to 5.5 V IO = 2 ma 2.3 V 2 2 IO = 6 ma 3 V IO = 12 ma 4.5 V IOL = 50 µa 2 V to 5.5 V IOL = 2 ma 2.3 V IOL = 6 ma 3 V IOL = 12 ma 4.5 V II VI = 5.5 V or GND 0 to 5.5 V ±1 ±1 µa ICC VI = or GND, IO = V µa Ioff VI or VO = 0 to 5.5 V µa Ci VI = or GND 3.3 V pf V V V V PODUCT PEVIEW information concer products in the formative or design phase of development. Characteristic data and other specificatio are design goals. Texas Itruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX DALLAS, TEXAS

6 timing requirements over recommended operating free-air temperature range, V CC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) tw Pulse duration TA = 25 C SN54LV166A SN74LV166A MIN MAX MIN MAX MIN MAX low high or low IN before Data before tsu Setup time S/LD before SE before inactive before th old time Data after timing requirements over recommended operating free-air temperature range, V CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) tw Pulse duration TA = 25 C SN54LV166A SN74LV166A MIN MAX MIN MAX MIN MAX low high or low IN before Data before tsu Setup time S/LD before SE before inactive before th old time Data after timing requirements over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) tw Pulse duration TA = 25 C SN54LV166A SN74LV166A MIN MAX MIN MAX MIN4 MAX low high or low IN before Data before tsu Setup time S/LD before SE before inactive before th old time Data after PODUCT PEVIEW information concer products in the formative or design phase of development. Characteristic data and other specificatio are design goals. Texas Itruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 switching characteristics over recommended operating free-air temperature range, V CC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PAAMETE FOM TO LOAD TA = 25 C SN54LV166A SN74LV166A (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX fmax CL = 15 pf 50* 105* 45* 45 CL = 50 pf * 16* 1* 18* 1 18 CL =15pF tpd 9.2* 19.8* 1* 22* CL =50pF tpd * On products compliant to MIL-PF-38535, this parameter is not production tested. Mz switching characteristics over recommended operating free-air temperature range, V CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PAAMETE FOM TO LOAD TA = 25 C SN54LV166A SN74LV166A (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX fmax CL = 15 pf 65* 150* 55* 55 CL = 50 pf * 12.5* 1* 15* 1 15 CL =15pF tpd 6.6* 15.4* 1* 18* CL =50pF tpd * On products compliant to MIL-PF-38535, this parameter is not production tested. Mz switching characteristics over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PAAMETE FOM TO LOAD TA = 25 C SN54LV166A SN74LV166A (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX fmax CL = 15 pf 110* 205* 90* 90 CL = 50 pf * 8.6* 1* 10* 1 10 CL =15pF tpd 4.8* 9.9* 1* 11.5* CL =50pF tpd * On products compliant to MIL-PF-38535, this parameter is not production tested. Mz operating characteristics, T A = 25 C PAAMETE TEST CONDITIONS TYP 3.3 V 39.1 Cpd Power dissipation capacitanceacitance CL =50pF F, f=10mz pf 5 V 44.5 PODUCT PEVIEW information concer products in the formative or design phase of development. Characteristic data and other specificatio are design goals. Texas Itruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX DALLAS, TEXAS

8 PAAMETE MEASUEMENT INFOMATION From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) L = 1 kω S1 Open GND TEST tpl/ tplz/tpzl tpz/tpz Open Drain S1 Open GND LOAD CICUIT FO TOTEM-POLE OUTPUTS LOAD CICUIT FO 3-STATE AND OPEN-DAIN OUTPUTS Input tw VOLTAGE WAVEFOMS PULSE DUATION 0 V Timing Input Data Input tsu th VOLTAGE WAVEFOMS SETUP AND OLD TIMES 0 V 0 V Input In-Phase Output Out-of-Phase Output tpl VO VOL tpl 0 V VO VOL VOLTAGE WAVEFOMS POPAGATION DELAY TIMES INVETING AND NONINVETING OUTPUTS Output Control Output Waveform 1 S1 at (see Note B) Output Waveform 2 S1 at GND (see Note B) tpzl tpz tplz VOL V VOL tpz VOLTAGE WAVEFOMS ENABLE AND DISABLE TIMES LOW- AND IG-LEVEL ENABLING 0 V VO VO 0.3 V 0 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: P 1 Mz, ZO = 50 Ω, tr 3, tf 3. D. The outputs are measured one at a time with one input traition per measurement. E. tplz and tpz are the same as tdis. F. tpzl and tpz are the same as ten. G. and tpl are the same as tpd.. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX DALLAS, TEXAS 75265

9 MECANICAL DATA MPDS006C FEBUAY 1996 EVISED AUGUST 2000 DGV (-PDSO-G**) 24 PINS SOWN PLASTIC SMALL-OUTLINE 0,40 0,23 0,13 0,07 M ,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 1 12 A 0 8 0,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,08 DIM PINS ** A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11, /E 08/00 NOTES: A. All linear dimeio are in millimeters. B. This drawing is subject to change without notice. C. Body dimeio do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pi MO /16/20/56 Pi MO-194 POST OFFICE BOX DALLAS, TEXAS 75265

12 MECANICAL DATA MSSO002E JANUAY 1995 EVISED DECEMBE 2001 DB (-PDSO-G**) 28 PINS SOWN PLASTIC SMALL-OUTLINE 0,65 0,38 0,22 0,15 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane ,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,10 DIM PINS ** A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12, /E 12/01 NOTES: A. All linear dimeio are in millimeters. B. This drawing is subject to change without notice. C. Body dimeio do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 POST OFFICE BOX DALLAS, TEXAS 75265

13 MECANICAL DATA MTSS001C JANUAY 1995 EVISED FEBUAY 1999 PW (-PDSO-G**) 14 PINS SOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,10 M 0, ,50 4,30 6,60 6,20 0,15 NOM Gage Plane 1 A ,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 DIM PINS ** A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 01/97 NOTES: A. All linear dimeio are in millimeters. B. This drawing is subject to change without notice. C. Body dimeio do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 POST OFFICE BOX DALLAS, TEXAS 75265

14 IMPOTANT NOTICE Texas Itruments Incorporated and its subsidiaries (TI) reserve the right to make correctio, modificatio, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditio of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applicatio assistance or customer product design. Customers are respoible for their products and applicatio using TI components. To minimize the risks associated with customer products and applicatio, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any licee, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not cotitute a licee from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a licee from a third party under the patents or other intellectual property of the third party, or a licee from TI under the patents or other intellectual property of TI. eproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditio, limitatio, and notices. eproduction of this information with alteration is an unfair and deceptive business practice. TI is not respoible or liable for such altered documentation. esale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not respoible or liable for any such statements. Following are ULs where you can obtain information on other Texas Itruments products and application solutio: Products Applicatio Amplifiers amplifier.ti.com Audio Data Converters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Telephony Video & Imaging Wireless Mailing Address: Texas Itruments Post Office Box Dallas, Texas Copyright 2004, Texas Itruments Incorporated

SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR 2-V to 5.5-V V CC Operation Typical V OLP (Output Ground Bounce) 2.3 V at V CC = 3.3 V, T A = 25 C Support Mixed-Mode Voltage