SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

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1 2-V to 5.5-V V CC Operation Max t pd of 10.5 at 5 V Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T = 25 C Typical V OHV (Output V OH Undershoot) >2.3 V at V CC = 3.3 V, T = 25 C Support Mixed-Mode Voltage Operation on ll Ports Latch-Up Performance Exceeds 250 m Per JESD 17 ESD Protection Exceeds JESD V Human-Body Model (114-) 200-V Machine Model (115-) 1000-V Charged-Device Model (01) SN54LV164...J O W PCKGE SN74LV D, DB, DGV, NS, O PW PCKGE (TOP VIEW) B Q Q B Q C Q D GND V CC Q H Q G Q F Q E description/ordering information SN74LV GY PCKGE (TOP VIEW) B Q Q B Q C Q D GND CC V Q H Q G Q F Q E SN54LV FK PCKGE (TOP VIEW) Q NC Q B NC Q C B NC V CC Q H Q D GND NC NC No internal connection Q G NC Q F NC Q E The LV164 devices are 8-bit parallel-out serial shift registers designed for 2-V to 5.5-V V CC operation. T ODEING INFOMTION PCKGE ODEBLE PT NUMBE TOP-SIDE MKING QFN GY eel of 1000 SN74LV164GY LV164 SOIC D Tube of 50 SN74LV164D eel of 2500 SN74LV164D LV164 SOP NS eel of 2000 SN74LV164NS 74LV C to 85 C SSOP DB eel of 2000 SN74LV164DB LV164 Tube of 90 SN74LV164PW TSSOP PW eel of 2000 SN74LV164PW LV164 eel of 250 SN74LV164PWT TVSOP DGV eel of 2000 SN74LV164DGV LV164 CDIP J Tube of 25 SNJ54LV164J SNJ54LV164J 55 C to 125 C CFP W Tube of 150 SNJ54LV164W SNJ54LV164W LCCC FK Tube of 55 SNJ54LV164FK SNJ54LV164FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHEWISE NOTED this document contai PODUCTION DT information current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2003, Texas Itruments Incorporated POST OFFICE BOX DLLS, TEXS

2 description/ordering information (continued) These devices feature ND-gated serial ( and B) inputs and an asynchronous clear () input. The gated serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level traition of the clock () input. FUNCTION TBLE INPUTS OUTPUTS B Q QB...QH L X X X L L L H L X X Q0 QB0 QH0 H H H H Qn QGn H L X L Qn QGn H X L L Qn QGn Q0, QB0, QH0 = the level of Q, QB, or QH, respectively, before the indicated steady-state input conditio were established. Qn, QGn = the level of Q or QG before the most recent traition of the clock: indicates a 1-bit shift. logic diagram (positive logic) 8 B Q QB QC QD QE QF QG QH Pin numbers shown are for the D, DB, DGV, J, NS, PW, GY, and W packages. 2 POST OFFICE BOX DLLS, TEXS 75265

3 typical clear, shift, and clear sequences Serial Inputs B Q QB QC Outputs QD QE QF QG QH Clear Clear POST OFFICE BOX DLLS, TEXS

4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7 V Input voltage range, V I (see Note 1) V to 7 V Voltage range applied to any output in the high-impedance or power-off state, V O (see Note 1) V to 7 V Output voltage range, V O (see Notes 1 and 2) V to V CC V Input clamp current, I IK (V I < 0) m Output clamp current, I OK (V O < 0 or V O > V CC ) ±50 m Continuous output current, I O (V O = 0 to V CC ) ±25 m Continuous current through V CC or GND ±50 m Package thermal impedance, θ J (see Note 3): D package C/W (see Note 3): DB package C/W (see Note 3): DGV package C/W (see Note 3): NS package C/W (see Note 3): PW package C/W (see Note 4): GY package C/W Storage temperature range, T stg C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD The package thermal impedance is calculated in accordance with JESD POST OFFICE BOX DLLS, TEXS 75265

5 recommended operating conditio (see Note 5) SN54LV164 SN74LV164 MIN MX MIN MX Supply voltage V VIH VIL High-level input voltage Low-level input voltage = 2 V = 2.3 V to 2.7 V = 3 V to 3.6 V = 4.5 V to 5.5 V = 2 V = 2.3 V to 2.7 V = 3 V to 3.6 V = 4.5 V to 5.5 V VI Input voltage V VO Output voltage 0 0 V IOH IOL High-level output current Low-level output current = 2 V µ = 2.3 V to 2.7 V 2 2 = 3 V to 3.6 V 6 6 m = 4.5 V to 5.5 V = 2 V µ = 2.3 V to 2.7 V 2 2 = 3 V to 3.6 V 6 6 m = 4.5 V to 5.5 V = 2.3 V to 2.7 V t/ v Input traition rise or fall rate = 3 V to 3.6 V /V = 4.5 V to 5.5 V T Operating free-air temperature C NOTE 5: ll unused inputs of the device must be held at or GND to eure proper device operation. efer to the TI application report, Implicatio of Slow or Floating CMOS Inputs, literature number SCB004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PMETE TEST CONDITIONS VOH VOL SN54LV164 SN74LV164 MIN TYP MX MIN TYP MX IOH = 50 µ 2 V to 5.5 V IOH = 2 m 2.3 V 2 2 IOH = 6 m 3 V IOH = 12 m 4.5 V IOL = 50 µ 2 V to 5.5 V IOL = 2 m 2.3 V IOL = 6 m 3 V IOL = 12 m 4.5 V II VI = 5.5 V or GND 0 to 5.5 V ±1 ±1 µ ICC VI = or GND, IO = V µ Ioff VI or VO = 0 to 5.5 V µ Ci VI = or GND 3.3 V pf V V V V PODUCT PEVIEW information concer products in the formative or design phase of development. Characteristic data and other specificatio are design goals. Texas Itruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX DLLS, TEXS

6 timing requirements over recommended operating free-air temperature range, V CC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) tw tsu Pulse duration Setup time T = 25 C SN54LV164 SN74LV164 MIN MX MIN MX MIN MX low high or low Data before inactive th Hold time Data after timing requirements over recommended operating free-air temperature range, V CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) tw tsu Pulse duration Setup time T = 25 C SN54LV164 SN74LV164 MIN MX MIN MX MIN MX low high or low Data before inactive th Hold time Data after timing requirements over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) tw tsu Pulse duration Setup time T = 25 C SN54LV164 SN74LV164 MIN MX MIN MX MIN MX low high or low Data before inactive th Hold time Data after switching characteristics over recommended operating free-air temperature range, V CC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) FOM TO LOD T = 25 C SN54LV164 SN74LV164 PMETE (INPUT) (OUTPUT) CPCITNCE MIN TYP MX MIN MX MIN MX CL = 15 pf 55* 105* 50* 50 fmax CL = 50 pf tpd Q 9.2* 17.6* 1* 20* 1 20 CL =15pF tphl Q 8.6* 16* 1* 18* 1 18 tpd Q CL =50pF tphl Q * On products compliant to MIL-PF-38535, this parameter is not production tested. MHz PODUCT PEVIEW information concer products in the formative or design phase of development. Characteristic data and other specificatio are design goals. Texas Itruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX DLLS, TEXS 75265

7 switching characteristics over recommended operating free-air temperature range, V CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PMETE FOM TO LOD T = 25 C SN54LV164 SN74LV164 (INPUT) (OUTPUT) CPCITNCE MIN TYP MX MIN MX MIN MX fmax CL = 15 pf 80* 155* 65* 65 CL = 50 pf tpd 6.4* 12.8* 1* 15* 1 15 Q CL =15pF tphl 6* 12.8* 1* 15* 1 15 tpd Q CL =50pF tphl * On products compliant to MIL-PF-38535, this parameter is not production tested. MHz switching characteristics over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PMETE FOM TO LOD T = 25 C SN54LV164 SN74LV164 (INPUT) (OUTPUT) CPCITNCE MIN TYP MX MIN MX MIN MX fmax CL = 15 pf 125* 220* 105* 105 CL = 50 pf tpd 4.5* 9* 1* 10.5* Q CL =15pF tphl 4.2* 8.6* 1* 10* 1 10 tpd Q CL =50pF tphl * On products compliant to MIL-PF-38535, this parameter is not production tested. MHz noise characteristics, V CC = 3.3 V, C L = 50 pf, T = 25 C (see Note 6) PMETE SN74LV164 MIN TYP MX VOL(P) Quiet output, maximum dynamic VOL V VOL(V) Quiet output, minimum dynamic VOL V VOH(V) Quiet output, minimum dynamic VOH 3.09 V VIH(D) High-level dynamic input voltage 2.31 V VIL(D) Low-level dynamic input voltage 0.99 V NOTE 6: Characteristics are for surface-mount packages only. operating characteristics, T = 25 C PMETE TEST CONDITIONS TYP 3.3 V 48.1 Cpd Power dissipation capacitanceacitance CL =50pF F, f=10mhz pf 5 V 47.5 PODUCT PEVIEW information concer products in the formative or design phase of development. Characteristic data and other specificatio are design goals. Texas Itruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX DLLS, TEXS

8 PMETE MESUEMENT INFOMTION From Output Under Test CL (see Note ) Test Point From Output Under Test CL (see Note ) L = 1 kω S1 Open GND TEST tplh/tphl tplz/tpzl tphz/tpzh Open Drain S1 Open GND LOD CICUIT FO TOTEM-POLE OUTPUTS LOD CICUIT FO 3-STTE ND OPEN-DIN OUTPUTS Input tw VOLTGE WVEFOMS PULSE DUTION 0 V Timing Input Data Input tsu th VOLTGE WVEFOMS SETUP ND HOLD TIMES 0 V 0 V Input 0 V Output Control 0 V In-Phase Output Out-of-Phase Output tplh tphl tphl VOH VOL tplh VOH VOL VOLTGE WVEFOMS POPGTION DELY TIMES INVETING ND NONINVETING OUTPUTS Output Waveform 1 S1 at (see Note B) Output Waveform 2 S1 at GND (see Note B) tpzl tpzh tplz VOL V VOL tphz VOLTGE WVEFOMS ENBLE ND DISBLE TIMES LOW- ND HIGH-LEVEL ENBLING VOH VOH 0.3 V 0 V NOTES:. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. C. ll input pulses are supplied by generators having the following characteristics: P 1 MHz, ZO = 50 Ω, tr 3, tf 3. D. The outputs are measured one at a time with one input traition per measurement. E. tplz and tphz are the same as tdis. F. tpzl and tpzh are the same as ten. G. tphl and tplh are the same as tpd. H. ll parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX DLLS, TEXS 75265

9 MECHNICL DT MPDS006C FEBUY 1996 EVISED UGUST 2000 DGV (-PDSO-G**) 24 PINS SHOWN PLSTIC SMLL-OUTLINE 0,40 0,23 0,13 0,07 M ,16 NOM 4,50 4,30 6,60 6,20 Gage Plane ,25 0,75 0,50 1,20 MX 0,15 0,05 Seating Plane 0,08 DIM PINS ** MX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 MIN 3,50 3,50 4,90 4,90 7,70 9,60 11, /E 08/00 NOTES:. ll linear dimeio are in millimeters. B. This drawing is subject to change without notice. C. Body dimeio do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pi MO /16/20/56 Pi MO-194 POST OFFICE BOX DLLS, TEXS 75265

13 MECHNICL DT MSSO002E JNUY 1995 EVISED DECEMBE 2001 DB (-PDSO-G**) 28 PINS SHOWN PLSTIC SMLL-OUTLINE 0,65 0,38 0,22 0,15 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane , ,95 0,55 2,00 MX 0,05 MIN Seating Plane 0,10 DIM PINS ** MX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 MIN 5,90 5,90 6,90 7,90 9,90 9,90 12, /E 12/01 NOTES:. ll linear dimeio are in millimeters. B. This drawing is subject to change without notice. C. Body dimeio do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 POST OFFICE BOX DLLS, TEXS 75265

14 MECHNICL DT MTSS001C JNUY 1995 EVISED FEBUY 1999 PW (-PDSO-G**) 14 PINS SHOWN PLSTIC SMLL-OUTLINE PCKGE 0,30 0,65 0,10 M 0, ,50 4,30 6,60 6,20 0,15 NOM Gage Plane ,25 0,75 0,50 1,20 MX 0,15 0,05 Seating Plane 0,10 DIM PINS ** MX 3,10 5,10 5,10 6,60 7,90 9,80 MIN 2,90 4,90 4,90 6,40 7,70 9, /F 01/97 NOTES:. ll linear dimeio are in millimeters. B. This drawing is subject to change without notice. C. Body dimeio do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 POST OFFICE BOX DLLS, TEXS 75265

15 IMPOTNT NOTICE Texas Itruments Incorporated and its subsidiaries (TI) reserve the right to make correctio, modificatio, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. ll products are sold subject to TI s terms and conditio of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applicatio assistance or customer product design. Customers are respoible for their products and applicatio using TI components. To minimize the risks associated with customer products and applicatio, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any licee, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not cotitute a licee from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a licee from a third party under the patents or other intellectual property of the third party, or a licee from TI under the patents or other intellectual property of TI. eproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditio, limitatio, and notices. eproduction of this information with alteration is an unfair and deceptive business practice. TI is not respoible or liable for such altered documentation. esale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not respoible or liable for any such statements. Following are ULs where you can obtain information on other Texas Itruments products and application solutio: Products pplicatio mplifiers amplifier.ti.com udio Data Converters dataconverter.ti.com utomotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Telephony Video & Imaging Wireless Mailing ddress: Texas Itruments Post Office Box Dallas, Texas Copyright 2004, Texas Itruments Incorporated

SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR 2-V to 5.5-V V CC Operation Typical V OLP (Output Ground Bounce) 2.3 V at V CC = 3.3 V, T A = 25 C Support Mixed-Mode Voltage