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1 SCLS403H APRIL 1998 REVISED APRIL V to 5.5-V V CC Operation Max t pd of 10.5 at 5 V Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T A = 25 C Typical V OHV (Output V OH Undershoot) >2.3 V at V CC = 3.3 V, T A = 25 C Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 ma Per JESD 17 ESD Protection Exceeds JESD V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) SN54LV164A...J OR W PACKAGE SN74LV164A... D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) A B Q A Q B Q C Q D GND V CC Q H Q G Q F Q E CLK description/ordering information SN74LV164A... RGY PACKAGE (TOP VIEW) B Q A Q B Q C Q D A CLK V GND CC Q H Q G Q F Q E SN54LV164A... FK PACKAGE (TOP VIEW) Q A NC Q B NC Q C B A NC V CC Q H Q D GND NC CLK NC No internal connection Q G NC Q F NC Q E The LV164A devices are 8-bit parallel-out serial shift registers designed for 2-V to 5.5-V V CC operation. TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING QFN RGY Reel of 1000 SN74LV164ARGYR LV164A Tube of 50 SN74LV164AD SOIC D Reel of 2500 SN74LV164ADR LV164A SOP NS Reel of 2000 SN74LV164ANSR 74LV164A 40 C to 85 C SSOP DB Reel of 2000 SN74LV164ADBR LV164A Tube of 90 SN74LV164APW TSSOP PW Reel of 2000 SN74LV164APWR LV164A Reel of 250 SN74LV164APWT TVSOP DGV Reel of 2000 SN74LV164ADGVR LV164A CDIP J Tube of 25 SNJ54LV164AJ SNJ54LV164AJ 55 C to 125 C CFP W Tube of 150 SNJ54LV164AW SNJ54LV164AW LCCC FK Tube of 55 SNJ54LV164AFK SNJ54LV164AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2005, Texas Itruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 SCLS403H APRIL 1998 REVISED APRIL 2005 description/ordering information (continued) These devices feature AND-gated serial (A and B) inputs and an asynchronous clear () input. The gated serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level traition of the clock (CLK) input. FUNCTION TABLE INPUTS OUTPUTS CLK A B QA QB...QH L X X X L L L H L X X QA0 QB0 QH0 H H H H QAn QGn H L X L QAn QGn H X L L QAn QGn QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before the indicated steady-state input conditio were established. QAn, QGn = the level of QA or QG before the most recent traition of the clock: indicates a 1-bit shift. logic diagram (positive logic) CLK 8 A B 1 2 C1 1D R C1 1D R C1 1D R C1 1D R C1 1D R C1 1D R C1 1D R C1 1D R QA QB QC QD QE QF QG QH Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages. 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 SCLS403H APRIL 1998 REVISED APRIL 2005 typical clear, shift, and clear sequences Serial Inputs A B CLK QA QB QC Outputs QD QE QF QG QH Clear Clear POST OFFICE BOX DALLAS, TEXAS

4 SCLS403H APRIL 1998 REVISED APRIL 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7 V Input voltage range, V I (see Note 1) V to 7 V Voltage range applied to any output in the high-impedance or power-off state, V O (see Note 1) V to 7 V Output voltage range, V O (see Notes 1 and 2) V to V CC V Input clamp current, I IK (V I < 0) ma Output clamp current, I OK (V O < 0) ma Continuous output current, I O (V O = 0 to V CC ) ±25 ma Continuous current through V CC or GND ±50 ma Package thermal impedance, θ JA (see Note 3): D package C/W (see Note 3): DB package C/W (see Note 3): DGV package C/W (see Note 3): NS package C/W (see Note 3): PW package C/W (see Note 4): RGY package C/W Storage temperature range, T stg C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD The package thermal impedance is calculated in accordance with JESD POST OFFICE BOX DALLAS, TEXAS 75265

5 recommended operating conditio (see Note 5) SN54LV164A SCLS403H APRIL 1998 REVISED APRIL 2005 SN74LV164A MIN MAX MIN MAX VCC Supply voltage V VIH VIL High-level input voltage Low-level input voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC 0.7 VCC 0.7 VCC = 3 V to 3.6 V VCC 0.7 VCC 0.7 VCC = 4.5 V to 5.5 V VCC 0.7 VCC 0.7 VCC = 2 V VCC = 2.3 V to 2.7 V VCC 0.3 VCC 0.3 VCC = 3 V to 3.6 V VCC 0.3 VCC 0.3 VCC = 4.5 V to 5.5 V VCC 0.3 VCC 0.3 VI Input voltage V VO Output voltage 0 VCC 0 VCC V IOH IOL High-level output current Low-level output current VCC = 2 V µa VCC = 2.3 V to 2.7 V 2 2 VCC = 3 V to 3.6 V 6 6 ma VCC = 4.5 V to 5.5 V VCC = 2 V µa VCC = 2.3 V to 2.7 V 2 2 VCC = 3 V to 3.6 V 6 6 ma VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V t/ v Input traition rise or fall rate VCC = 3 V to 3.6 V /V VCC = 4.5 V to 5.5 V TA Operating free-air temperature C NOTE 5: All unused inputs of the device must be held at VCC or GND to eure proper device operation. Refer to the TI application report, Implicatio of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH VOL SN54LV164A SN74LV164A MIN TYP MAX MIN TYP MAX IOH = 50 µa 2 V to 5.5 V VCC 0.1 VCC 0.1 IOH = 2 ma 2.3 V 2 2 IOH = 6 ma 3 V IOH = 12 ma 4.5 V IOL = 50 µa 2 V to 5.5 V IOL = 2 ma 2.3 V IOL = 6 ma 3 V IOL = 12 ma 4.5 V II VI = 5.5 V or GND 0 to 5.5 V ±1 ±1 µa ICC VI = VCC or GND, IO = V µa Ioff VI or VO = 0 to 5.5 V µa Ci VI = VCC or GND 3.3 V pf V V V V POST OFFICE BOX DALLAS, TEXAS

6 SCLS403H APRIL 1998 REVISED APRIL 2005 timing requirements over recommended operating free-air temperature range, V CC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) tw tsu Pulse duration Setup time TA = 25 C SN54LV164A SN74LV164A MIN MAX MIN MAX MIN MAX low CLK high or low Data before CLK inactive th Hold time Data after CLK timing requirements over recommended operating free-air temperature range, V CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) tw tsu Pulse duration Setup time TA = 25 C SN54LV164A SN74LV164A MIN MAX MIN MAX MIN MAX low CLK high or low Data before CLK inactive th Hold time Data after CLK timing requirements over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) tw tsu Pulse duration Setup time TA = 25 C SN54LV164A SN74LV164A MIN MAX MIN MAX MIN MAX low CLK high or low Data before CLK inactive th Hold time Data after CLK switching characteristics over recommended operating free-air temperature range, V CC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) FROM TO LOAD TA = 25 C SN54LV164A SN74LV164A PARAMETER (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX CL = 15 pf 55* 105* 50* 50 fmax CL = 50 pf tpd CLK Q 9.2* 17.6* 1* 20* 1 20 CL = 15 pf tphl Q 8.6* 16* 1* 18* 1 18 tpd CLK Q CL = 50 pf tphl Q * On products compliant to MIL-PRF-38535, this parameter is not production tested. MHz 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 SCLS403H APRIL 1998 REVISED APRIL 2005 switching characteristics over recommended operating free-air temperature range, V CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO LOAD TA = 25 C SN54LV164A SN74LV164A (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX fmax CL = 15 pf 80* 155* 65* 65 CL = 50 pf tpd CLK 6.4* 12.8* 1* 15* 1 15 Q CL = 15 pf tphl 6* 12.8* 1* 15* 1 15 tpd CLK Q CL = 50 pf tphl * On products compliant to MIL-PRF-38535, this parameter is not production tested. MHz switching characteristics over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO LOAD TA = 25 C SN54LV164A SN74LV164A (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX fmax CL = 15 pf 125* 220* 105* 105 CL = 50 pf tpd CLK 4.5* 9* 1* 10.5* Q CL = 15 pf tphl 4.2* 8.6* 1* 10* 1 10 tpd CLK Q CL = 50 pf tphl * On products compliant to MIL-PRF-38535, this parameter is not production tested. MHz noise characteristics, V CC = 3.3 V, C L = 50 pf, T A = 25 C (see Note 6) SN74LV164A PARAMETER MIN TYP MAX VOL(P) Quiet output, maximum dynamic VOL V VOL(V) Quiet output, minimum dynamic VOL V VOH(V) Quiet output, minimum dynamic VOH 3.09 V VIH(D) High-level dynamic input voltage 2.31 V VIL(D) Low-level dynamic input voltage 0.99 V NOTE 6: Characteristics are for surface-mount packages only. operating characteristics, T A = 25 C PARAMETER TEST CONDITIONS VCC TYP 3.3 V 48.1 Cpd Power dissipation capacitance CL = 50 pf, f = 10 MHz pf 5 V 47.5 POST OFFICE BOX DALLAS, TEXAS

8 SCLS403H APRIL 1998 REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) RL = 1 kω S1 VCC Open GND TEST tplh/tphl tplz/tpzl tphz/tpzh Open Drain S1 Open VCC GND VCC LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS Input tw VOLTAGE WAVEFORMS PULSE DURATION VCC 0 V Timing Input Data Input tsu th VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 0 V VCC 0 V Input VCC 0 V Output Control VCC 0 V In-Phase Output Out-of-Phase Output tplh tphl tphl VOH VOL tplh VOH VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 1 S1 at VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tpzl tpzh tplz VOL V VOL tphz VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VCC VOH VOH 0.3 V 0 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditio such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 Ω, tr 3, tf 3. D. The outputs are measured one at a time, with one input traition per measurement. E. tplz and tphz are the same as tdis. F. tpzl and tpzh are the same as ten. G. tphl and tplh are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX DALLAS, TEXAS 75265

9 PACKAGE OPTION ADDENDUM 9-Aug-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pi Package Qty SN74LV164AD ACTIVE SOIC D Green (RoHS & SN74LV164ADBR ACTIVE SSOP DB Green (RoHS & SN74LV164ADBRE4 ACTIVE SSOP DB Green (RoHS & SN74LV164ADE4 ACTIVE SOIC D Green (RoHS & SN74LV164ADGVR ACTIVE TVSOP DGV Green (RoHS & SN74LV164ADGVRE4 ACTIVE TVSOP DGV Green (RoHS & SN74LV164ADR ACTIVE SOIC D Green (RoHS & SN74LV164ADRE4 ACTIVE SOIC D Green (RoHS & SN74LV164ANSR ACTIVE SO NS Green (RoHS & SN74LV164ANSRE4 ACTIVE SO NS Green (RoHS & SN74LV164APW ACTIVE TSSOP PW Green (RoHS & SN74LV164APWG4 ACTIVE TSSOP PW Green (RoHS & SN74LV164APWR ACTIVE TSSOP PW Green (RoHS & SN74LV164APWRG4 ACTIVE TSSOP PW Green (RoHS & SN74LV164APWT ACTIVE TSSOP PW Green (RoHS & SN74LV164APWTE4 ACTIVE TSSOP PW Green (RoHS & SN74LV164ARGYR ACTIVE QFN RGY Green (RoHS & Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Level-2-260C-1YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new desig. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new desig. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1

10 PACKAGE OPTION ADDENDUM 9-Aug-2005 (3) MSL, Peak Temp. -- The Moisture Seitivity Level rating according to the JEDEC industry standard classificatio, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers coider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

11 MECHANICAL DATA MPDS006C FEBRUARY 1996 REVISED AUGUST 2000 DGV (R-PDSO-G**) 24 PINS SHOWN PLASTIC SMALL-OUTLINE 0,40 0,23 0,13 0,07 M ,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 1 12 A 0 8 0,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,08 DIM PINS ** A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11, /E 08/00 NOTES: A. All linear dimeio are in millimeters. B. This drawing is subject to change without notice. C. Body dimeio do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pi MO /16/20/56 Pi MO-194 POST OFFICE BOX DALLAS, TEXAS 75265

15 MECHANICAL DATA MSSO002E JANUARY 1995 REVISED DECEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN PLASTIC SMALL-OUTLINE 0,65 0,38 0,22 0,15 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane ,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,10 DIM PINS ** A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12, /E 12/01 NOTES: A. All linear dimeio are in millimeters. B. This drawing is subject to change without notice. C. Body dimeio do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 POST OFFICE BOX DALLAS, TEXAS 75265

16 MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,10 M 0, ,50 4,30 6,60 6,20 0,15 NOM Gage Plane 1 A ,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 DIM PINS ** A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 01/97 NOTES: A. All linear dimeio are in millimeters. B. This drawing is subject to change without notice. C. Body dimeio do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 POST OFFICE BOX DALLAS, TEXAS 75265

17 IMPORTANT NOTICE Texas Itruments Incorporated and its subsidiaries (TI) reserve the right to make correctio, modificatio, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditio of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applicatio assistance or customer product design. Customers are respoible for their products and applicatio using TI components. To minimize the risks associated with customer products and applicatio, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any licee, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not cotitute a licee from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a licee from a third party under the patents or other intellectual property of the third party, or a licee from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditio, limitatio, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not respoible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not respoible or liable for any such statements. Following are URLs where you can obtain information on other Texas Itruments products and application solutio: Products Applicatio Amplifiers amplifier.ti.com Audio Data Converters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Telephony Video & Imaging Wireless Mailing Address: Texas Itruments Post Office Box Dallas, Texas Copyright 2005, Texas Itruments Incorporated

SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR 2-V to 5.5-V V CC Operation Typical V OLP (Output Ground Bounce) 2.3 V at V CC = 3.3 V, T A = 25 C Support Mixed-Mode Voltage