High-Speed, Low-Glitch D/CMOS Analog Switches

Transcription

1 High-Speed, Low-Glitch /CMOS Analog Switches G/2/3 Fast Switching t ON : 2 ns Low Charge Injection: 2 pc Wide Bandwidth: MHz -V CMOS Logic Compatible Low r S(on) : 8 Low Quiescent Power :.2 nw Single Supply Operation Improved ata Throughput Minimal Switching Transients Improved System Performance Easily Interfaced Low Insertion Loss Minimal Power Consumption Fast Sample-and-Holds Synchronous emodulators Pixel-Rate Video Switching isk/tape rives AC eglitching Switched Capacitor Filters GaAs FET rivers Satellite Receivers The G/2/3 feature high-speed low-capacitance lateral MOS switches. Charge injection has been minimized to optimize performance in fast sample-and-hold applications. Each switch conducts equally well in both directions when on and blocks up to V p-p when off. Capacitances have been minimized to ensure fast switching and low-glitch energy. To achieve such fast and clean switching performance, the G/2/3 are built on the proprietary /CMOS process. This process combines n-channel MOS switching FETs with low-power CMOS control logic and drivers. An epitaxial layer prevents latchup. The G and G2 differ only in that they respond to opposite logic levels. The versatile G3 has two normally open and two normally closed switches. It can be given various configurations, including four SPST, two SPT, one PT. For additional information see Applications Note AN7 (FaxBack number 7). G IN IN S 3 ual-in-line and SOIC 3 Top View 2 S S IN 8 9 IN 3 G IN IN 2 2 Key S 8 7 LCC Top View 7 S 8 S IN IN 3 3 Four SPST Switches per Package Logic G G2 ON OFF OFF ON Logic V Logic V S-399 Rev. G, 3-Sep-99 FaxBack

2 G/2/3 G3 G3 IN IN S 3 ual-in-line and SOIC 3 Top View 2 S S IN 8 9 IN 3 Key S 7 S 8 IN IN LCC Top View IN IN S 3 Four SPST Switches per Package Logic SW, SW SW 2, SW 3 OFF ON ON OFF Logic V Logic V Temp Range Package Part Number G/2 to 8 C to 2 C G3 to 8 C to 2 C -Pin Plastic IP -Pin Narrow SOIC -Pin CerIP LCC- -Pin Plastic IP -Pin Narrow SOIC -Pin CerIP LCC- GJ G2J GY G2Y GAK/883, MEA G2AK/883, MEA GAZ/883, M2A G2AZ/883, M2A G3J G3Y G3AK/883, MEA G3AZ/883, M2A to V to 2 V to V to 2 V to V to.3 V to V to () + V or ma, whichever occurs first V a IN () V to () + V or ma, whichever occurs first V S, V a ().3 V to () + V or ma, whichever occurs first Continuous Current (Any Terminal) ma Current, S or (Pulsed at s, % uty Cycle) ma Storage Temperature: CerIP to C Plastic to 2 C Power issipation (Package)b -Pin Plastic IP c mw -Pin Narrow SOIC d mw -Pin CerIP e mw -Pin LCC e mw Notes: a. Signals on S X, X, or IN X exceeding or will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC Board. c. erate mw/ C above 7 C d. erate 7. mw/ C above 7 C e. erate 2 mw/ C above 7 C V to 2 V V to V V to FaxBack V IN V to V ANALOG to () V S-399 Rev. G, 3-Sep-99

3 G/2/3 Parameter Analog Switch Symbol Test Conditions A Suffix Suffix Unless Otherwise Specified to 2 C to 8 C, = V, V IN = V, V f Temp b Typ c Min d Max d Min d Max d Unit Analog Signal Range e V ANALOG = V, = 2 V 7 7 V Switch On-Resistance r S(on) I S = ma, V = V Resistance r Match Bet Ch. S(on) Source Off Leakage I S(off) V S = V, V = V rain Off Leakage Current Switch On Leakage Current igital Control I (off) I (on) V S = V, V = V V S = V = V 2 Hot Hot Hot Input Voltage High V IH Input Voltage Low V IL Input Current I IN Hot. Input Capacitance C IN pf ynamic Characteristics Off State Input Capacitance C S(off) V S = V 3 Off State Output Capacitance C (off) V = V 2 pf On State Input Capacitance C S(on) V S = V = V Bandwidth BW R L = MHz Turn-On Time e t ON RL = 3, C L = 3 pf, V S = 2 V Turn-Off Time e t OFF L L S See Test Circuit, Figure 2 8 Turn-On Time t ON RL = 3, C L = 7 pf V S = 2 V Turn-Off Time t OFF See Test Circuit, Figure 2 Charge Injection e Q C L = nf, V S = V Ch. Injection Change e, g Q C L = nf, V S 3 V 3 Off Isolation e OIRR R IN =, R L = f = MHz 7 Crosstalk e X TALK R IN =, R L =, f = MHz 87 Power Supplies na V A ns pc db Positive Supply Curent I+. Negative I Supply Current V IN = V or V Logic Supply Current I L.. A Ground Current I. S-399 Rev. G, 3-Sep-99 FaxBack

4 G/2/3 Parameter Analog Switch Symbol Test Conditions Unless Otherwise Specified A Suffix to 2 C Suffix to 8 C, = V, V IN = V, V f Temp b Typ c Min d Max d Min d Max d Unit Analog Signal Range e V ANALOG 7 7 V Switch On-Resistance r S(on) I S = ma, V = V 2 ynamic Characteristics Turn-On Time e t ON RL L = 3, C L = 3 pf, V S= 2 V Turn-Off Time e t OFF See Test Circuit, Figure ns Notes: a. Refer to PROCESS OPTION FLOWCHART. b. = 2 C, = as determined by the operating temperature suffix. c. Typical values are for ESIGN AI ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. e. Guaranteed by design, not subject to production test. f. V IN = input voltage to perform proper function. g. Q = Q at V S = 3 V Q at V S = 3 V. FaxBack S-399 Rev. G, 3-Sep-99

5 G/2/3 ) rs(on) rain-source On-Resistance ( r S(on) vs. V and Power Supply Voltages I S = ma = V = V = 2 V = V ) rs(on) rain-source On-Resistance ( I S = ma r S(on) vs. V and Temperature 2 C 2 C C V rain Voltage (V) V rain Voltage (V) 3 Leakage Current vs. Analog Voltage na Leakage Currents vs. Temperature 2 na Leakage Current (pa), I I S 2 I S(off), I (off) I (on) Leakage (A) I S(off), I (off) pa pa pa I (on) I S(off), I (off) V or V S rain or Source Voltage (V). pa Temperature ( C) Input Switching Threshold vs. 2 Switching Times vs. Temperature 22 Logic Input Voltage (V) V TH 3 2 Time (ns) t OFF t ON R L = 3 C L = pf Logic Supply Voltage (V) Temperature ( C) S-399 Rev. G, 3-Sep-99 FaxBack

6 G/2/3 Charge Injection vs. Analog Voltage Crosstalk and Off Isolation vs. Frequency Qd Charge (pc) Qs (db) 8 Crosstalk Off Isolation V ANALOG Analog Voltage (V) f Frequency (MHz) Insertion Loss (db) db Bandwidth/Insertion Loss vs. Frequency R L = 3 db Point Supply Current (ma) Supply Currents vs. Switching Frequency = V C X =, V I+ I I L 3 2 k k k M M f Frequency (MHz) f Frequency (Hz) S IN X Input Logic Level Translator river MOS Switch FIGURE. FaxBack S-399 Rev. G, 3-Sep-99

7 G/2/3 2 V + V S IN + V R L 3 V O C L V Logic Input V V S = 2 V Switch Output V % % 9% t r < ns t f < ns t ON t OFF C L (includes fixture and stray capacitance) FIGURE 2. Switching Time V O = V S R L R L + r S(on) C + V + V C + V + V V S S V g R g V S IN V O C L nf R g = V, V V, V IN 2 IN 2 C V O R L 3 V X TALK Isolation = log C = RF bypass V S V O 3 V FIGURE 3. Charge Injection FIGURE. Crosstalk High-Speed Sample-and-Hold In a fast sample-and-hold application, the analog switch characteristics are critical. A fast switch reduces aperture uncertainty. A low charge injection eliminates offset (step) errors. A low leakage reduces droop errors. The CLC, a fast input buffer, helps to shorten acquisition and settling times. A low leakage, low dielectric absorption hold capacitor must be used. Polycarbonate, polystyrene and polypropylene are good choices. The JFET output buffer reduces droop due to its low input bias current. (See Figure.) GaAs FET rivers Figure 7 illustrates a high-speed GaAs FET driver. To turn the GaAs FET on V are applied to its gate via S, whereas to turn it off, 8 V are applied via. This high-speed, low-power driver is especially suited for applications that require a large number of RF switches, such as phased array radars. Pixel-Rate Switch Windows, picture-in-picture, title overlays are economically generated using a high-speed analog switch such as the G3. For this application the two video sources must be sync locked. The glitch-less analog switch eliminates halos. (See Figure.) S-399 Rev. G, 3-Sep-99 FaxBack

8 G/2/3 Input Buffer + V +2 V Output Buffer Analog Input 7 CLC S + LF3 V Output to A/ V Control IN / G C HOL pf Polystyrene V FIGURE. High-Speed Sample-and-Hold Background 7 / 2 CLC + V +2 V Output Buffer + CLC 7 Composite Output Titles V Control / 2 G3 V FIGURE. A Pixel-Rate Switch Creates Title Overlays + V S RF IN GaAs RF OUT IN / 2 G3 2 V IN 2 8 V FIGURE 7. A High-Speed GaAs FET river that Saves Power FaxBack S-399 Rev. G, 3-Sep-99