! RC Charging. " RC Step Response Curve. ! What is the C? " Capacitive Load on Gate Output. ! What is the R? " Equivalent Output Resistance

Transcription

1 ESE70: Circuit-Level Modeling, Design, and Optimization for Digital Systems Delay is RC Charging Lec 5: September, 05 Delay and RC Response Delay is RC Charging Today Strategy:! RC Charging! Use zero-order model to understand switch state! reak into output/ input stages! For each stage " RC Step Response Curve! What is the C? " Capacitive Load on Gate put! What is the R? " Equivalent put Resistance! pproximating and Measuring Delay " Understand R drive " Understand C load 4 90% Rise Time? What does response look like? What is time constant, τ? ~ ps for 90% rise 5 6

2 Governing Equations? (KCL) Governing Equations? (KCL) I C! V measure " Kirchoff s Current Law " Sum of all currents into a node = 0 " Current entering a node = current exiting a node! V measure " Kirchoff s Current Law " Sum of all currents into a node = 0 " Current entering a node = current exiting a node " =I C 7 8 Governing Equations? (KCL) Governing Equations? (KCL) I C I C = I C V R = C dv C R dt V in V measure = C dv measure R dt 9 = I C V R = C dv C R dt V in V measure = C dv measure R dt 0 = dv measure dt V measure = V in τ = RC + RC V measure V in RC ( ( e t/rc )) 0 What does look like? Shape of Curve t (in ps) e -t/rc -e -t/rc V measure = V in ( ( e t/rc )) V in = V measure = V in ( ( e t/rc ))

3 Shape of Curve Rise Time: 0 90% t (in ps) e -t/rc -e -t/rc /e = /e = % 90% V in = V measure = V in ( ( e t/rc )) T rise ~=.ps ~=.τ 4 Rise Time: 0 90% What is C? τ=rc T rise ~=.ps ~=.τ 5 6 Capacitance Fanout! Wire! Number of things to which a gate output connects! Fanout -- Total gate load " Logical Gate " MOSFET gate 7 8

4 ! put routed to many gate inputs

5 MOSFET Capacitance First Order Model! load of? " Capacitive! Switch " Loads input capacitively 5 6 MOSFET Capacitance First Order Model! load of? " Capacitive! Switch " Loads input capacitively! s we dig into the device structure understand: " Origin of capacitance " How to engineer device parameters like C g, R ON, V th " Tradeoffs 7 8 Lumped Capacitive Load What is R? C load = C gi + C wi i fanout i wires 9 0 5

6 Resistance First Order Model! Wire resistance " From supply (Vdd or Gnd) to transistor source " From transistor output to gate it is driving! Transistor equivalent resistance (R on )! Switch " Resistive driver! s we dig into the device structure understand: " More sophisticated view, not just R ON " How to engineer device parameters like C g, R ON, V th " Tradeoffs Equivalent Resistance Equivalent Resistance! What resistances might transistors contribute? " How many cases? " ssume R on =R on,p =R on,n 4 Equivalent Resistance Equivalent Resistance! What resistances might transistors contribute? " How many cases?! What resistances might transistors contribute? " How many cases? " ssume R on =R on,p =R on,n " ssume R on =R on,p =R on,n Input Rout Input Rout 00 R on / 0 R on 0 R on R on 5 6 6

7 Rise/Fall Times Lumped Resistive Source! Rise and Fall time may differ " Why? " What is ratio? " R drive = R tr,net + i wires R wi Input Rout 00 R on / 0 R on 0 R on R tr,net = transistor network resistance = parallel and series combination of R tr R on 7 8 Voltage Waveform at Input/put Node R drive from output stages and wires C Load from input stages and wires Measuring Delay 9 40 Measuring Gate Delay Characterizing Gate/Technology 67ps 80ps t del = ps! Delay measure will be " Function of load on gate " Function of input rise time " Which, in turn, may be a function of input loading! Next stage starts to switch before first finishes! Measure from 50% of input swing to 50% of output swing 4 4 7

8 Delay vs. Risetime ps rise 00ps rise Characterizing Gate/Technology! Delay measure will be " Function of load on gate " Function of input rise time " Which, in turn, may be a function of input loading! Want to understand typical delay times " llows us to compare designs with a (somewhat) normalized delay metric 0ps delay 0ps delay! If we didn t know the input rise time, we wouldn t know what a ps delay meant 4 44 Standard Measurement for Characterization HW Measurement Setup! Drive with a gate " Not an ideal source " Input rise time typically would see in circuit! Measure loaded gate " Typical loading FO4 Function Generator Oscilloscope Not realistic measurement Measurement for Characterization Measurement for Characterization! Drive with a gate! Drive with a gate " Not an ideal source (how does delay change if drive is ideal?) " Not an ideal source " Input rise time typically would see in circuit " Input rise time typically would see in circuit! Measure loaded gate " Typical loading FO4! Measure loaded gate " Typical loading FO4 (how does delay change if gate is unloaded?)

9 Delay is RC Charging dmin! Normal Week " Lecture Week (all here) " MOS Operation and Devices! Spice Flow " access to electric, setup for spice, run ngspice dmin! Normal Week " Lecture Week (all here) " MOS Operation and Devices! Spice Flow " access to electric, setup for spice, run ngspice! HW quality " Show your work " Label axes, explain your results " If we can t understand it, we can t grade it! HW turnin " Must turn in by the time I start lecturing (:05) " Won t accept any more after that 5 9