750 MHz, 8 8 Analog Crosspoint Switch ADV3228/ADV3229

Transcription

1 75 MHz, Analog Crosspoint Switch ADV/ADV9 FEATURES FUNCTIONAL BLOCK DIAGRAM high speed, nonblocking switch array Pinout and functionally equivalent to the AD/AD9 Drop-in compatible with ADV/ADV5 6 array Complete solution Buffered inputs Programmable high impedance outputs output amplifiers, G = + (ADV), G = + (ADV9) Drives 5 Ω loads Operates on ±5 V supplies Low power:.5 W Excellent ac performance db bandwidth mv p-p: MHz (ADV), 9 MHz (ADV9) V p-p: 75 MHz (ADV), 5 MHz (ADV9).5 db flatness ( V p-p): 5 MHz (ADV), 5 MHz (ADV9) Slew rate: 5 V/μs Serial or parallel programming of switch array 7-lead LFCSP ( mm mm) APPLICATIONS DATAIN CE RESET INPUTS SER/PAR ADV/ ADV9 D D D D -BIT SHIFT REGISTER WITH -BIT PARALLEL LOADING PARALLEL LATCH (RESERVED) DECODE : DECODERS 6 SWITCH SET INDIVIDUAL OR RESET ALL OUTPUTS TO OFF OUTPUT BUFFER G = +, G = + ENABLED/DISABLED A A A DATAOUT OUTPUTS Routing of high speed signals including Video (NTSC, PAL, S, SECAM, YUV, RGB) Compressed video (MPEG, wavelet) -level digital video (HDB) Data communications Telecommunications Figure. 9- GENERAL DESCRIPTION The ADV/ADV9 are high speed analog crosspoint switch matrices. They offer a db large signal bandwidth of 75 MHz (ADV) and a slew rate of 5 V/μs. The ADV/ADV9 include eight independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs to prevent off channels from loading the output bus. The ADV has a gain of +, the ADV9 has a gain of +, and they both operate on voltage supplies of ±5 V. Channel switching is performed via a serial digital control that can accommodate daisy chaining of several devices or via a parallel control to allow updating of an individual output without reprogramming the entire array. The ADV/ADV9 are available in the 7-lead LFCSP package over the extended industrial temperature range of C to +5 C. Rev. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: 7.6. Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Revision History... Specifications... Timing Characteristics (Serial)... 5 Logic Levels... 5 Timing Characteristics (Parallel)... 6 Absolute Maximum Ratings... 7 Thermal Resistance... 7 Power Dissipation... 7 ESD Caution... 7 Pin Configuration and Function Descriptions... Truth Table and Logic Diagram... Typical Performance Characteristics... Circuit Diagrams... Theory of Operation... Applications Information... Serial Programming... Parallel Programming... Power-On Reset... Gain Selection... Creating Larger Crosspoint Arrays... Outline Dimensions... Ordering Guide... REVISION HISTORY / Revision : Initial Version Rev. Page of

3 SPECIFICATIONS VS = ±5 V, TA = 5 C, RL = 5 Ω, unless otherwise noted. Table. ADV ADV9 Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE db Bandwidth mv p-p 9 MHz V p-p 75 5 MHz Gain Flatness. db, V p-p 55 5 MHz.5 db, V p-p 5 5 MHz Propagation Delay V p-p.6.6 ns Settling Time %, V step ns Slew Rate V step, peak 5 5 V/μs NOISE/DISTORTION PERFORMANCE Differential Gain Error NTSC or PAL.. % Differential Phase Error NTSC or PAL.. Degrees Crosstalk, All Hostile, RTO f = MHz 5 5 db f = 5 MHz 7 7 db Off Isolation, Input to Output f = MHz, one channel 7 db OIP f = MHz, RL = Ω dbm f = 5 MHz, RL = Ω 5 dbm OIP f = MHz, RL = Ω dbm f = 5 MHz, RL = Ω 7 dbm Output db Compression Point f = MHz, RL = Ω 9 dbm f = 5 MHz, RL = Ω dbm Input Voltage Noise Density 5 MHz nv/ Hz DC PERFORMANCE Gain Error % Gain Matching Channel-to-channel.5.5 % Gain Temperature Coefficient.5 5 ppm/ C OUTPUT CHARACTERISTICS Output Resistance DC, enabled.. Ω DC, disabled 5 MΩ Output Disabled Capacitance..6 pf Output Leakage Current Output disabled.5.5 μa Output Voltage Range No load ± ± V RL = 5 Ω ±. ±. V Short-Circuit Current ma INPUT CHARACTERISTICS Input Offset Voltage Worst case (all configurations) ±5 ±5 mv Input Offset Voltage Drift 5 5 μv/ C Input Voltage Range ± ±.5 V Input Capacitance Any switch configuration.. pf Input Resistance MΩ Input Bias Current Any switch configuration ± ± μa SWITCHING CHARACTERISTICS Enable/Disable Time 5% to % settling ns Switching Time, V Step 5% to % settling ns Switching Transient (Glitch) 5 5 mv p-p Rev. Page of

4 ADV ADV9 Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit POWER SUPPLIES Supply Current, outputs enabled, no load ma, outputs disabled ma, outputs enabled, no load ma, outputs disabled ma DVCC, outputs enabled, no load 6 6 ma Supply Voltage Range ±.5 ±5 ±5.5 ±.5 ±5 ±5.5 V PSRR DC to 5 khz,, < 6 < 6 db f = khz,, 6 6 db f = MHz, 5 db f = MHz, 5 55 db f = MHz, 5 5 db f = MHz, 5 5 db f = khz, DVCC 9 9 db OPERATING TEMPERATURE RANGE Temperature Range Operating (still air) C θja Operating (still air) 9 9 C/W Rev. Page of

5 TIMING CHARACTERISTICS (SERIAL) Table. Parameter Symbol Min Typ Max Unit Serial Data Setup Time t ns Pulse Width t ns Serial Data Hold Time t ns Pulse Separation, Serial Mode t ns to Delay t5 ns Pulse Width t6 ns to DATAOUT Valid, Serial Mode t7 5 ns Propagation Delay, to Switch On or Off ns Data Load Time, = 5 MHz, Serial Mode μs, Rise and Fall Times 5 ns RESET Time ns Timing Diagram Serial Mode t t t t LOAD DATA INTO SERIAL REGISTER ON FALLING EDGE DATAIN OUT7 (D) OUT7 (RESERVED) OUT (D) = LATCHED = TRANSPARENT t 7 t 5 TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL t 6 DATAOUT Figure. Timing Diagram, Serial Mode 9- LOGIC LEVELS Table. Logic Levels VIH VIL VOH VOL IIH IIL IIH IIL IOH IOL RESET, SER/PAR,, DATA IN, CE, RESET, SER/PAR,, DATA IN, CE, DATA OUT DATA OUT SER/PAR,, DATA IN, CE, SER/PAR,, DATA IN, CE, RESET RESET DATA OUT DATA OUT. V min. V max. V min. V max μa max μa max μa max μa max ma min ma min Rev. Page 5 of

6 TIMING CHARACTERISTICS (PARALLEL) Table. Parameter Symbol Min Typ Max Unit Parallel Data Setup Time td ns Address Setup Time ta ns Pulse Width t ns Parallel Data Hold Time td ns Address Hold Time ta ns Pulse Separation t ns Pulse Width t5 ns, Rise and Fall Times 5 ns RESET Time ns Timing Diagram Parallel Mode A TO A D TO D = LATCHED = TRANSPARENT t a t t t a t d t d Figure. Timing Diagram, Parallel Mode t 5 9- Rev. Page 6 of

7 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Supply Voltage ( to ) Digital Supply Voltage (DVCC to DGND) Supply Potential Difference ( to DVCC) Ground Potential Difference (AGND to DGND) Maximum Potential Difference (DVCC to ) Analog Input Voltage Digital Input Voltage Exposed Paddle Voltage Output Voltage (Disabled Analog Output) Output Short-Circuit Duration Current Rating V 6 V ±.5 V ±.5 V 6 V < VIN < DGND < DIN < DVCC AGND < VOUT < Momentary Internally limited to 55 ma Temperature Storage Temperature Range 65 C to +5 C Operating Temperature Range C to +5 C Junction Temperature 5 C Lead Temperature C (Soldering, sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance Package Type θja θjc Unit 7-Lead LFCSP_V 9.5 C/W POWER DISSIPATION The ADV/ADV9 operate with ±5 V supplies and can drive loads down to Ω, resulting in a wide range of possible power dissipations. For this reason, extra care must be taken when derating the operating conditions based on ambient temperature. Packaged in the 7-lead LFCSP, the ADV/ADV9 junctionto-ambient thermal impedance (θja) is 9 C/W. For long-term reliability, the maximum allowed junction temperature of the die should not exceed 5 C; even temporarily exceeding this limit can cause a shift in parametric performance due to a change in stresses exerted on the die by the package. Exceeding a junction temperature of 5 C for an extended period can result in device failure. In Figure, the curve shows the range of allowed internal die power dissipation that meets these conditions over the C to +5 C ambient temperature range. When using Figure, do not include the external load power in the maximum power calculation, but do include the load current dropped on the die output transistors. MAXIMUM POWER DISSIPATION (W) T J = 5 C 6 AMBIENT TEMPERATURE ( C) Figure. Maximum Die Power Dissipation vs. Ambient Temperature ESD CAUTION 9- Rev. Page 7 of

8 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN IN IN IN IN IN5 IN6 IN7 AGND ADV/ADV9 TOP VIEW (Not to Scale) DGND RESET CE DATAOUT DATAIN SER/PAR A A A D D D D NC DGND DVCC OUT7 OUT6 OUT5 OUT OUT OUT OUT OUT AGND NC NC NC NC NC NC NC NC AGND DVCC PIN INDICATOR NOTES. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.. EXPOSED PADDLE. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE MUST BE SOLDERED TO THE PCB AGND FOR PROPER HEAT DISSIPATION AND FOR NOISE AND MECHANICAL STRENGTH BENEFITS. Figure 5. Pin Configuration 9-5 Table 7. Pin Function Descriptions Pin No. Mnemonic Description, 5, 9,, 9,, 7,, 5, 6, 6, 6 Analog Positive Supply. IN Input Number., 7,, 5,,, 5, 9,, 6, 5, 6, 66, 7 Analog Negative Supply. IN Input Number. 6 IN Input Number. IN Input Number. IN Input Number. IN5 Input Number 5. IN6 Input Number 6. 6 IN7 Input Number 7. 7, 56, 7 AGND Analog Ground. OUT7 Output Number 7. OUT6 Output Number 6. OUT5 Output Number 5. 6 OUT Output Number. OUT Output Number. OUT Output Number. OUT Output Number. OUT Output Number. 7, 55 DVCC Digital Positive Supply., 5 DGND Digital Ground. 9, 57, 59, 6, 6, 65, 67, 69, 7 NC No Internal Connection. Rev. Page of

9 Pin No. Mnemonic Description to D, D, D, D Parallel Data Input. to 6 A, A, A Parallel Output Address Input. 7 SER/PAR Serial/Parallel Mode Select (Control Pin). Second Rank Write Strobe (Control Pin). 9 DATAIN Serial Data In (Control Pin). 5 Serial Data Clock, Parallel First Rank Latch Enable (Control Pin). 5 DATAOUT Serial Data Out. 5 CE Chip Enable (Control Pin). 5 RESET Second Rank Reset (Control Pin). EPAD Exposed Paddle. The exposed metal paddle on the bottom of the LFCSP package must be soldered to the PCB AGND for proper heat dissipation and for noise and mechanical strength benefits. Rev. Page 9 of

10 TRUTH TABLE AND LOGIC DIAGRAM Table. Operation Truth Table CE DATAIN DATAOUT RESET SER/PAR Description X X X X X X No change in logic. X DataI DataI- X The data on the serial DATAIN line is loaded into the serial register. The first bit clocked into the serial register appears at DATAOUT clock cycles later. X D D Not applicable in parallel mode X The data on the parallel data lines, D to D, are loaded into the -bit serial shift register location addressed at A to A. X X X X Data in the -bit shift register transfers into the parallel latches that control the switch array. Latches are transparent. X X X X X X Asynchronous operation. All outputs are disabled. Second rank latches are cleared. Remainder of logic is unchanged. X is don t care. DataI: serial data. Reserved bit internally set to Logic. DATAOUT remains active in parallel mode and always reflects the state of the MSB of the serial shift register. PARALLEL DATA RESERVED (INTERNALLY SET HIGHT) D D D (OUTPUT ENABLE) D SER/PAR DATAIN (SERIAL) S D D D S D D D S D D D S D D D S D D D S D D D S D D D S D D D S D D D S D D D S D D D S D D D DATA OUT CE OUT EN OUTPUT ADDRESS A A A TO DECODER OUT EN OUT EN OUT EN OUT EN OUT5 EN OUT6 EN OUT7 EN LE D OUT B LE D OUT B LE D OUT B LE D OUT R LE D OUT EN CLR LE D OUT B LE D OUT6 EN CLR LE D OUT7 B LE D OUT7 B LE D OUT7 B LE D OUT7 R LE D OUT7 EN CLR RESET (OUTPUT ENABLE) DECODE SWITCH MATRIX Figure 6. Logic Diagram OUTPUT ENABLE 9-6 Rev. Page of

11 TYPICAL PERFORMANCE CHARACTERISTICS GAIN (db) OUTPUT SIGNAL, UNICAST OUTPUT SIGNAL, BROADCAST V OUT = mv p-p Figure 7. ADV Small Signal Frequency Response 9- GAIN (db) OUTPUT SIGNAL, UNICAST OUTPUT SIGNAL, BROADCAST V OUT = mv p-p Figure. ADV9 Small Signal Frequency Response 9- GAIN (db) OUTPUT SIGNAL, UNICAST OUTPUT SIGNAL, BROADCAST V OUT = V p-p Figure. ADV Large Signal Frequency Response 9-9 GAIN (db) OUTPUT SIGNAL, UNICAST OUTPUT SIGNAL, BROADCAST V OUT = V p-p Figure. ADV9 Large Signal Frequency Response 9- GAIN (db) pF.pF.pF.pF pf V OUT = mv p-p Figure 9. ADV Small Signal Frequency Response with Capacitive Loads 9- GAIN (db).pf 5.pF 9.pF pF pf V OUT = mv p-p Figure. ADV9 Small Signal Frequency Response, RL = 5 Ω 9- Rev. Page of

12 GAIN (db) pF 5.pF.pF.pF pf V OUT = V p-p 9- GAIN (db) pF.pF.pF pf V OUT = V p-p 5.pF 9-7 Figure. ADV Large Signal Frequency Response with Capacitive Loads Figure 6. ADV9 Large Signal Frequency Response with Capacitive Loads.5. INPUT SIGNAL OUTPUT SIGNAL, UNICAST OUTPUT SIGNAL, BROADCAST.5. INPUT OUTPUT SIGNAL, UNICAST OUTPUT SIGNAL, BROADCAST V OUT = mv p-p Figure. ADV Small Signal Pulse Response 9-5 V OUT = mv p-p Figure 7. ADV9 Small Signal Pulse Response INPUT SIGNAL OUTPUT SIGNAL, UNICAST OUTPUT SIGNAL, BROADCAST.5. INPUT OUTPUT SIGNAL, UNICAST OUTPUT SIGNAL, BROADCAST V OUT = V p-p Time (ns) Figure 5. ADV Large Signal Pulse Response 9-6 V OUT = V p-p Figure. ADV9 Large Signal Pulse Response 9-9 Rev. Page of

13 ..5 RISING EDGE PULSE RISING EDGE SLEW RATE SLEW RATE (V/μs) SLEW RATE (V/μs) Figure 9. ADV Rising Edge Slew Rate 9-.5 RISING EDGE PULSE 5 RISING EDGE SLEW RATE Figure. ADV9 Rising Edge Slew Rate FALLING EDGE PULSE FALLING EDGE SLEW RATE FALLING EDGE PULSE FALLING EDGE SLEW RATE Figure. ADV Falling Edge Slew Rate SLEW RATE (V/μs) Figure. ADV9 Falling Edge Slew Rate SLEW RATE (V/μs) OUTPUT INPUT INPUT SIGNAL.5. OUTPUT INPUT.5.5 OUTPUT SIGNAL OUTPUT ERROR (%).5.5 OUTPUT SIGNAL INPUT SIGNAL OUTPUT ERROR (%).. PROPAGATION DELAY NOT SHOWN Figure. ADV Settling Time 9-9 PROPAGATION DELAY NOT SHOWN Figure. ADV9 Settling Time 9-5 Rev. Page of

14 V EE AGGRESSOR V CC AGGRESSOR PSR (db) V CC AGGRESSOR PSR (db) V EE AGGRESSOR 9. k Figure 5. ADV Power Supply Rejection k Figure. ADV9 Power Supply Rejection NOISE (nv/ Hz) 5 5 NOISE (nv/hz) FREUENCY (khz) Figure 6. ADV Output Noise, Ω Load 9- FREUENCY (khz) Figure 9. ADV9 Output Noise, Ω Load ISOLATION (db) 7 9 ISOLATION (db) 6 Figure 7. ADV Off Isolation 9-5 Figure. ADV9 Off Isolation 9-7 Rev. Page of

15 IN-OUT: VICTIM CHANNEL IN-OUT: AGGRESSOR V OUT = V p-p IN-OUT:VICTIM CHANNEL IN-OUT: AGGRESSOR V OUT = V p-p CROSSTALK (db) CROSSTALK (db) Figure. ADV Crosstalk, One Adjacent Channel, RTO 9-9 Figure. ADV9 Crosstalk, One Adjacent Channel, RTO 9- CROSSTALK (db) IN-OUT: VICTIM CHANNEL V OUT = V p-p CROSSTALK (db) IN-OUT: VICTIM CHANNEL V OUT = V p-p Figure. ADV Crosstalk, All Hostile, RTO 9- Figure 5. ADV9 Crosstalk, All Hostile, RTO 9- M M k k IMPEDANCE (Ω) k k IMPEDANCE (Ω) k k. Figure. ADV Input Impedance 9-. Figure 6. ADV9 Input Impedance 9- Rev. Page 5 of

16 M M k k IMPEDANCE (Ω) k k IMPEDANCE (Ω) k k. Figure 7. ADV Output Impedance, Disabled 9-5. Figure. ADV9 Output Impedance, Disabled 9- IMPEDANCE (Ω) IMPEDANCE (Ω).. Figure. ADV Output Impedance, Enabled Figure. ADV9 Output Impedance, Enabled V OUT RISING EDGE.5. V OUT RISING EDGE (V) (V). V OUT FALLING EDGE.5. V OUT FALLING EDGE Figure 9. ADV Switching Time Figure. ADV9 Switching Time 9- Rev. Page 6 of

17 V OUT..5. (V).5.5 V OUT..5. (V) Figure. ADV Switching Glitch Figure 6. ADV9 Switching Glitch V OUT RISING EDGE V OUT FALLING EDGE (V) V OUT RISING EDGE V OUT FALLING EDGE (V) Figure. ADV Enable Time Figure 7. ADV9 Enable Time DIFFERENTIAL GAIN ERROR (%) DIFFERENTIAL GAIN ERROR (%) INPUT DC OFFSET (V) Figure 5. ADV Differential Gain Error INPUT DC OFFSET (V) Figure. ADV9 Differential Gain Error 9-6 Rev. Page 7 of

18 .. DIFFERENTIAL PHASE ERROR (Degrees) DIFFERENTIAL PHASE ERROR (Degrees) INPUT VOLTAGE (V) Figure 9. ADV Differential Phase Error INPUT VOLTAGE (V) Figure 5. ADV9 Differential Phase Error V IN =.5V p-p V IN =.5V p-p VOLTAGE (V) VOLTAGE (V) V OUT AT V IN =.5V p-p V OUT AT V IN =.5V p-p Figure 5. ADV Overdrive Recovery Figure 5. ADV9 Overdrive Recovery 9-55 REF: 5Ω REF: 5Ω db GAIN COMPRESSION (dbm) 6 R L = Ω INPUT 9-5 THIRD-ORDER INTERCEPT (dbm) R L = Ω TONE SPACING: MHz INPUT 9-56 Figure 5. ADV9 db Gain Compression, Ω Load Figure 5. ADV9 Third-Order Intercept, Ω Load Rev. Page of

19 55 5 REF: 5Ω HD, dbm SECOND-ORDER INTERCEPT (dbm) R L = Ω TONE SPACING: MHz INPUT Figure 55. ADV9 Second-Order Intercept, Ω Load 9-57 HARMONIC DISTORTION (dbc) HD, dbm 5 6 HD, dbm 7 HD, dbm 9 R L = Ω INPUT Figure 57. ADV9 Harmonic Distortion, Ω Load NUMBER OF HITS INPUT OFFSET VOLTAGE (mv) Figure 56. ADV and ADV9, Input VOS Distribution 9-59 Rev. Page 9 of

20 CIRCUIT DIAGRAMS INx.pF 9-6 Figure 5. Analog Input OUTx.pF Figure 6. Analog Output Disabled 9-6 OUTx DVCC RESET kω kω Figure 59. Analog Output Enabled 9-6 DGND Figure 6. Reset Input 9-65 DVCC DVCC INx, OUTx, RESET, SER/PAR, CE,, DATAIN, DATAOUT, A[:], D[:] DATAOUT AGND AGND DGND Figure 6. ESD Map 97-6 DGND Figure 6. Logic Output 9-66 A[:], CE,, D[:], DATAIN, SER/PAR, kω DGND Figure 6. Logic Input 9-6 Rev. Page of

21 THEORY OF OPERATION The ADV (G = +) and ADV9 (G = +) are crosspoint arrays with eight outputs, each of which can be connected to any one of eight inputs. Organized by output row, eight switchable input transconductance stages are connected to each output buffer to form -to- multiplexers. There are eight of these multiplexers, each with its inputs wired in parallel, for a total array of 6 transconductance stages forming a multicast-capable crosspoint switch. Each input is buffered and is not loaded by the outputs, simplifying the construction of larger arrays using the ADV or ADV9 as a building block. Decoding logic for each output selects one (or none) of the transconductance stages to drive the output stage. The enabled transconductance stage drives the output stage, and feedback forms a closed-loop amplifier. A mask programmable feedback network sets the closed-loop signal gain. For the ADV, this gain is +, and for the ADV9, this gain is +. The output stage of the ADV or ADV9 is designed for low differential gain and phase error when driving composite video signals. It also provides slew current for a fast pulse response when driving component video signals. Unlike many multiplexer designs, these requirements are balanced such that large signal bandwidth is very similar to small signal bandwidth. The design load is 5 Ω, but provisions are made to drive loads as low as Ω when on-chip power dissipation limits are not exceeded. The outputs of the ADV/ADV9 can be disabled to minimize on-chip power dissipation. When disabled, there is no feedback network loading the output. This high disabled output impedance allows multiple ICs to be bussed together without additional buffering. Take care to reduce output capacitance, which results in more overshoot and frequency domain peaking. A series of internal amplifiers drives internal nodes such that a wideband high impedance is presented at the disabled output, even while the output bus is under large signal swings. To keep these internal amplifiers in their linear range of operation when the outputs are disabled and driven externally, do not allow the voltage applied to them to exceed the valid output swing range for the ADV/ADV9. If the disabled outputs are left floating, they may exhibit high enable glitches. If necessary, the disabled output can be kept from drifting out of range by applying an output load resistor to ground. The connection of the ADV/ADV9 is controlled by a flexible TTL-compatible logic interface. Either parallel or serial loading into a first rank of latches preprograms each output. A global update signal moves the programming data into the second rank of latches, simultaneously updating all outputs. In serial mode, a serial output pin allows devices to be daisy-chained together for single pin programming of multiple ICs. A poweron reset pin is available to avoid bus conflicts by disabling all outputs. This power-on reset clears the second rank of latches but does not clear the first rank of latches. In serial mode, preprogramming individual inputs is not possible, and the entire shift register must be flushed. To easily interface to ground-referenced video signals, the ADV/ADV9 operate on split ±5 V supplies. The logic inputs and output run on a single 5 V supply, and the logic inputs switch at approximately.6 V for compatibility with a variety of logic families. The serial output buffer is a rail-to-rail output stage with 5 ma of drive capability. Rev. Page of

22 APPLICATIONS INFORMATION The ADV/ADV9 have two options for changing the programming of the crosspoint matrix. In the first option, a serial word of bits can be provided, which updates the entire matrix each time the -bit word is shifted into the device. The second option allows for changing the programming of a single output via a parallel interface. The serial option requires fewer signals but more time (clock cycles) for changing the programming, whereas the parallel programming technique requires more signals but can change a single output at a time and requires fewer clock cycles to complete the programming. SERIAL PROGRAMMING The serial programming mode uses the CE,, DATAIN,, and SER/PAR pins. The first step is to assert a low on SER/PAR to enable the serial programming mode. CE for the chip must be low to allow data to be clocked into the device. The CE signal can be used to address an individual device when devices are connected in parallel. The signal should be high during the time that data is shifted into the serial port of the device. Although the data still shifts in when is low, the transparent, asynchronous latches allow the shifting data to reach the matrix, which causes the matrix to try to update to every intermediate state as defined by the shifting data. The data at DATAIN is clocked in at every falling edge of, and a total of bits must be shifted in to fill the register, and thereby, complete the programming. For each of the eight outputs there are five bits in the shift register; the position of these bits in the register determines the output to which they apply (see Figure 6). Three of the bits (D to D) determine the source of the input that connects to the output that pertains to the position in the register; the MSB is shifted in first. The fourth bit (reserved) is a reserved enable bit and must be shifted in as a logic high prior to D to D in all cases (in parallel programming mode this bit is internally set high). The fifth bit (D) precedes these four bits and determines the enabled state of the output. If D is low (output disabled), the four associated bits do not matter because no input switches to that output. The most significant output address data is shifted in first, and the remaining addresses follow in sequence until the least significant output address data is shifted in. At this point, can be taken low, which programs the device according to the data that was just shifted in. The update registers are asynchronous, and when is low (and CE is low), they are transparent. If more than one ADV/ADV9 device is to be serially programmed in a system, the DATAOUT signal from one device can be connected to the DATAIN of the next device to form a serial chain. Connect all of the, CE,, and SER/PAR pins in parallel and operate them as described previously in this section. The serial data is input to the DATAIN pin of the first device of the chain, and it ripples through to the last. Therefore, the data for the last device in the chain should come at the beginning of the programming sequence. The length of the programming sequence ( bits) is multiplied by the number of devices in the chain. PARALLEL PROGRAMMING When using the parallel programming mode, it is not necessary to reprogram the entire device when making changes to the matrix. Parallel programming allows the modification of a single output at a time. Because this takes only one / cycle, significant time savings can be realized by using parallel programming. An important consideration in using parallel programming is that the RESET signal does not reset all registers in the ADV/ ADV9. When taken low, the RESET signal sets each output to the disabled state. This is helpful during power-up to ensure that two parallel outputs are not active at the same time. After initial power-up, the internal registers in the device generally contain random data, even though the RESET signal was asserted. If parallel programming is used to program one output, that output is properly programmed, but the rest of the device has a random program state depending on the internal register content at power-up. Therefore, when using parallel programming, it is essential that all outputs be programmed to a desired state after power-up to ensure that the programming matrix is always in a known state. From this point, parallel programming can be used to modify either a single output or multiple outputs at one time. Similarly, if both CE and are taken low after initial power-up, the random power-up data in the shift register is programmed into the matrix. Therefore, to prevent programming the crosspoint into an unknown state, do not apply low logic levels to both CE and after power is initially applied. To eliminate the possibility of programming the matrix to an unknown state, after initial power-up, program the full shift register one time to a desired state using either serial or parallel programming. To change the programming of an output via parallel programming, take the SER/PAR and pins high, and take the CE pin low. The signal should be in the high state. Place the -bit address of the output to be programmed on A to A. The first three data bits (D to D) contain the information that identifies the input that is programmed to the addressed output. A fourth bit, reserved, is a reserved enable bit and is internally connected to a logic high level in parallel programming mode. The fifth data bit (D) determines the enabled state of the output. If D is low (output disabled), the data bits on D to D do not matter. After the address and data signals are established, they can be latched into the shift register by pulling the signal low; however, the matrix is not programmed until the signal is taken low. In this way, it is possible to latch in new data for several or all of the outputs first via successive negative transitions of while is held high and then have all the new data take effect when goes low. Use this technique when programming the device for the first time after power-up when Rev. Page of

23 using parallel programming. In parallel mode, the pin is level sensitive, whereas in serial mode, it is edge triggered. POWER-ON RESET When powering up the ADV/ADV9, it is usually desirable to have the outputs come up in the disabled state. When taken low, the RESET pin causes all outputs to be in the disabled state. However, the RESET signal does not reset all registers in the ADV/ADV9. This is important when operating in the parallel programming mode. Refer to the Parallel Programming section for information about programming internal registers after power-up. Serial programming programs the entire matrix each time; therefore, no special considerations apply. Because the data in the shift register is random after power-up, it should not be used to program the matrix, or the matrix can enter unknown states. To prevent the matrix from entering unknown states, do not apply logic low signals to both CE and initially after power-up. Instead, first load the shift register with the data and then take low to program the device. The RESET pin has a kω pull-up resistor to DVCC that can be used to create a simple power-up reset circuit. A capacitor from RESET to ground holds the RESET pin low for a period during which the rest of the device stabilizes. The low condition causes all of the outputs to be disabled. The capacitor then charges through the pull-up resistor to the high state, thereby, allowing full programming capability of the device. GAIN SELECTION The crosspoints come in two versions, depending on the gain of the analog circuit path. The ADV device is unity gain and can be used for analog logic switching and other applications where unity gain is desired. The ADV outputs have very high impedance when their outputs are disabled. The ADV9 can be used for devices that drive a terminated cable with its outputs. This device has a built-in gain of + that eliminates the need for a gain of + buffer to drive a video line. Its high output disabled impedance minimizes signal degradation when paralleling additional outputs of other crosspoint devices. CREATING LARGER CROSSPOINT ARRAYS The ADV/ADV9 are high density building blocks for creating crosspoint arrays of dimensions larger than. Various features, such as output disable, chip enable, and gain of + and gain of + options, are useful for creating larger arrays. The first consideration in constructing a larger crosspoint is to determine the minimum number of devices that is required. The architecture of the ADV/ADV9 contains 6 points, which is a factor of 6 greater than a crosspoint (or multiplexer). The benefits realized in printed circuit board (PCB) area used, power consumption, and design effort are readily apparent when compared to using multiples of these smaller devices. To obtain the minimum number of required points for a nonblocking crosspoint, multiply the number of inputs by the number of outputs. Nonblocking requires that the programming of a given input to one or more outputs not restrict the availability of that input to be a source for any other outputs. Some nonblocking crosspoint architectures require more than this minimum. In addition, there are blocking architectures that can be constructed with fewer devices than this minimum. These systems have connectivity available on a statistical basis that is determined when designing the overall system. The basic concept in constructing larger crosspoint arrays is to connect inputs in parallel in a horizontal direction and to wire-or the outputs together in the vertical direction. The wire-or connection can be viewed as a tristate multiplex of the two outputs, in that only one output is enabled and the other is in a high-z state. The meaning of horizontal and vertical can best be understood by referring to Figure 65, which illustrates this concept for a crosspoint array that uses four ADV or ADV9 devices. IN TO IN7 IN TO IN5 IN6 TO IN IN TO IN R TERM R TERM R TERM R TERM ADV OR ADV9 ADV OR ADV9 ADV OR ADV9 ADV OR ADV9 OUT TO OUT7 Figure 65. A Nonblocking Crosspoint Switch Array Each input is uniquely assigned to each of the eight inputs of the four devices and terminated appropriately; the outputs are wired- OR ed together. The output from only one wire-or ed connection can be enabled at any given time, and care must be exercised to minimize load capacitance at the wired-or ed connections. The device programming software must be properly written to prevent multiple connected outputs from being enabled at the same time. More expansion options are possible using the ADV6 and ADV7 wideband 6 6 arrays, and ADV and ADV5 6 arrays. Also available are 6 arrays in a single package: AD, AD5, ADV, and ADV. For a complete array in a single device, use the AD7 and AD for wide bandwidth or the ADV and ADV for less bandwidth. 9-7 Rev. Page of

24 OUTLINE DIMENSIONS PIN INDICATOR. BSC S TOP VIEW 9.75 BSC S BSC EXPOSED PAD 7 PIN INDICATOR.7 BSC S (BOTTOM VIEW) SEATING PLANE MAX.... MAX.65 TYP.5 MAX. NOM COPLANARITY. REF..5 REF COMPLIANT TO JEDEC STANDARDS MO--VNND- Figure Lead Lead Frame Chip Scale Package [LFCSP_V] mm mm Body, Very Thin uad (CP-7-) Dimensions shown in millimeters FORPROPERCONNECTIONOF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET A ORDERING GUIDE Model Temperature Range Package Description Package Option ADVACPZ C to +5 C 7-Lead Lead Frame Chip Scale Package [LFCSP_V] CP-7- ADV-EVALZ Evaluation Board ADV9ACPZ C to +5 C 7-Lead Lead Frame Chip Scale Package [LFCSP_V] CP-7- ADV9-EVALZ Evaluation Board Z = RoHS Compliant Part. Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D9--/() Rev. Page of