CD4066B Types. COS/MOS Quad Bilateral Switch. Features: Applications: Analog signal switching/multiplexing

Transcription

1 COS/MOS Quad Bilateral Switch For Transmission or Multiplexing of Analog or Digital Signals Features: High-Voltage Types (20-Volt Rating) The RCA-CD40668 S a quad bilateral SWitch ntended for the transmission or multiplex ng of analog or digl tal Signals. t is pin-for pin compatible with RCA-CD40168, but exhibits a much lower on-state resistance. n addition, the on-state resistance S relatively constant over the full input-signal range. The CD40668 consists of four independent bilateral SWitches. A Single control Signal is required per SWitch. 80th the p and the n device in a given switch are biased on or off simultaneously by the control signal. As shown in Fig_ 1, the well of the n-channel device on each SWitch S either tied to the input when the switch is on or to VSS when the switch S off. This configuration eliminates the variation of the SWitch-tranSistor threshold voltage with input signal, and thus keeps the on-state resistance low over the full operating-signal range. The advantages over Single-channel switches include peak input-signal voltage swings equal to the full supply Voltage, and more constant on-state mpedance over the input-signal range_ For sample-and-hold applications, however, the CD40168 S recommended. The C04066B is available n 14-lead ceramic dual-in-line packages (0 and F suffixes). 14-lead plastic dual-in-line packages (E suffix). 14-lead ceramic flat pac;kages (K suffix). and n chip form (H suffix). 15-V digital or ±7.5-V peak-to-peak switching 125n typical on-state resistance for 15-V operation Switch on-state resistance matched to within 5 n over 15-V signal-input range On-state resistance flat over full peak-to-peak signal range High on/off output-voltage ratio: 80 db fis = 10 khz. R L = 1 kn High degree of linearity: <0.5% distortion fis = 1 khz, Vis = 5 VP-P. VOO - VSS 10 V, RL = 10 kn Extremely low off-state swtch leakage resulting in very low offset current and high effective off-state resistance: 10 pa VOO - VSS = 10 V, TA = 25 0 C Extremely high control input impedan.;e (control circuit isolated from signal circuit): 1012 n typo Low crosstalk between switches: -50 db fis = 8, RL = 1 kn Matched control-input to signal-output capacitance: Reduces output signal transients Frequency response, switch on = 40 (typ.) 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEOEC Tentative Standard No.13A, "Standard Specifications for Description of "B" Series CMOS Devices" FUNCTONAL DAGRAM Applications: Analog signal switching/multiplexing Signal gating Modulator Squelch control Demodulator Chopper Commutating switch Digital signal switching/multiplexing Transmission-gate logic implementation Analog-to-digital & digital-to-analog conversion Digital control of frequency, impedance, phase, and analog-signal gain MAXMUM RATNGS, Absolute-Maxmum Values DC SUPPL Y-VOL TAGE RANGE. (VDD' (Voltages referl!nced to VSS Termlnall -05 to +20 V NPUT VOLTAGE RANGE. ALL NPUTS -05 to V DD +05 V DC NPUT CURRENT. ANY ONE NPUT (except for TRANSMS.)N GATE which S 25 mal ±10 ma POWER DSSPATON PoER PACKAGE (PO' For T A : -40 to +60 C PACKAGE TYPE E) 500mW 0 For T A : +60 to +85 (PACKAGE TYPE E) Derate Lln"_ '., at 12 mw C to 200 mw For T A = -55 to +100 f (PACKAGE TYPES D. F) 500mW For T A: +100 to +125 C (PACKAGE TYPES D. F) Derate Linearly at 12 mw C to 200 mw DEVCE DSSPATON PER OUTPUT TRANSSTOR FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) 100mW OPERATNG-TEMPERATURE RANGE (T A) PACKAGE TYPES 0, F. H PACKAGE TYPE E -55 to +125 C -40 to +85:C STORAGE TEMPERATURE RANGE (T st -65 to +150 C LEAD TEMPERATURE lourng SOLDRNG At distance 1/16 ± 1/32 nch 1159 ± 079 mml from case for 10 s max RECOMMENDED OPERATNG CONDTONS For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges: CHARACTERSTC Min. LMTS UNTS Supply-Voltage Range (For T A = Full Package- Temperature Range) 3 18 V g NORMAL OPERATON CONTROL-LNE BASNG SWTCH ON.Vc"- VDO SWTCH OFF, VC -0' 'VSS E p'substrates ---- CONNECTED TO V DD '*ALL CONTROL NPUTS ARE PROTECTEO BY COS MOS PROTECTON NETWORK DO Vss Fg. 1 - SchematC dagram of 1 of 4 identical SWtches and its associated control C/fCUltry. 218

2 CD4066B Types ELECTRC/'L CHARACTERSTCS, Total.MTS AT. NDCATED TEM- PERATURES (OC) 'alues at -55, +25, +125 Apply Characteristic Test Conditions o D, F, H Packages Values at -40, +25, +85 Apply to E Package VN VDD (V) (V) f+125 Typ. 0, QUiescent Device 0, Current, 'no 0, Signal nputs (Vis) and Output (Vos) 0, Vc = VOO On State R L = 10 ku returned Resistance. ron to VOO - VSS Vis = VSS to VOO n State Resistance Between Any RL =lokh, Vc = VOO 10 - _ n 2 SWitches, 6r on Harmonic VC=VOO = 5 V, VSS=-5V. VS(p-p) Distortion. = 5 V (SlOe wave centered on 0 V) THO -3dB Cutolf Frequency (Switch on) RL =10 kn, fls=l khz sloe wave VC=VOO=5V, VSS=-5V, VS(p-p) =5 V (Sine wave centered on 0 V RL=lkn, -50dB Feed through VC=VSS= -5V, VS(p-p) = 5V Frequency Sine wave centerd on 0 V (Switch off) RL = 1 kn i nput/output Vc = 0" Leakage CJrrenl Vls=18V;Vos= 18 ±0.1 ±0.1 ±1 ±1 ±10 5 ±O 1 J.A (Switch off) o V. VS = OV; lis Vos=18V V(A =VOO= -50dB + V, VCVB = VSS Crosstalk = -5 V, isla) = Frequency 5 V P_' 50 n source RL = 1 kn RL=200kn Vc = VOO. VS= Delay (Signal GNO.CL=50p Propagation nput to Signal Output) tpd Vis = 10 V (Square wave centered on 5 V tr tf = 20 ns Capacitancl!: nput. Cis VOO=+SV Output. Cos Vc = VSS = -S V FeedthroL gh. Cios O.S - U N T S J.A n % ns tpf NPUT SGNAL VOLTAGE V.) - V 92CS-21326Rl Fig. 2- Typical on-state resistance vs. input signal 300 :.i;! 250f--.-, +- i--r+-.., 200;-q-+- '"... S 150' HJ '?.::: 100:.:-r+r SUPPLY VOLTAGE voo - VSS ) 15 V :! i1\ NPUT SGNAL VOLTAGE V.) - ; 1: 5 e v 92CS-Z13UR Fig. 4- Typical on-state resistance vs. nput signal NPUT SGNAL VOLTAGE V.. ) - Fig. 5- on-state resistance vs. input signal V 92CS-21HOR 219

3 ElECTRCAL CHARACTERSTCS (cont'd) Voo Characteristic Test Conditions LMTS AT NDCATED TEMPERATURES (OC) Values at -55, +25, +125 Apply to D, F, H Packages at -40, +25, +85 Apply to U N T S L- >-- PLOTTER x-y H P MOSELEY 1030.& Control (VC) Control nput Low Voltage, VLC llsl <10pA VS = VSS' VOS = VOO and VS = VOO, VOS = VSS Fig. 7 - Channel on srate resisrance measurement circuit. Control nput High Voltage, VHC See Fig. 2 nput Current, VS VO lin VOO - SS = 18 V VCC VOO - VSS Crosstalk (Con, trol nput to Signal Output) Turn On Propagation Oelay Vc = 10 V (Sq. Wave) tr, tf = 20 ns RL = 10 kr2 VN=VOO tr, tf = 20 ns CL = 50 pf RL = 1 kr2 VS = VOO, VSS = RL= 1 kh tognd, Maximum CL=50pF, Control nput Vc = 10 V(Square Repetition Rate wave centered on 5 V) tr, tf = 20 ns, Vos = Y,Vos@ 1 khz nput Capacitance, JJ.F CN Fig. 8 - Typical ron characteristics for 1 of 4 channels. VDD (V) Vis (V) Switch nput lis (rna) -55 C -40 C C C C VOl --_...:,=-,-_-L.. CO_4_06_6_B _---'Lv., OF 4 SWTCHES r- vls-v., '.n Fig. 6- Determination of r qn as a test condition for control input high voltage (V,HC ' specif,cat,on. Switch Output. Vas (V) Min a: a 10' SWTCHNG FREQUENCY (f)-h, Fig. 9 - Power dissipation per package ls. switching frequency. c o. r ,!::COEN :ON : vc'-,,, "001.',,: gi;m2actance: C'* NULLED OUT *co. * Fig Capacirance test circuit. 220

4 CD4088B Types.OVJ"\... 'f -20nl ALL UNuSED TERMNALS ARE CONNECTEO TO Vss ALL UNUSED NPUTS ARE CONNECTED TO VSS ALL UNUSED TERMNALS ARE CONNECTED TO Vss Fig. 77 -,)ff-$witch input or output leakage. Fig Propagation dalay time lignal input (Vi,) to signsl output (V 0,)' Fig Crosstslkontrollnput to signal output. ALL NUSEO TERMNALS ARE CONNECTED TO VSS Fig PrClpagation delay tplh' tphl controlsigllaloutput. Delay is measured at Vos lellel of from ground (turn-onj or,n-state output lellel (turn-offj. +O Vc 'r',-20ns VO' nl ALL UNuSEO NPuTS ARE CONNECTED TO Vss F;g. 75- Maximum al/owable control input repetition rate. 'NPUOS Yeo Yoo NOTE '-----'\- MEASURE NPUTS o SEQUENTAllY. VSS TO BOTH YOO ANa VSS CONNECT All UNUSEO NPUTS TO r..ther YOO OR VSS YSS MEASURE CONTROL NPUTS ONLY Fig nput leakage current test circuit. SGNAL.S PUTS O { O O CH'NNELl. O P4C'<4G[ 2 - C C0404ge 2 -C \ CLOCK ljuljl;voo Fig channel PAM multiplex system diagram. 221

5 ANALOG NPUTS (! 5 v) Fig Bidirectional signal transmission via digital control logic (l ) C040668H CHP PHOTOGRAPH DimenSions n parentheses are n millimeters and are def/ved from the basc nch dimensions as n' dlcated G"d graduations are n mils (1a-3 nch). The photographs and dimensons of each CDSMDS chip represent a chip when t S part of the wafer When the wafer S cut nto chips. the cleavage angles are 57 nstead of 90 with respect to the face of the chip Therefore, the solated chip S actually 7 mils (0. 17 mm) larger n both dimensions. SPECAL CONSDERATONS - CD n applications that employ separate power sources to drive VOO and the signal inputs, the VOO current capability should exceed VOO/RL (RL = effective external load of the four C bilateral switches). This provision avoids any permanent current flow or clamp action on the VOO supply when power is applied or removed from the C n certain applications, the external load-resistor current may nclude both VOO and signal-line components. To avoid drawing VOO current when switch current flows into terminals 1,4,8, or 11, the voltage drop across the bidirectional switch must not exceed 0.8 volts (calculated from RON values shown). No VOO current will flow through RL if the switch current flows into terminals 2,3,9, or