DATA SHEET. HEF4051B MSI 8-channel analogue multiplexer/demultiplexer. For a complete data sheet, please also download: INTEGRATED CIRCUITS

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1 INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC 8-channel analogue multiplexer/demultiplexer File under Integrated Circuits, IC04 January 1995

2 DESCRIPTION The is an 8-channel analogue multiplexer/demultiplexer with three address inputs (A 0 to A 2 ), an active LOW enable input (E), eight independent inputs/outputs (Y 0 to Y 7 ) and a common input/output (Z). The device contains eight bidirectional analogue switches, each with one side connected to an independent input/output (Y 0 to Y 7 ) and the other side connected to a common input/output (Z). With E LOW, one of the eight switches is selected (low impedance ON-state) by A 0 to A 2. With E HIGH, all switches are in the high impedance OFF-state, independent of A 0 to A 2. V DD and V SS are the supply voltage connections for the digital control inputs (A 0 to A 2, and E). The V DD to V SS range is 3 to 15 V. The analogue inputs/outputs (Y 0 to Y 7, and Z) can swing between V DD as a positive limit and V EE as a negative limit. V DD V EE may not exceed 15 V. For operation as a digital multiplexer/demultiplexer, V EE is connected to V SS (typically ground). Fig.2 Pinning diagram. P(N): 16-lead DIL; plastic (SOT38-1) D(F): 16-lead DIL; ceramic (cerdip) (SOT74) T(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING Y 0 to Y 7 A 0 to A 2 E Z independent inputs/outputs address inputs enable input (active LOW) common input/output FAMILY DATA, I DD LIMITS category Fig.1 Functional diagram. See Family Specifications. January

3 Fig.3 Schematic diagram (one switch). FUNCTION TABLE INPUTS CHANNEL E A 2 A 1 A 0 ON L L L L Y 0 Z L L L H Y 1 Z L L H L Y 2 Z L L H H Y 3 Z L H L L Y 4 Z L H L H Y 5 Z L H H L Y 6 Z L H H H Y 7 Z H X X X none Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Supply voltage (with reference to V DD ) V EE 18 to + 0,5 V Note 1. To avoid drawing V DD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional switch must not exceed 0,4 V. If the switch current flows into terminal Z, no V DD current will flow out of terminals Y, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed V DD or V EE. January

4 Fig.4 Logic diagram. January

5 DC CHARACTERISTICS T amb =25 C V DD V EE V Ω SYMBOL TYP. MAX. CONDITIONS ON resistance 10 R ON Ω Ω Ω ON resistance 10 R ON Ω Ω Ω ON resistance 10 R ON Ω Ω ON resistance 5 25 Ω between any two 10 R ON 10 Ω channels 15 5 Ω OFF-state leakage 5 na current, all 10 I OZZ na channels OFF na OFF-state leakage 5 na current, any 10 I OZY na channel na V is = 0 to V DD V EE see Fig.6 V is =0 see Fig.6 V is =V DD V EE see Fig.6 V is = 0 to V DD V EE see Fig.6 E at V DD V SS =V EE E at V SS V SS =V EE Fig.5 Operating area as a function of the supply voltages. January

6 Fig.6 Test set-up for measuring R ON. I is = 200 µa V SS = V EE = 0 V Fig.7 Typical R ON as a function of input voltage. January

7 AC CHARACTERISTICS V EE =V SS = 0 V; T amb =25 C; input transition times 20 ns V DD V TYPICAL FORMULA FOR P (µw) Dynamic power f i + (f o C L ) V 2 DD where dissipation per f i + (f o C L ) V 2 DD f i = input freq. (MHz) package (P) f i + (f o C L ) V 2 DD f o = output freq. (MHz) C L = load capacitance (pf) (f o C L ) = sum of outputs V DD = supply voltage (V) AC CHARACTERISTICS V EE =V SS = 0 V; T amb =25 C; input transition times 20 ns V DD V SYMBOL TYP. MAX. Propagation delays V is V os ns HIGH to LOW 10 t PHL 5 10 ns ns ns LOW to HIGH 10 t PLH 5 10 ns ns A n V os ns HIGH to LOW 10 t PHL ns ns ns LOW to HIGH 10 t PLH ns ns Output disable times E V os ns HIGH 10 t PHZ ns ns ns LOW 10 t PLZ ns ns Output enable times E V os ns HIGH 10 t PZH ns ns ns LOW 10 t PZL ns ns note 1 note 1 note 2 note 2 note 3 note 3 note 3 note 3 January

8 Distortion, sine-wave 5 0,25 % response 10 0,04 % 15 0,04 % Crosstalk between 5 MHz any two channels 10 1 MHz 15 MHz Crosstalk; enable 5 mv or address input mv to output 15 mv OFF-state 5 MHz feed-through 10 1 MHz 15 MHz ON-state frequency 5 13 MHz response MHz MHz Notes V DD V SYMBOL TYP. MAX. V is is the input voltage at a Y or Z terminal, whichever is assigned as input. note 4 note 5 note 6 note 7 note 8 V os is the output voltage at a Y or Z terminal, whichever is assigned as output. 1. R L = 10 kω to V EE ; C L = 50 pf to V EE ; E=V SS ; V is =V DD (square-wave); see Fig R L = 10 kω; C L = 50 pf to V EE ; E=V SS ; A n =V DD (square-wave); V is =V DD and R L to V EE for t PLH ; V is =V EE and R L to V DD for t PHL ; see Fig R L = 10 kω; C L = 50 pf to V EE ; E=V DD (square-wave); V is =V DD and R L to V EE for t PHZ and t PZH ; V is =V EE and R L to V DD for t PLZ and t PZL ; see Fig R L = 10 kω; C L = 15 pf; channel ON; V is = 1 2 V DD (p-p) (sine-wave, symmetrical about 1 2 V DD ); f is = 1 khz; seefig R L =1 kω; V is = 1 2 V DD (p-p) (sine-wave, symmetrical about 1 2 V DD ); 20 log V os = 50 db; see Fig. 10. V is 6. R L = 10 kω to V EE ; C L = 15 pf to V EE ; E or A n =V DD (square-wave); crosstalk is V os (peak value); see Fig R L =1 kω; C L = 5 pf; channel OFF; V is = 1 2 V DD (p-p) (sine-wave, symmetrical about 1 2 V DD ); 20 log V os = 50 db; see Fig. 9. V is 8. R L =1 kω; C L = 5 pf; channel ON; V is = 1 2 V DD (p-p) (sine-wave, symmetrical about 1 2 V DD ); 20 log V os = 3 db; see Fig. 9. V is January

9 Fig.8 Fig.9 (a) Fig.10 (b) APPLICATION INFORMATION Some examples of applications for the are: Analogue multiplexing and demultiplexing. Digital multiplexing and demultiplexing. Signal gating. NOTE If break before make is needed, then it is necessary to use the enable input. January