8 x 4 Analog Switch Array
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1 CMOS MT884A 8 x 4 Analog Switch Array Features Microprocessor compatible control inputs On chip control memory and address decoding Row addressing Master reset 32 crosspoint switches in 8 x 4 array 5. to 5. operation Low crosstalk between switches Low on resistance: 9 (typ.) at 3 Matched switch characteristics Switches frequencies up to 4MHz Applicatio PABX and key sytems Data acquisition systems Test equipment/itrumentation Analog/digital multiplexers ISSUE 2 October 989 Ordering Information MT884AC 24 Pin Ceramic DIP MT Pin Plastic DIP MT884AP 28 Pin PLCC -4 to 85 C Description The MT884A is a CMOS/LSI 8 x 4 Analog Switch Array incorporating control memory (32 bits), decoder and digital logic level converters. This circuit has digitally controlled analog switches having very low ON resistance and very low OFF leakage current. Switches will operate with analog signals at frequencies to 4 MHz and up to 5.p-p. A HIGH on the Master Reset input switches all channels OFF and clears the memory. This device is ideal for crosspoint switching applicatio. D D D2 D3 DD EE SS A A A2 3 to 8 Decoder Latches x 4 Switch Array Li I/O (i=-7) Ji I/O (i=-3) Figure - Functional Block Diagram 3-3
2 D3 J3 SS EE A A MT884A CMOS L L D J D J D2 J2 D3 J3 SS DD A2 A A EE D J D J D2 J L L DD A2 24 PIN CERDIP/PLASTIC DIP 28 PIN PLCC Figure 2 - Pin Connectio Pin Description Pin #* Name Description -3 -L -L Analog Lines (Inputs/Outputs): these are connected to the -L colum of the switch array. 4 D D Data (Input): Active High. 5 J J Analog Junctor (Input/Output): this is connected to the J row of the switch array. 6 DI DI Data (Input). Active High. 7 J J Analog Junctor (Input/Output): this is connected to the J row of the switch array. 8 D2 D2 Data (Input): Active High. 9 J2 J2 Analog Junctor (Input/Output): this is connected to the J2 row of the switch array. D3 D3 Data (Input): Active High. J3 J3 Analog Junctor (Input/Output): this is connected to the J3 row of the switch array. 2 SS Digital Ground Reference. 3 EE Negative Power Supply. 4-6 A-A2 A-A2 Address Lines (Inputs). 7 Address Enable/Strobe (Input): enables function selected by address and data. Address must be stable before goes high and D-D3 must be stable on the falling edge of the. Active High. 8 Master RESET (Input): this is used to turn off all switches. Active High Analog Lines (Inputs/Outputs): these are connected to the - colum of the switch array. 24 DD Positive Power Supply. * Plastic DIP and CERDIP only 3-4
3 CMOS MT884A Functional Description The MT884A is a CMOS/LSI 8 X 4 Analog Switch Array incorporating an 8 X 4 analog switch array, address decoder, control memory, and digital logic level converter. The analog switch array is arranged in 8 rows and 4 colum. The row input/outputs are referred to as Lines (L-) and the column input/outputs as Junctors (J-J3). The crosspoint analog switches interconnect the lines and junctors when turned ON and provide a high degree of isolation when turned OFF. Interchannel crosstalk is minimal despite the high deity of the analog switch array. The control memory of the MT884A can be treated as an 8 word by 4 bit random access memory. The 8 words are selected by the ADDRESS (A-A2) inputs through the on chip address decoder. Data is presented to the memory via the four DATA inputs (D-D3). This data is asynchronously written into the control memory whenever the ADDRESS ENABLE () input is HIGH. A HIGH level written into a memory cell tur the corresponding crosspoint switch ON while a LOW level causes the crosspoint to turn OFF. Figure 3 - On Resistance vs. Temperature (Input Signal oltage=supply oltage/2), SS = and EE =-6, the control inputs can be driven by a 5 system while the analog voltages through the crosspoint switches can swing from 5 to -6. Only the crosspoint switches corresponding to the addressed memory word are affected when data is written into the memory. The remaining switches retain their previous states. By establishing appropriate patter in the control memory, any combination of lines and junctors may be interconnected. A HIGH level on the MASTER RESET () input retur all memory locatio to a LOW level and tur all crosspoint switches OFF effectively isolating the lines from the junctors. The digital logic level converters allow the digital input levels to differ from limits of the analog levels switched through the array. For example, with Figure 4 - On Resistance vs. Input Signal oltage 8x8 Analog/Digital Switch Two MT884s configured as shown, implement an 8 x 8 analog/digital switch. The switch capacity can be expanded to an M x N array of inputs/ outputs. Expaion in the M dimeion is as shown with the MT884A lines (L-) commoned. Expaion in the N dimeion is accomplished by replicating the circuit shown and connecting the MT884A junctors (J-J3) in common. The address and data control inputs of the MT884A s can be connected in common for any size and switch provided that the address enable () inputs are driven individually. A particular signal path is connected by setting up the appropriate signals or the address and data lines and taking the corresponding address enable input high. The master reset (), when taken high, disconnects all signal paths. Figure 5-8 x 8 Analog/Digital Switch 3-5
4 MT884A CMOS Absolute Maximum Ratings* - oltages are with respect to EE unless otherwise stated. Parameter Symbol Min Max Units Supply oltage DD- SS DD- EE SS- EE Analog Input oltage INA EE -.3 DD.3 3 Digital Input oltage IN SS -.3 DD.3 4 Current on any Logic Pin I ma 5 Storage Temperature T S C 6 Package Power Dissipation PLASTIC DIP CERDIP P D.6 P D.2 * Exceeding these values may cause permanent damage. Functional operation under these conditio is not implied. Recommended Operating Conditio - oltages are with respect to EE unless otherwise stated. Characteristics Sym Min Typ Max Units Test Conditio Operating Temperature T O C 2 Supply oltage DD - SS DD - EE 5 5 SS - EE 5 3 Analog Input oltage INA EE DD 4 Digital Input oltage IN SS DD W W DC Electrical Characteristics - oltages are with respect to EE = SS =. Characteristics Sym Min Typ Max Units Test Conditio Quiescent Supply Current I DD µa. All digital inputs at IN = SS or DD 2 Off-state Leakage Current (Any line to any junctor) 3 Input Logic level IL Input Logic level IH Maximum current through Crosspoint Switch I OFF ±. ±5 na DD =3, Switch is Off I Ji - Lj I = DD - EE I MAX ±8. ma DD =3 DC Electrical Characteristics are at ambient temperature (25 C). Typical figures are for design aid only; not guaranteed and not subject to production testing. DD = INA = DD through k DD = INA = DD through k DC Electrical Characteristics- Switch Resistance - DC is the external DC offset applied at the analog I/O pi. Characteristics Sym 25 C 7 C 85 C Units Test Conditio Min Typ Max Typ Typ On-state DD =3 Resistance DD = DD = 5 2 Difference in on-state resistance between two switches DD =3 DD = R ON R ON SS = EE =, DC = DD /2, I Ji - Lj I =.6 SS = EE =, DC = DD /2, I Ji - Lj I =.6 3-6
5 CMOS MT884A AC Electrical Characteristics - Crosspoint Performance - DC is the external DC offset applied at the analog I/O pi. oltages are with respect to DD =, SS = EE = unless otherwise stated. Characteristics Sym Min Typ Max Units Test Conditio Switch Line Capacitance C IS 5 pf 2 Switch Junctor Capacitance C OS 2 pf 3 Feedthrough Capacitance C I.2 pf 4 Frequency Respoe Channel ON 2LOG( OUT / INA ) = -3dB 5 Total Harmonic Distortion / DC =7.5 DD =/ DC =5 / DC =2.5 6 Feedthrough Channel OFF Feed.=2LOG ( OUT / INA ) 7 Crosstalk between any two channels for switches Li - Ji and Lj - Jj. Li - Ji is ON Lj - Jj is OFF Xtalk=2LOG ( Jj / Li ). 8 Propagation delay through switch F 3dB 4 MHz Switch is ON ; DC =5, INA =5pp sinewave f= khz; R L = k THD..2. AC Electrical Characteristics are at ambient temperature (25 C). Typical figures are for design aid only; not guaranteed and not subject to production testing. % % % Switch is ON ; EE= SS = INA =5pp sinewave f= khz; R L = k FDT -5 db All Switches OFF ; INA = 5pp sinewave f= MHz; R L = k. DC =5 X talk -4 db INA =2pp sinewave f=.mhz; R L = db INA =2pp sinewave f= 3.4kHz; R L = 6. DC = 5 t PS C L =5pF AC Electrical Characteristics - Control and I/O Timings- oltages are with respect to SS = EE = unless otherwise stated. Characteristics Sym Min Typ Max Units Test Conditio Digital Input Capacitance C DI 5 pf DD = 2 Setup Time D-D3 to t DS Hold Time D-D3 to t DH Setup Time Address to t AS 5 5 Hold Time Address to t AH Pulse Width t W 25 7 to Switch Status Delay t P DATA to Switch Status Delay t PLH 25 t PHL 65 9 to Switch Status Delay t 25 5 t R AC Electrical Characteristics are at ambient temperature (25 C). Typical figures are for design aid only; not guaranteed and not subject to production testing. Note R L = k, C L =5pF Note 2 R L = k, C L =5pF Digital Input rise time (tr) and fall time (tf) = 5. DD = DD = DD = DD = DD = DD = DD = DD = DD = See Note See Note See Note 2 3-7
6 MT884A CMOS 3-8 Figure 6 - Control Memory Timing Diagram Table - Address Decode Truth Table NOTES: - Low Logic Level - High Logic Level X - Don t Care Condition - Indicates Connection Between Junctor and Addressed Line - Indicates No Connection Between Junctor and Addressed Line Memory Reset Address Enable Address Addressed Line Input Data To Control Memory Junctors Connected To Addressed Line A2 A A D3 D2 D D J3 J2 J J X X X X ALL X X X X All Switches "OFF" X X X NONE X X X X No Change of State L L L L L L L L L L L L L L L L L L t W t AS t DH t PLH /t PHL t P t t R tplh /t PHL t DS t AH 5% 5% 5% 5% 5% 5% 5% 5% 5% ADDRESS D-D3 SWITCH ON OFF
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