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2 3.1 Circuito integrado October 1987 Revised March 2002 CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2- Input NAND Buffered B Series Gate General Description Features The CD4001BC and CD4011BC quad gates are monolithic Low power TTL: complementary MOS (CMOS) integrated circuits con- Fan out of 2 driving 74L compatibility: or 1 driving 74LS structed with N- and P-channel enhancement mode tran- 5V 10V 15V parametric ratings sistors. They have equal source and sink current Symmetrical output characteristics capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve Maximum input leakage 1 µa at 15V over full transfer characteristics by providing very high gain. temperature range All inputs are protected against static discharge with diodes to V DD and V SS. Ordering Code: Order Number Package Number Package Description CD4001BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4001BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4001BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS- 001, 0.300" Wide CD4011BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4011BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS- 001, 0.300" Wide pág. 2

3 Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagrams Pin Assignments for DIP, SOIC and SOP CD4001BC Pin Assignments for DIP and SOIC CD4011BC Top View Top View pág. 3

4 Schematic Diagrams CD / 4 of device shown J = A + B Logical 1 = HIGH Logical 0 = LOW All inputs protected by standard CMOS protection circuit. CD / 4 of device shown J = A B Logical 1 = HIGH Logical 0 = LOW All inputs protected by standard CMOS protection circuit. AC Electrical Characteristics ( Note 5) CD4011BC: TA= 25 C, Input t r; t f = 20 ns. C L = 50 pf, R L = 200k. Typical Temperature Coefficient is 0.3%/ C. Symbol Parameter Conditions Typ Max Units pág. 4

5 tphl Propagation Delay, HIGH-to-LOW Level VDD = 5V VDD = 10V VDD = 15V ns tplh Propagation Delay, LOW-to-HIGH Level VDD = 5V VDD = 10V ns VDD = 15V tthl, t TLH Transition Time VDD = 5V VDD = 10V VDD = 15V ns CIN Average Input Capacitance Any Input pf CPD Power Dissipation Capacity Any Gate 14 pf Note 5: AC Parameters are guaranteed by DC correlated testing. Typical Performance Characteristics Transfer Characteristics Typical Transfer Characteristics/Typical Typical Typical Transfer Characteristics pág. 5

6 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICYFAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support which, (a) are intended for surgical implant into the device or system whose failure to perform can be reabody, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support to perform when properly used in accordance with device or system. 3.2 Circuito integrado LM380. pág. 6

7 (1) The package is to be derated at 15 C/W junction to heat sink pins for 14-pin pkg; 75 C/W for 8-pin. Electrical Characteristics (1) Symbol Parameter Conditions Min Typ Max Units POUT(RMS) Output Power RL = 8Ω, THD = 3%(2)(3) 2.5 W A V Gain V/V VOUT Output Voltage Swing R L = 8Ω 14 Vp-p ZIN Input Resistance 150k Ω THD Total Harmonic Distortion See(3)(4) 0.2 % PSRR Power Supply Rejection Ratio See(5) 38 db V S Supply Voltage V BW Bandwidth P OUT = 2W, R L = 8Ω 100k Hz pág. 7

8 IQ VOUTQ Quiescent Supply Current 7 25 ma Quiescent Output Voltage V Block and Schematic Diagrams Typical Performance Characteristics Maximum Device Dissipation vs Ambient Temperature Output Power 4Ω Load Device Dissipation vs pág. 8

9 Figure 6. Figure 7. Device Dissipation vsoutput Power 16Ω Device Dissipation vs Output Power 8Ω Load Load Figure 8. Figure 9. Power Supply Current vs Supply Voltage Total Harmonic Distortion vs Frequency Figure 10. Figure 11. Typical Performance Characteristics (continued) Output Voltage Gain and Phase vs Frequency Total Harmonic Distortion vs Output Power pág. 9

10 3.3 Circuito integrado BC108. pág. 10

BC107 BC108 LOWNOISEGENERALPURPOSEAUDIOAMPLIFIERS DESCRIPTION The BC107 and BC108 are silicon planar epitaxialnpntransistorsinto-18metalcase.

11 BC107 BC108 LOWNOISEGENERALPURPOSEAUDIOAMPLIFIERS DESCRIPTION The BC107 and BC108 are silicon planar epitaxialnpntransistorsinto-18metalcase. Theyaresuitableforuseindriverstages,low noiseinputstagesandsignalprocessingcircuits oftelevisionreveivers.thepnpcomplemetfor BC107isBC177. TO-18 INTERNALSCHEMATICDIAGRAM ABSOLUTEMAXIMUMRATINGS Symbol Parameter Value Unit BC107 BC108 V CBO Collector-BaseVoltage(I E =0) V V CEO Collector-EmitterVoltage(I B =0) V V EBO Emitter-BaseVoltage(I C =0) 6 5 V I C CollectorCurrent 100 ma P tot TotalDissipationatT amb 25 o C att case 25 o C T stg StorageTemperature -55 to 175 T j Max.OperatingJunctionTemperature 175 o C W W o C November1997 pág. 11

12 pág. 12

13 Collector-baseCapacitance. TransitionFrequency. PowerRatingChart. pág. 13

14 This datasheet has been download from: for electronics components. 3.4 Circuito integrado LM741. LM741 Operational Amplifier Check for Samples: LM741 1FEATURES DESCRIPTION 2 Overload Protection on the Input and Output The LM741 series are general purpose operational No Latch-Up When the Common Mode Range amplifiers which feature improved performance over industry standards like the LM709. They are direct, is Exceeded plug-in replacements for the 709C, LM201, MC1439 and 748 in most applications. Connection Diagrams LM741H is available per JM38510/10101 The amplifiers offer many features which make their application nearly foolproof: overload protection on the input and output, no latch-up when the common mode range is exceeded, as well as freedom from oscillations. The LM741C is identical to the LM741/LM741A except that the LM741C has their performance ensured over a 0 C to +70 C temperature range, instead of 55 C to +125 C. Figure 1. TO-99 Package See Package Number LMC0008C Figure 2. CDIP or PDIP Package See Package Number NAB0008A, P0008E Figure 3. CLGA Package See Package Number NAD0010A pág. 14

15 Electrical Characteristics (1) LM741A LM741 LM741C Parameter Test Conditions Min Typ Max Min Typ Max Min Typ Max Units Input Offset Voltage T A = 25 C R S 10 kω mv R S 50Ω TAMIN TA TAMAX R S 50Ω 4.0 mv R S 10 kω Average Input Offset Voltage Drift 15 μv/ C (1) Unless otherwise specified, these specifications apply for VS = ±15V, 55 C TA +125 C (LM741/LM741A). For the LM741C/LM741E, these specifications are limited to 0 C TA +70 C. 2 Submit Documentation Feedback Copyright , Texas Instruments Incorporated LM741 Electrical Characteristics (1) (continued) LM741A LM741 LM741C Parameter Test Conditions Min Typ Max Min Typ Max Min Typ Max Units Input Offset Voltage T A = 25 C, V S = ±10 ±15 ±15 mv Adjustment Range ±20V Input Offset Current T A = 25 C na TAMIN TA TAMAX Average Input Offset Current 0.5 na/ C Drift Input Bias Current T A = 25 C na TAMIN TA TAMAX μa Input Resistance T A = 25 C, V S = ±20V Input Voltage Range T A = 25 C ±12 ±13 TAMIN TA TAMAX ±12 ±13 MΩ V pág. 15

16 Large Signal Voltage Gain T A = 25 C, R L 2 kω V S = ±20V, V O = ±15V 50 V/mV V S = ±15V, V O = ±10V TAMIN TA TAMAX, R L 2 kω, V S = ±20V, V O = ±15V 32 V/mV V S = ±15V, V O = ±10V V S = ±5V, V O = ±2V 10 Output Voltage Swing V S = ±20V R L 10 kω ±16 V R L 2 kω ±15 V S = ±15V R L 10 kω ±12 ±14 ±12 ±14 V R L 2 kω ±10 ±13 ±10 ±13 Output Short Circuit Current Common-Mode T A = 25 C TAMIN TA TAMAX TAMIN TA TAMAX ma Rejection Ratio R S 10 kω, V CM = ±12V R S 50Ω, V CM = ±12V Supply Voltage TAMIN TA TAMAX, Rejection Ratio V S = ±20V to V S = ±5V db R S 50Ω R S 10 kω Transient Response T A = 25 C, Unity Gain Rise Time μs Overshoot % Bandwidth (2) T A = 25 C MHz db Slew Rate T A = 25 C, Unity Gain V/μs pág. 16

17 Supply Current T A = 25 C ma Power Consumption T A = 25 C V S = ±20V mw V S = ±15V (2)Calculated value from: BW (MHz) = 0.35/Rise Time (μs). Copyright , Texas Instruments Incorporated Submit Documentation Feedback 3 LM741 SNOSC25C MAY 1998 REVISED MARCH Electrical Characteristics (1) (continued) LM741A LM741 LM741 C Parameter Test Conditions Min Typ Max Min Typ Max Min Typ Max Units LM741A V S = ±20V TA = TAMIN 165 mw TA = TAMAX 135 LM741 V S = ±15V Thermal Resistance TA = TAMIN mw TA = TAMAX CDIP (NAB0008A) PDIP (P0008E) TO-99 (LMC0008C) SO-8 (M) θ ja (Junction to Ambient) 100 C/W 100 C/W 170 C/W 195 C/W θ jc (Junction to Case) N/A N/A 25 C/W N/A MECHANICAL DATA NAB0008A NAB0008A MECHANICAL DATA pág. 17

18 Mechanical data. pág. 18

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CD4069UBC Inverter Circuits

CD4069UBC Inverter Circuits General Description The CD4069UB consists of six inverter circuits and is manufactured using complementary MOS (CMOS) to achieve wide power supply operating range, low power