Status and Challenges for Probe Nanopatterning. Urs Duerig, IBM Research - Zurich

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1 Status and Challenges for Probe Nanopatterning Urs Duerig, IBM Research - Zurich

2 Mask-less Lithography Electron beam lithography de-facto industry standard Probe lithography mainly a research tool Courtesy of Leica Lithography Systems Ltd. Challenge: Bring probe lithography closer to industrial applications

3 Lithography Throughput versus Feature Size Mask-less lithography is slow at the nm scale High throughput mask lithography Chemically amplified resists VSB optical EUV? (NIL?) parallelization?? Low throughput mask-less lithography electron beam (E-beam) thermal scanning probe lithography tspl typical probe based lithography Adapted from: C. Marrian, D. Tennant, J. Vac. Sci. Technol., A, 2003, 21, S207 S.V. Sreenivasan, MRS Bulletin, Sept. 2008; Mask production: cm 2 /s 1 mask in 8h Wafer scale litho: 1 20 cm 2 /s wph

4 Why is probe lithography attractive High resolution capability (in the nm range) No proximity effects Urs Duerig, IBM Research Zurich, 2013 Direct write method no development needed In-situ imaging capability for process control and alignment Table-top instrumentation and low cost of ownership Challenges: Probe patterning is slow not generically true parallelization is perfectly feasible Tip endurance Compatibility with standard processing

5 Examples of Probe Patterning Moving atoms Eigler 1990 Urs Duerig, IBM Research Zurich, 2013 LAO (local anodic oxidation) Dagata 1990 Electron exposure of resist Quate 1990s- Material: Silicon; Tapping R. Garcia, R. V. Martinez and J. Martinez, Chem. Soc. Rev. 2006, 35, GaAs Quantum devices Speed: 180 um/s 1 mm/s; Material: Siloxane SOG S. W. Park, H. T. Soh, C. F. Quate and S. I. Park, Appl. Phys. Lett. 1995, 67, A. Fuhrer et al., Nature 2001, 413, 822.

6 Direct Patterning of Organic Resists Compatibility with standard processing Rangelow, Ilmenau University of Technology nm Kaestner and Rangelow, Micro Electronic Engineering 97 (2012) Electric field assisted desorption of low molecular weight glass resist (calixarene) Potential for sub 10 nm resolution patterning Z. Durrani et al. Proc. of SPIE Vol. 8689, 2013

7 Direct Patterning of Organic Resists by Thermally Induced Evaporation The IBM-Approach : thermal Scanning Probe Lithography (tspl) Main features of the technique Sub 15 nm patterning resolution Operates under atmospheric conditions Pixel rates of up to 500 khz Sub10 nm field stitching Compatible with CMOS processing 3D patterning Closed-loop lithography: Combined write and read scheme

8 tspl: Operation Principle Micromachined Cantilevers Thermo-mechanical writing: Electrostatic actuation: up to 1 µn Resistive tip heating: up to 750 ºC Thermo-resistive reading: Read resistor heated to ~ 200 ºC Sensitivity ~ khz BW

9 tspl: Early Results using Molecular Glass Resist MG 2 nm -10 nm Transfer by RIE SiOx PS Silicon 1µm 1µm Tip after patterning several fields: same scale: Pattern in Si after transfer: 400 nm depth (50x) Pitch 29nm 8 nm depth Parameters: # Pixels: Heater temperature: 300 C Load force: 80nN Pulse duration: 5.5µs 0.2 µm 3 100nm SEM of the tip after written pixels Pires et al. Science 328 (2010)

10 depth (nm) depth (nm) Urs Duerig, IBM Research Zurich, 2013 tspl: Early Results using Molecular Glass Resist nm 2 nm -4 z (nm) distance ( m) - 5 nm 0 15 nm half-pitch vertical horizontal Parameters: Heater temperature: 500C Load force: 108 nn Pulse duration: 5.0 µs Pixel size: 10 nm Patterning depth: 6 nm 15 nm half-pitch achieved no proximity effect good for 10 nm node lithography half pitch (nm) Pires et al. Science 328 (2010)

11 tspl: Path to Viable Technology Patterning Speed and Reliability High efficiency poly-phthalaldehyde (PPA) resist 500 khz pixel rate Fractal pattern Circles and lines 300 nm 3 µ m 1 µm 880 x 880 pixels (pitch 15 nm) scan speed 7.5 mm/s total writing time 11.8 s 125 x 100 pixels (pitch 40 nm) scan speed 20 mm/s total writing time 0.8 s Paul et al. Nanotechnology 22 (2011)

12 tspl: Path to Viable Technology Stitching and Overlay Surface topography is used as unique position marker image cross-correlation provides accurate offset measurement no special purpose alignment markers needed Field stitching using natural surface roughness as fingerprint 4 th 3 rd 1 st 2 nd 5 th Paul et al. Nanotechnology 23 (2012) ) write 1 st field and read back topography with a stitching margin 2) move coarse positioning stage 3) read topography at new position 4) correlate the two overlapping fields and determine offset 5) write 2 nd field at correct position. etc. Result: 1 nm metrological accuracy 10 nm stitching accuracy limited by - distortions of the scan motion - thermal drift

13 tspl: Path to Viable Technology Stitching and Overlay Overlay using topography modulation for alignment tspl pattern in PPA resist PPA HM8006 layer Si 7 nm 20 nm 50 nm 13 nm Coarse pattern in Si wafer Challenge: pattern registration with respect to scan field: position rotation scaling Rawlings et al. MNE 2013 tspl pattern 37 nm half-pitch nested L Result: Buried coarse pattern 1 nm metrological accuracy from correlation algorithm 7 nm overlay accuracy in experiment

14 tspl: Path to Viable Technology Pattern Transfer into Si Challenge: Conversion shallow tspl patterns into high aspect ratio binary patterns in a suitable resist for Si processing Solution: 3 step RIE transfer process using 4nm of SiO2 as intermediate hard mask PPA SiO2 HM8006 Patterning depth 8 nm 20 nm 50 nm Step 1 Step 2 Step 3 1 O2 + 4 N2 RIE thinning of PPA 4 nm CHF3 RIE pattern transfer into SiO2 4 nm O2 RIE pattern transfer into HM8006 Cheong et al. Nano Letters 13 (2013)

15 tspl: Path to Viable Technology Pattern Transfer into Si as written by tspl in PPA resist 1 µm after transfer into Si 27 nm HP lines transferred 50 nm deep into silicon 2.4 nm (3s) line edge roughness Cheong et al. Nano Letters 13 (2013) nm

16 tspl: 3-D patterning Accurate control of the patterning depth via tip-force unique 3-D (grey scale) patterning capability 2013 IBM Research - Zurich 2048 x 1382 pixels 9 nm per pixel Writing speed 20 µs/pixel Relief depth 40 nm Accuracy 3 nm (3 sigma) Application Fabrication of micrometer size optical Fabri-Perrot cavities for quantum-optical devices: Gaussian shaped mirrors with nm precision surface profile Source: Knoll et al. Advanced Materials 22 (2010) , Zientek et al. MNE 2013

17 Next Steps Facilitate access to probe patterning technology for a large user community commercialization of tspl tool (SwissLitho AG) Explore full potential of probe patterning for sub-10 nm lithography and manufacturing FP7 integrated project SNM: Single Nanometer Manufacturing for beyond CMOS devices involving 15 major European players from industry and academia in the field Raise industry interest for the development of high throughput probe array lithography tools

18 Acknowledgements Nano-Patterning at IBM Research - Zurich: Armin Knoll, Colin Rowlings, Michal Zientek, Felix Holzner (now at SwissLitho), Philip Paul (now at SwissLitho), Michel Despont (now at CSEM, Neuchatel) Microfabrication at IBM Research - Zurich: Ute Drechsler, Daniel Grogg, Richard Stutz Synthesis of PPA at IBM Research - Almaden: James L. Hedrick, Daniel Coady Pattern Transfer: Lin Lee Cheong, MIT (now at IBM Research Yorktown Heights) Others at IBM Research - Zurich: Heiko Wolf, Walter Riess Funding Swiss National Science Foundation European Seventh Framework Program (FP7) in the project SNM: Single Nanometer Manufacturing for beyond CMOS devices.

19 Thank you for your attention