Systematic experimental study on stitching techniques of CMOS image sensors

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1 LETTER IEICE Electronics Express, Vol.13, No.15, 1 11 Systematic experimental study on stitching techniques of CMOS image sensors Jun Zhu 1, Donghua Liu 1, Wei Zhang 1, Qing Wang 2a), Wenliang Li 2, Lijun Chen 2, Chen Li 3, and Yuhang Zhao 3 1 State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai , China 2 Shanghai Huali Microelectronics Corporation, Shanghai , China 3 Shanghai Integrated Circuit Research and Development Center Ltd, Shanghai , China a) qwangever@126.com Abstract: On the basis of the systematic study of stitching techniques, a large area, 28.3 mm 38.8 mm, 42 Mega pixels CMOS Imaging Sensor (CIS) had been demonstrated on 12 inch silicon wafer in a µm CMOS process. By scanning a reticle across a wafer of silicon, smaller arrays can be stitched together to construct larger area sensors. Meanwhile, in order to verify the feasibility and capability of stitching, a 203 mm 179 mm, 1.8 Billion pixels CIS was also created without any performance deficiency. Keywords: CMOS Imaging Sensor (CIS), stitching technique, 12 inch, µm CMOS process Classification: Integrated circuits References [1] A. T. Clark, et al.: A 54mm 54 mm-1.8 Megapixel CMOS image sensor for medical imaging, Nuclear Science Symposium Conference Record (2008) 4540 (DOI: /NSSMIC ). [2] B. C. Burkey, et al.: The pinned photodiode for an interline-transfer CCD image sensor, International Electron Devices Meeting 30 (1984) 28 (DOI: /IEDM ). [3] S. Ay and E. R. Fossum: A mm sup 2, million pixel CMOS APS image sensor, Symposium on VlSI Circuits (2006) 19 (DOI: / VLSIC ). [4] P. J. W. Noble: Self-scanned image detector arrays, IEEE Trans. Electron Devices 15 (1968) 202 (DOI: /T-ED ). [5] E. R. Fossum: Active pixel sensors: are CCDs dinosaurs?, Proc. SPIE 1900 (1993) 2 (DOI: / ). [6] G. Meynants, et al.: A 35 mm million pixel CMOS active pixel image sensor, IEEE CCD & AIS (2003). [7] G. Kreider, et al.: An mk nk modular image sensor design, 1995 International Electron Devices Meeting. IEDM 95 (1995) 155 (DOI: / IEDM ). [8] H. W. P. Koops, et al.: Combined lithographies for the reduction of stitching errors in lithography, J. Vac. Sci. Technol. B 12 (1994) 3265 (DOI: / 1

2 ). [9] A. Levin, et al.: Seamless image stitching in the gradient domain, Lect. Notes Comput. Sci (2004) 377 (DOI: / _31). [10] H. Liu and Y. Chen: Breaking through 1D layout limitations and regaining 2D design freedom part II: stitching yield modeling and optimization, Proc. SPIE 9427 (2015) (DOI: / ). [11] Y. C. Pai, et al.: High-order stitching overlay analysis for advanced process control, Proc. SPIE 7971 (2011) (DOI: / ). [12] J. Zhou and Y. Chen: A comparative study on the yield performance of via landing and direct stitching processes for 2D pattern connection, Proc. SPIE 9781 (2016) 97810T (DOI: / ). 1 Introduction In the new era of high resolution solid state imaging devices, Conventional chargecoupled devices (CCDs) and CIS, had threatened traditional image recording technologies, such as film, video and so on [1]. Comparing with CCD, CIS has the major advantages of low power consumption, single voltage power supply and compatibility with well-established standard silicon process in high-volume wafer plants [2, 3, 4]. The CIS preserved all the desirable features of CCD, yet circumvented the major weaknesses of the CCD technology [5], making the CIS become the most common and highest yielding process in the world by far. Because of the reticle size limitation, the size of CIS were constrained within 26 mm 33 mm, left the semiconductor industry with no choice but to adopt Stitching Techniques to continue the scaling of technology. The stitching was one of the most favorable processes to allow a single chip occupy any amount of the wafer [6]. The technology was achieved by dividing the reticle into sections that could individually be exposed and aligned with neighboring sections [7]. Making an intensive study of stitching techniques and related guideline would enable CIS to participate in Si process shrinkage that moves to deep sub-micrometer node and is flexibly compatible with advanced manufacture process [8]. Systematically study has to be done in chip placement and architecture and design guideline. In particular, we established an evaluation procedure to identify the baseline accuracy of different exposure tools, as well as the fundamental guarantee of the stitching techniques. Then, based on a series of experiments and analysis [9, 10], a stitching overlay control approach using correctables generated from the overlay metrology system effectively reduce the distortion [11]. Finally, the proposed sensor is successfully implemented in a µm CMOS process, which demonstrated on 12 inch silicon wafer. In addition to the details of experiments, a raw imaging application by using this sensor architecture is also presented. 2 Stitched CIS: Placement and architecture The size with 42 Mega pixels is obviously larger than the typical reticle size (26 mm 33 mm) when peripheral circuits are included. To produce the chip, stitching techniques are the only realistic way at present. Stitching allows different sections of a chip to be repeated across the wafer with very high accuracy 2

3 placement. The high resolution CIS is a natural fit for the stitching application. The pixel array forms the central repeated sections while the supporting circuits and pads forms the external sections. This CIS is constructed by stitching a 2 2 array of pixel regions together on a single wafer. Fig. 1. Stitched CIS chip and the sections layout (Left: the CIS separated by 7 sections; Right: the exposure shot map placement on 12 inch). The architecture of the CIS chip is shown in Fig. 1, separated by 7 sections ða; B; C; D; E; F; GÞ. The sub blocks forms a pixel array (labeled as G in Fig. 1). It is scanned and imaged 4 times to form the 2 2 array of stitched regions which contained a total of pixels or 42 Megapixels with an imaging area of 25:4 mm 35:8 mm. The sensor is completed with the Correlated Double Sampling circuits (CDS) and comparators in the two corner in the top ða1;a2þ. Block B(1 4) on the edge pieces contains decoders and drivers. Block C and E form the Phase Locked Loop (PLL), decoder controllers and digital buffers. The read-out circuitry including digital and analog processors, decoders and charge mode readout circuits is located in block D and F on the top and bottom. Fig. 2. Schematic illustration of image sensor circuit and block Diagram of the CMOS APS. The external sides around the array area are seamlessly placed by other sections. Therefore no space is wasted. The pads for control signals, outputs, digital and analog power supply were spread all over the sections so that the stitching of pixel region is not mandatory. Implemented schematic diagram is described in Fig. 2. And a specification of the image sensor is tabulated in Table I. There are 45 layers (1P4M) in total on µm CMOS process. 3

4 Table I. Specifications of the image sensor. Chip Size 28:3ðv:Þ38:8ðh:Þ Pixel size 5.67 µm Shutter Scroll electronic shutter Exposure method Support a global reset release exposure method Frame Rate 2.5 fps Windowing Support open window, the smallest window size Pixels merger Support 2 2 pixels-merger Basic frequency 25 MHZ Output interface 8 analog readout port Gain In-pixel programmable gain amplifier FD Conversion Gain 27 (uv/e) Dynamic Range 70.5 db Noise Floor 0.3 mv VDD H 3.3 V RX H 4V Power Supply RS H 3.3 V TX H 4V TX L 0.5 V 3 Stitched CIS: Design of stitching Complying with the placement of stitching, the large CIS chip was achieved by separating the design into several sections. Due to the characteristics of process layers, different kinds of tools including 193 nm wet, 248 nm and 365 nm lithography had been allocated to achieve all of the layers. An evaluation procedure to identify the baseline accuracy of different exposure tools which could be the fundamental guarantee of the stitching techniques had been setup. The schematic diagram of the evaluation procedure is shown in Fig. 3. The field 1 5 were exposed by different tools. The overlay measurement pattern could be used to quantify the accuracy. One of the biggest complexities of stitching is that a stitch can be across different pattern combinations (i.e. line, space and hole structures). Consequently, stitches might be shape-dependent and the location of candidate stitches could only be determined by the experiment result. To further study the stitching performance of different structures and mastery the design guideline of the techniques [12], test reticle have been design and implemented. Snippets are shown as Fig. 4. Meanwhile, a 193 nm PSM mask and a 248 nm Binary mask were used to check the performance of ArF immersion, KrF and I-line lithography. Following the evaluation procedure shown in Fig. 3, the field 1 5 are exposed by 193 nm, 248 nm and 365 nm tools separately. The measurement of overlay pattern was used to define the stitched overlay and the details will be discussed in the next section. On the basis of experiment results [11], we have established a methodology for layout decomposition and guideline of the stitching for different layers. Without 4

5 IEICE Electronics Express, Vol.13, No.15, 1 11 Fig. 3. The schematic diagram for different exposure tool overlay accuracy evaluation, where the overlay measurement pattern for horizontal and vertical are marked by dotted line. Fig. 4. Examples of test reticle (line, space and hole structures), the red dotted line indicating the position of stitching. loss of generality, we take the Metal 1 layer as an example, the major design guideline of the stitching for M1 was shown in Fig. 5. locations of the stitching were represented by red dotted line; patterns ware represented by green blocks; letter A F represent the distance between different geometric boundary. Some key rules are listed in the Table II with different lithography conditions. Width of nonstitching space to stitched line, the minimum space between lines, the length of hammer head and the width of overlap area are specified. Fig. 5. Schematic diagram of the design guideline for stitching. 5

6 Unit: µm Table II. Design guideline of the stitching. Label Critical Layers (193 nm) Implants (248 nm) Non-critical layers (365 nm) Recommended Pattern Stitching Design NA No-Recommended Pattern Stitching Design NA Minimum Pattern Minimum DR A 0:2 0:5 1:0 No-stitching Space to Stitching Cut Line B 0:25 0:5 0:5 Overlap Area Width C ¼ 0:05 ¼ 0:1 ¼ 0:2 Hammer Head Width D MinDR þ 0:05 MinDR þ 0:02 MinDR þ 0:01 Hammer Head Length E ¼ 0:1 ¼ 0:1 ¼ 0:1 Minimum Space between Line F MinDR MinDR MinDR We use the design rule to find all parts of the layout that have spacing violations with neighboring features and reassigned these violating parts. The fine tuning layout is also implemented on the stitching friendly design guideline. Layout snippets of M1 are shown in Fig. 6, left one is the original pixel design and right one is the optimized pixel design. Details of the differences between their architectures are marked in the gray dotted box, where we have applied some changes in. Fig. 6. Layout snippets of results of the proposed decomposition methodology applied to regular M1 (Left) and optimized pixel design of M1 (right). 4 Stitched CIS: Leveraging stitching capability 4.1 Correction model Although our approach is improved over the native approach in separate steps, it still has chances to fail in many cases: lens distortion, wafer thermal expansion and other tool properties. These errors will give rise to distortions of patterns on the wafer. In order to solve those problems, we used a correction model to quantitate the stitching overlay, and then predicted and corrected the stitching performance. The correction model is a higher-order, non-linear model and parameterize the six degrees of freedom of intra-field corrections as a function of the exposure position. Test reticles were used in steps below: Select an amount of test patterns to measure the overlay for each exposure on the wafer. 6

7 Average the overlay residuals from the measured wafers and use the 6 intrafield model to caculate these residuals (equals to corrections per exposure). Apply the corrections per exposure in nest lot. In the 6 intra-field model, distortions were described as six corrections: translation T x, T y ; magnification M s and asymmetrical magnification M a ; rotation R s and asymmetrical rotation R a. They could be written as the function of the exposure coordinates: T x ðx i ;y i Þ¼ m;n T xm;n x n i ym i ; T y ðx i ;y i Þ¼ m;n T ym;n x n i ym i ; R a ðx i ;y i Þ¼ m;n R am;n x n i ym i ; R s ðx i ;y i Þ¼ m;n R sm;n x n i ym i ; M a ðx i ;y i Þ¼ m;n M am;n x n i ym i ; M s ðx i ;y i Þ¼ m;n M sm;n x n i ym i ; Where ðx i ;y i Þ represent the coordinates of the center in exposure field i, and m; n ¼ 0; 1; 2; 3.were the integral power of polynomial, every polynomial included linear and nonlinear corrections, the higher order will be truncated depends on the requirement of calculation precision. We used a vector diagram to show the magnification and rotation in Fig. 7, the red arrows indicated the two types of distortion. Fig. 7. Vector diagram shows the distortion of magnification (Left) and rotation (Right). Corresponding to Fig. 7, stitched overlay was defined as XX, XY, YX, YY to compute indicators for every target location. XX component means X stitching of left-right adjacent fields; XY component means X stitching of left-right adjacent fields; YX component means Y stitching of top-bottom adjacent fields; YY component means Y stitching of top-bottom adjacent fields. 4.2 Results and discussion We calculated the corrections per exposure after first run, and made compensation in slot #1, #2. Then, the results of first compensation were used to calculate the offsets to receive the second compensation in slot #1, #2. Finally, we applied these compensation to all the slots. The comparison of the results between first run and after compensation was shown as Fig. 8. The values of OVL were decreased by 23%(x direction) and 41%(y direction) in average. 7

8 IEICE Electronics Express, Vol.13, No.15, 1 11 Fig. 8. Comparison of the test reticle results in first run and after compensation, vertical is the stitching OVL in nanometer and horizontal is the slot number for wafer. Based on a series of experiments and analysis, this overlay control approach using correctables generated from the overlay metrology system effectively reduce the distortion. As an example, the results of AA layer stitching overlay were shown in Fig. 9. The horizontal represents the number of wafer slot while the vertical represents stitching-ovl, the four components of stitching-ovl were all in 8 nm. Fig Results of the four components stitching OVL of AA layer. Stitched CIS: Experiments and results The proposed sensor was designed and implemented on a µm CMOS process with stitching techniques. A CIS, 28:3 mm 38:8 mm, 42 Mega pixels, had been demonstrated on 12 inch silicon wafer. In Fig. 10a, we take the AA layer as an example, the white thin line along the horizontal and the longitudinal marked the 8

9 location of the stitching. We use the dotted line circled the area that has a stitching line throughout ð1; 2; 3Þ and the normal area non through of stitching ð4; 5; 6Þ; Fig. 10. Pixel area stitching image of AA layer. Fig. 10(Right) shows the SEM image around stitched and normal area. The corresponding stitched region is indicated by dotted circle in Fig. 10(left). We compared the area with stitching line and the area without stitching line, as shown in Table III, the CDs deviation is in the scope of the tolerance. Table III. The CD of x and y direction according to the position in SEM-image X Space (nm) Y Space (nm) X Space (nm) Y Space (nm) Fig. 11. Layout snippets and SEM image of M1 in horizontal and vertical stitching area. The SEM image of stitching in horizontal and vertical are shown in Fig. 11 with the layout snippets, areas in opposite side of the stitching line were painted with different colors. A complete chip is shown in Fig. 12, use Pin Grid Array Package with SPI interface: 9

10 Fig. 12. Photograph of the sensors fabricated on 12 inch wafer and the 28.3 mm 38.8 mm, 42 Mega pixels CMOS Imaging Sensor. A test for the uniform of the CIS was implemented and the raw, reproduced image taken by this CIS is shown in Fig. 13. Table IV. The performance of the proposed detector. Pixel Size (after shrink) µm 5.67 µm Parameter Test mv/s@25 C 2.8 mv/s@60 C 80.1 Dark Current pa/cm C 32.6 pa/cm C 934 Full Well Change e Sensitivity V/lx.s@540 nm 2.8 V out Swing V 1.99 Blue 0.55 Spectral Characteristics Green 0.54 Red 0.56 Signal Noise Ratio (SNR/Max.) db 46.7 FD Conversion Gain uv/e 42.7 Dynamic Range db 76.4 Noise Floor mv 0.3 Fig. 13. Raw, reproduced image taken by CIS. The performance of the proposed detector is summarized in Table IV. Meanwhile, in order to verify the feasibility and capability, 203ðv:Þ179ðh:Þ, almost the biggest sensor can be made on the 12 inch wafer, 1.8 Billion pixels CIS was also demonstrated, shown in Fig. 14. The example of stitching pixel array and corresponding wafer image was checked and no physical issues found. 10

11 Fig. 14. A huge area, 203 mm 179 mm, 1.8 Billion pixels CIS (Left: A photograph of the exposure shot map placement and the sensor fabricated on 12 inch; Right: the corresponding wafer image.) Acknowledgment The project is the cooperation with Shanghai Integrated Circuit Research Development Center, Shanghai Huali Microelectronics Corporation and Fudan University. There are so many specialists who had done huge important contributions for the project. The technical team has worked closely and efficiently, which is the most important guarantee for the success. 11